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Fixed sign parsing for ac_fixed and ac_int (#727)
* fix sign parsing for ac_fixed and ac_int * add a lower for false comparison in ac_fixed/int parsing, simplify logic * update precision parsing * add some comments * remove print
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2 files changed

+37
-2
lines changed

2 files changed

+37
-2
lines changed

hls4ml/backends/fpga/fpga_backend.py

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -342,14 +342,20 @@ def _convert_ac_type(cls, precision):
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integer = int(bits[1])
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fields = 2
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if len(bits) > 2:
345-
signed = bool(bits[2])
345+
# only if the third argument is false or 0, set signed to False
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# (default is True)
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if bits[2].strip().lower() in ['false', '0']:
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signed = False
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fields = 3
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elif 'int' in precision:
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width = int(bits[0])
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integer = width
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fields = 1
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if len(bits) > 1:
352-
signed = bool(bits[1])
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# only if the second argument is false or 0, set signed to False
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# (default is True)
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if bits[1].strip().lower() in ['false', '0']:
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signed = False
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fields = 2
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if len(bits) > fields:
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round_mode = bits[fields]

test/pytest/test_precision_parsing.py

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
import pytest
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import hls4ml
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@pytest.mark.parametrize(
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'prec_pair',
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[
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('ap_fixed<3, 2>', True),
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('ap_ufixed<3, 2>', False),
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('ac_fixed<3, 2, true>', True),
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('ac_fixed<3, 2, false>', False),
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('ac_fixed<3, 2, 1>', True),
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('ac_fixed<3, 2, 0>', False),
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('ap_int<3, 2>', True),
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('ap_uint<3>', False),
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('ac_int<3, TRue>', True),
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('ac_int<3, FALse>', False),
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('ac_int<3, 1>', True),
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('ac_int<3, 0>', False),
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],
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)
23+
def test_sign_parsing(prec_pair):
24+
'''Test that convert_precions_string determines the signedness correctly'''
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strprec = prec_pair[0]
26+
signed = prec_pair[1]
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28+
evalprec = hls4ml.backends.fpga.fpga_backend.FPGABackend.convert_precision_string(strprec)
29+
assert evalprec.signed == signed

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