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print_vivado_report function for nicer reports (#730)
* print_vivado_report function for fancier reports * Fancy reports (#51) * fix uram divide by 0 * add test * fix parsing of vsynth in 2020.1; add test * Update test_report.py * exclude pregenerated reports --------- Co-authored-by: Javier Duarte <[email protected]>
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‎.pre-commit-config.yaml

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exclude: ^hls4ml\/templates\/(vivado|quartus)\/(ap_types|ac_types)\/
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exclude: (^hls4ml\/templates\/(vivado|quartus)\/(ap_types|ac_types)\/|^test/pytest/test_report/)
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repos:
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- repo: https://github.com/psf/black

‎hls4ml/report/__init__.py

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from __future__ import absolute_import
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from hls4ml.report.vivado_report import read_vivado_report
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from hls4ml.report.vivado_report import parse_vivado_report
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from hls4ml.report.quartus_report import read_quartus_report
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from hls4ml.report.quartus_report import parse_quartus_report
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from hls4ml.report.quartus_report import parse_quartus_report # noqa: F401
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from hls4ml.report.quartus_report import read_quartus_report # noqa: F401
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from hls4ml.report.vivado_report import parse_vivado_report # noqa: F401
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from hls4ml.report.vivado_report import print_vivado_report # noqa: F401
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from hls4ml.report.vivado_report import read_vivado_report # noqa: F401

‎hls4ml/report/vivado_report.py

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‎test/pytest/test_report.py

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import os
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import shutil
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from pathlib import Path
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import pytest
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from tensorflow.keras.layers import Dense
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from tensorflow.keras.models import Sequential
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import hls4ml
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test_root_path = Path(__file__).parent
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@pytest.mark.parametrize('backend', ['Vivado'])
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def test_report(backend, capsys):
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model = Sequential()
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model.add(Dense(5, input_shape=(16,), name='fc1', activation='relu'))
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config = hls4ml.utils.config_from_keras_model(model, granularity='model')
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output_dir = str(test_root_path / f'hls4mlprj_report_{backend}')
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hls_model = hls4ml.converters.convert_from_keras_model(
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model, io_type='io_stream', hls_config=config, output_dir=output_dir, part='xc7z020clg400-1', backend=backend
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)
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hls_model.write()
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# to actually generate the reports (using Vivado 2020.1)
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# hls_model.build(synth=True, vsynth=True)
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# copy pregenerated reports
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os.makedirs(f'hls4mlprj_report_{backend}/myproject_prj/solution1/syn/report', exist_ok=True)
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shutil.copy('test_report/vivado_hls.app', f'{output_dir}/myproject_prj/vivado_hls.app')
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shutil.copy('test_report/myproject_csynth.rpt', f'{output_dir}/myproject_prj/solution1/syn/report/myproject_csynth.rpt')
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shutil.copy('test_report/myproject_csynth.xml', f'{output_dir}/myproject_prj/solution1/syn/report/myproject_csynth.xml')
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shutil.copy('test_report/vivado_synth.rpt', f'{output_dir}/vivado_synth.rpt')
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report = hls4ml.report.parse_vivado_report(output_dir) # or report = hls_model.build(...)
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capsys.readouterr() # capture to clear
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hls4ml.report.print_vivado_report(report)
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captured = capsys.readouterr() # capture again to test
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assert (
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captured.out
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== '\n'
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+ '======================================================\n'
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+ '== C Synthesis report\n'
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+ '======================================================\n\n'
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+ ' - Performance estimates:\n'
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+ ' Best-case latency: 10 (50.0 ns)\n'
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+ ' Worst-case latency: 10 (50.0 ns)\n'
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+ ' Interval Min: 8\n'
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+ ' Interval Max: 8\n'
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+ ' Estimated Clock Period: 4.049\n\n'
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+ ' - Resource estimates:\n'
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+ ' BRAM_18K: 0 / 280 (0.0%)\n'
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+ ' DSP48E: 73 / 220 (33.2%)\n'
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+ ' FF: 7969 / 106400 (7.5%)\n'
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+ ' LUT: 2532 / 53200 (4.8%)\n'
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+ ' URAM: N/A\n\n'
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+ '======================================================\n'
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+ '== Vivado Synthesis report\n'
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+ '======================================================\n\n'
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+ ' - Resource utilization:\n'
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+ ' BRAM_18K: 0\n'
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+ ' DSP48E: 66\n'
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+ ' FF: 2428\n'
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+ ' LUT: 1526\n'
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+ ' URAM: N/A\n\n'
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)

‎test/pytest/test_report/myproject_csynth.rpt

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================================================================
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== Vivado HLS Report for 'myproject'
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================================================================
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* Date: Sat Mar 18 22:59:37 2023
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* Version: 2020.1 (Build 2897737 on Wed May 27 20:21:37 MDT 2020)
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* Project: myproject_prj
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* Solution: solution1
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* Product family: zynq
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* Target device: xc7z020-clg400-1
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================================================================
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== Performance Estimates
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================================================================
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+ Timing:
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* Summary:
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+--------+---------+----------+------------+
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| Clock | Target | Estimated| Uncertainty|
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+--------+---------+----------+------------+
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|ap_clk | 5.00 ns | 4.049 ns | 0.62 ns |
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+--------+---------+----------+------------+
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+ Latency:
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* Summary:
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+---------+---------+-----------+-----------+-----+-----+----------+
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| Latency (cycles) | Latency (absolute) | Interval | Pipeline |
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| min | max | min | max | min | max | Type |
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+---------+---------+-----------+-----------+-----+-----+----------+
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| 10| 10| 50.000 ns | 50.000 ns | 8| 8| dataflow |
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+---------+---------+-----------+-----------+-----+-----+----------+
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+ Detail:
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* Instance:
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+-----------------------------------------------------+----------------------------------------------------+---------+---------+-----------+-----------+-----+-----+----------+
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| | | Latency (cycles) | Latency (absolute) | Interval | Pipeline |
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| Instance | Module | min | max | min | max | min | max | Type |
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+-----------------------------------------------------+----------------------------------------------------+---------+---------+-----------+-----------+-----+-----+----------+
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|dense_array_array_ap_fixed_16_6_5_3_0_5u_config2_U0 |dense_array_array_ap_fixed_16_6_5_3_0_5u_config2_s | 7| 7| 35.000 ns | 35.000 ns | 7| 7| none |
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|relu_array_array_ap_fixed_5u_relu_config3_U0 |relu_array_array_ap_fixed_5u_relu_config3_s | 2| 2| 10.000 ns | 10.000 ns | 1| 1| function |
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+-----------------------------------------------------+----------------------------------------------------+---------+---------+-----------+-----------+-----+-----+----------+
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* Loop:
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N/A
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================================================================
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== Utilization Estimates
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================================================================
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* Summary:
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+-----------------+---------+-------+--------+-------+-----+
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| Name | BRAM_18K| DSP48E| FF | LUT | URAM|
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+-----------------+---------+-------+--------+-------+-----+
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|DSP | -| -| -| -| -|
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|Expression | -| -| 0| 2| -|
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|FIFO | 0| -| 25| 140| -|
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|Instance | 0| 73| 7944| 2390| -|
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|Memory | -| -| -| -| -|
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|Multiplexer | -| -| -| -| -|
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|Register | -| -| -| -| -|
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+-----------------+---------+-------+--------+-------+-----+
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|Total | 0| 73| 7969| 2532| 0|
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+-----------------+---------+-------+--------+-------+-----+
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|Available | 280| 220| 106400| 53200| 0|
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+-----------------+---------+-------+--------+-------+-----+
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|Utilization (%) | 0| 33| 7| 4| 0|
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+-----------------+---------+-------+--------+-------+-----+
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+ Detail:
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* Instance:
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+-----------------------------------------------------+----------------------------------------------------+---------+-------+------+------+-----+
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| Instance | Module | BRAM_18K| DSP48E| FF | LUT | URAM|
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+-----------------------------------------------------+----------------------------------------------------+---------+-------+------+------+-----+
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|dense_array_array_ap_fixed_16_6_5_3_0_5u_config2_U0 |dense_array_array_ap_fixed_16_6_5_3_0_5u_config2_s | 0| 73| 7860| 2134| 0|
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|relu_array_array_ap_fixed_5u_relu_config3_U0 |relu_array_array_ap_fixed_5u_relu_config3_s | 0| 0| 84| 256| 0|
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+-----------------------------------------------------+----------------------------------------------------+---------+-------+------+------+-----+
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|Total | | 0| 73| 7944| 2390| 0|
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+-----------------------------------------------------+----------------------------------------------------+---------+-------+------+------+-----+
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* DSP48E:
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N/A
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* Memory:
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N/A
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* FIFO:
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+-------------------------+---------+---+----+-----+------+-----+---------+
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| Name | BRAM_18K| FF| LUT| URAM| Depth| Bits| Size:D*B|
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+-------------------------+---------+---+----+-----+------+-----+---------+
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|layer2_out_V_data_0_V_U | 0| 5| 0| -| 1| 16| 16|
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|layer2_out_V_data_1_V_U | 0| 5| 0| -| 1| 16| 16|
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|layer2_out_V_data_2_V_U | 0| 5| 0| -| 1| 16| 16|
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|layer2_out_V_data_3_V_U | 0| 5| 0| -| 1| 16| 16|
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|layer2_out_V_data_4_V_U | 0| 5| 0| -| 1| 16| 16|
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+-------------------------+---------+---+----+-----+------+-----+---------+
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|Total | 0| 25| 0| 0| 5| 80| 80|
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+-------------------------+---------+---+----+-----+------+-----+---------+
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* Expression:
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+--------------+----------+-------+---+----+------------+------------+
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| Variable Name| Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1|
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+--------------+----------+-------+---+----+------------+------------+
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|ap_idle | and | 0| 0| 2| 1| 1|
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+--------------+----------+-------+---+----+------------+------------+
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|Total | | 0| 0| 2| 1| 1|
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+--------------+----------+-------+---+----+------------+------------+
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* Multiplexer:
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N/A
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* Register:
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N/A
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================================================================
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== Interface
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================================================================
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* Summary:
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+------------------------------+-----+-----+------------+-----------------------+--------------+
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| RTL Ports | Dir | Bits| Protocol | Source Object | C Type |
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+------------------------------+-----+-----+------------+-----------------------+--------------+
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|fc1_input_V_data_0_V_TDATA | in | 16| axis | fc1_input_V_data_0_V | pointer |
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|fc1_input_V_data_0_V_TVALID | in | 1| axis | fc1_input_V_data_0_V | pointer |
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|fc1_input_V_data_0_V_TREADY | out | 1| axis | fc1_input_V_data_0_V | pointer |
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|fc1_input_V_data_1_V_TDATA | in | 16| axis | fc1_input_V_data_1_V | pointer |
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|fc1_input_V_data_1_V_TVALID | in | 1| axis | fc1_input_V_data_1_V | pointer |
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|fc1_input_V_data_1_V_TREADY | out | 1| axis | fc1_input_V_data_1_V | pointer |
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|fc1_input_V_data_2_V_TDATA | in | 16| axis | fc1_input_V_data_2_V | pointer |
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|fc1_input_V_data_2_V_TVALID | in | 1| axis | fc1_input_V_data_2_V | pointer |
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|fc1_input_V_data_2_V_TREADY | out | 1| axis | fc1_input_V_data_2_V | pointer |
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|fc1_input_V_data_3_V_TDATA | in | 16| axis | fc1_input_V_data_3_V | pointer |
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|fc1_input_V_data_3_V_TVALID | in | 1| axis | fc1_input_V_data_3_V | pointer |
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|fc1_input_V_data_3_V_TREADY | out | 1| axis | fc1_input_V_data_3_V | pointer |
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|fc1_input_V_data_4_V_TDATA | in | 16| axis | fc1_input_V_data_4_V | pointer |
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|fc1_input_V_data_4_V_TVALID | in | 1| axis | fc1_input_V_data_4_V | pointer |
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|fc1_input_V_data_4_V_TREADY | out | 1| axis | fc1_input_V_data_4_V | pointer |
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|fc1_input_V_data_5_V_TDATA | in | 16| axis | fc1_input_V_data_5_V | pointer |
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|fc1_input_V_data_5_V_TVALID | in | 1| axis | fc1_input_V_data_5_V | pointer |
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|fc1_input_V_data_5_V_TREADY | out | 1| axis | fc1_input_V_data_5_V | pointer |
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|fc1_input_V_data_6_V_TDATA | in | 16| axis | fc1_input_V_data_6_V | pointer |
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|fc1_input_V_data_6_V_TVALID | in | 1| axis | fc1_input_V_data_6_V | pointer |
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|fc1_input_V_data_6_V_TREADY | out | 1| axis | fc1_input_V_data_6_V | pointer |
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|fc1_input_V_data_7_V_TDATA | in | 16| axis | fc1_input_V_data_7_V | pointer |
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|fc1_input_V_data_7_V_TVALID | in | 1| axis | fc1_input_V_data_7_V | pointer |
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|fc1_input_V_data_7_V_TREADY | out | 1| axis | fc1_input_V_data_7_V | pointer |
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|fc1_input_V_data_8_V_TDATA | in | 16| axis | fc1_input_V_data_8_V | pointer |
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|fc1_input_V_data_8_V_TVALID | in | 1| axis | fc1_input_V_data_8_V | pointer |
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|fc1_input_V_data_8_V_TREADY | out | 1| axis | fc1_input_V_data_8_V | pointer |
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|fc1_input_V_data_9_V_TDATA | in | 16| axis | fc1_input_V_data_9_V | pointer |
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|fc1_input_V_data_9_V_TVALID | in | 1| axis | fc1_input_V_data_9_V | pointer |
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|fc1_input_V_data_9_V_TREADY | out | 1| axis | fc1_input_V_data_9_V | pointer |
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|fc1_input_V_data_10_V_TDATA | in | 16| axis | fc1_input_V_data_10_V | pointer |
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|fc1_input_V_data_10_V_TVALID | in | 1| axis | fc1_input_V_data_10_V | pointer |
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|fc1_input_V_data_10_V_TREADY | out | 1| axis | fc1_input_V_data_10_V | pointer |
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|fc1_input_V_data_11_V_TDATA | in | 16| axis | fc1_input_V_data_11_V | pointer |
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|fc1_input_V_data_11_V_TVALID | in | 1| axis | fc1_input_V_data_11_V | pointer |
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|fc1_input_V_data_11_V_TREADY | out | 1| axis | fc1_input_V_data_11_V | pointer |
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|fc1_input_V_data_12_V_TDATA | in | 16| axis | fc1_input_V_data_12_V | pointer |
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|fc1_input_V_data_12_V_TVALID | in | 1| axis | fc1_input_V_data_12_V | pointer |
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|fc1_input_V_data_12_V_TREADY | out | 1| axis | fc1_input_V_data_12_V | pointer |
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|fc1_input_V_data_13_V_TDATA | in | 16| axis | fc1_input_V_data_13_V | pointer |
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|fc1_input_V_data_13_V_TVALID | in | 1| axis | fc1_input_V_data_13_V | pointer |
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|fc1_input_V_data_13_V_TREADY | out | 1| axis | fc1_input_V_data_13_V | pointer |
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|fc1_input_V_data_14_V_TDATA | in | 16| axis | fc1_input_V_data_14_V | pointer |
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|fc1_input_V_data_14_V_TVALID | in | 1| axis | fc1_input_V_data_14_V | pointer |
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|fc1_input_V_data_14_V_TREADY | out | 1| axis | fc1_input_V_data_14_V | pointer |
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|fc1_input_V_data_15_V_TDATA | in | 16| axis | fc1_input_V_data_15_V | pointer |
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|fc1_input_V_data_15_V_TVALID | in | 1| axis | fc1_input_V_data_15_V | pointer |
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|fc1_input_V_data_15_V_TREADY | out | 1| axis | fc1_input_V_data_15_V | pointer |
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|layer3_out_V_data_0_V_TDATA | out | 16| axis | layer3_out_V_data_0_V | pointer |
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|layer3_out_V_data_0_V_TVALID | out | 1| axis | layer3_out_V_data_0_V | pointer |
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|layer3_out_V_data_0_V_TREADY | in | 1| axis | layer3_out_V_data_0_V | pointer |
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|layer3_out_V_data_1_V_TDATA | out | 16| axis | layer3_out_V_data_1_V | pointer |
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|layer3_out_V_data_1_V_TVALID | out | 1| axis | layer3_out_V_data_1_V | pointer |
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|layer3_out_V_data_1_V_TREADY | in | 1| axis | layer3_out_V_data_1_V | pointer |
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|layer3_out_V_data_2_V_TDATA | out | 16| axis | layer3_out_V_data_2_V | pointer |
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|layer3_out_V_data_2_V_TVALID | out | 1| axis | layer3_out_V_data_2_V | pointer |
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|layer3_out_V_data_2_V_TREADY | in | 1| axis | layer3_out_V_data_2_V | pointer |
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|layer3_out_V_data_3_V_TDATA | out | 16| axis | layer3_out_V_data_3_V | pointer |
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|layer3_out_V_data_3_V_TVALID | out | 1| axis | layer3_out_V_data_3_V | pointer |
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|layer3_out_V_data_3_V_TREADY | in | 1| axis | layer3_out_V_data_3_V | pointer |
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|layer3_out_V_data_4_V_TDATA | out | 16| axis | layer3_out_V_data_4_V | pointer |
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|layer3_out_V_data_4_V_TVALID | out | 1| axis | layer3_out_V_data_4_V | pointer |
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|layer3_out_V_data_4_V_TREADY | in | 1| axis | layer3_out_V_data_4_V | pointer |
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|ap_clk | in | 1| ap_ctrl_hs | myproject | return value |
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|ap_rst_n | in | 1| ap_ctrl_hs | myproject | return value |
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|ap_start | in | 1| ap_ctrl_hs | myproject | return value |
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|ap_done | out | 1| ap_ctrl_hs | myproject | return value |
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|ap_ready | out | 1| ap_ctrl_hs | myproject | return value |
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|ap_idle | out | 1| ap_ctrl_hs | myproject | return value |
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+------------------------------+-----+-----+------------+-----------------------+--------------+
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