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Merge pull request #924 from fastmachinelearning/vu13p
Update default FPGA part number from KU115 to VU13P
2 parents 14f06d5 + 2240b42 commit d9391dd

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docs/api/configuration.rst

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@@ -70,7 +70,7 @@ It looks like this:
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OutputPredictions: keras/KERAS_3layer_predictions.dat
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# Backend section (Vivado backend)
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Part: xcku115-flvb2104-2-i
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Part: xcvu13p-flga2577-2-e
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ClockPeriod: 5
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IOType: io_parallel # options: io_parallel/io_stream
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@@ -97,7 +97,7 @@ There are a number of configuration options that you have. Let's go through the
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The backend-specific section of the configuration depends on the backend. You can get a starting point for the necessary settings using, for example `hls4ml.templates.get_backend('Vivado').create_initial_config()`.
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For Vivado backend the options are:
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* **Part**\ : the particular FPGA part number that you are considering, here it's a Xilinx Virtex-7 FPGA
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* **Part**\ : the particular FPGA part number that you are considering, here it's a Xilinx Virtex UltraScale+ VU13P FPGA
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* **ClockPeriod**\ : the clock period, in ns, at which your algorithm runs
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Then you have some optimization parameters for how your algorithm runs:
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* **IOType**\ : your options are ``io_parallel`` or ``io_stream`` which defines the type of data structure used for inputs, intermediate activations between layers, and outputs. For ``io_parallel``, arrays are used that, in principle, can be fully unrolled and are typically implemented in RAMs. For ``io_stream``, HLS streams are used, which are a more efficient/scalable mechanism to represent data that are produced and consumed in a sequential manner. Typically, HLS streams are implemented with FIFOs instead of RAMs. For more information see `here <https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/pragma-HLS-stream>`__.

hls4ml/backends/vivado/vivado_backend.py

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@@ -175,10 +175,10 @@ def get_default_flow(self):
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def get_writer_flow(self):
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return self._writer_flow
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def create_initial_config(self, part='xcku115-flvb2104-2-i', clock_period=5, io_type='io_parallel'):
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def create_initial_config(self, part='xcvu13p-flga2577-2-e', clock_period=5, io_type='io_parallel'):
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config = {}
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config['Part'] = part if part is not None else 'xcku115-flvb2104-2-i'
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config['Part'] = part if part is not None else 'xcvu13p-flga2577-2-e'
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config['ClockPeriod'] = clock_period
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config['IOType'] = io_type
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config['HLSConfig'] = {}

hls4ml/converters/__init__.py

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KerasH5: my_keras_model.h5
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OutputDir: my-hls-test
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ProjectName: myproject
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Part: xcku115-flvb2104-2-i
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Part: xcvu13p-flga2577-2-e
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ClockPeriod: 5
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IOType: io_stream
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HLSConfig:

scripts/hls4ml

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)
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config_parser.add_argument('-p', '--project', help='Project name', default='myproject')
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config_parser.add_argument('-d', '--dir', help='Project output directory', default='my-hls-test')
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config_parser.add_argument('-f', '--fpga', help='FPGA part', default='xcku115-flvb2104-2-i')
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config_parser.add_argument('-f', '--fpga', help='FPGA part', default='xcvu13p-flga2577-2-e')
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config_parser.add_argument('-bo', '--board', help='Board used.', default='pynq-z2')
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config_parser.add_argument(
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'-ba', '--backend', help='Backend to use (Vivado, VivadoAccelerator, Quartus)', default='Vivado'

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