Neural network in the FPGA not having the same results as in the simulations

[aabueno]

Hi!
I am using HLS4ML to create a CNN to classify 32x64 images with about 29000 parameters. In the simulations, it works fine, with all classes being correctly classified. But, when I try to put my Neural Network on the FPGA, no matter what image is input, the output is always the same class. Anyone has got something like this?
I am using Xilinx Vivado 2020.1 to compile and a ZynqMP SoC ZCU106 board to test

[bo3z]

What backend are you using? VivadoAccelerator or are you integrating the IP to the FPGA in a custom manner?

[bo3z]

Try reversing the order of input bits (this is something I've seen in Vitis HLS; I don't think this is specific to hls4ml).

So the input to your IP block (the top-level function from Verilog) is one big bus of width = number_of_inputs x input_precision (for example, for 16 inputs with 16 bits precision, like the hls4ml starter example, your input bus would be 256 bits wide). But what I've seen in the past is the after HLS compilation the order of bits needs to be reversed. Now I've only done this when the input precision is 1 bit, so reversing the entire input signal is okay. If you're precision is greater than 1 bit I am not sure what the correct order of operations might be. It could be concatenate individual inputs into one large bus then reverse or reverse bits of individual bits and then concatenate. You might have to experiment with this a bit.

[aabueno]

It doesn't seem to be that, I mean, it works on simulation but not on the real circuit. Wouldn't that change on simulation too?

[bo3z]

Yes and no. Remember, in simulation there is a testbench written in C++ that passes the inputs to the simulated RTL. When working with the IP it's really up to the developer to make sure everything is connected properly, the inputs as well as the control logic. Have you made sure all the hand-shake signals (ap_done, ap_valid etc.) are correctly connected and driven by some appropriate logic?

[aabueno]

I am sorry, I think I haven't been clear. I have done rtl simulation in Vivado using the verilog code I encounter on the impl folder plus other code I use to deliver data to the neural network. In this simulation, everything works fine. But, when I use the same code on the FPGA, the results are wrong (no matter what class I put on the input, the output is always the same)

[bo3z]

Thanks, now I understand. This is now unfortunately a bug outside of hls4ml, most likely (as you say C++ simulation, HLS simulation and your custom RTL simulation are all correct). This could be any number of issues such as pin assignment on the FPGA or similar. Have you tried adding some Integrated Logic Analyzers (ILAs) to your design and probing the values of control signals?

[gaofengfeng]

I met the same problem, by reversing the whole row of the input data and proper set of ap_hs, it works well.

• beckend: vivado 2018.3
• ML model: 1layer MLP.
• 20 features
• input configure: config['LayerName']['fc1_input']['Precision']['result'] = 'ap_fixed<8,8>'.

Normal order(hex）: 0507151E1613170E11100F0D060B0708050C0704
after reversing the whole row：04070C0508070B060D0F10110E1713161E150705