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internal/simdgen: add EXTRACT[IF]128 instructions
This generates dev.simd CL 684115 Change-Id: Ibb8e77e40c426b2cf3dd73c996e5118d5fd5afff Reviewed-on: https://go-review.googlesource.com/c/arch/+/684080 LUCI-TryBot-Result: Go LUCI <[email protected]> Reviewed-by: Junyang Shao <[email protected]>
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4 files changed

+146
-28
lines changed

4 files changed

+146
-28
lines changed

‎internal/simdgen/categories.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -550,6 +550,11 @@
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extension: "AVX.*"
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documentation: !string |-
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// Set128 combines a 128-bit vector with a 256-bit vector, where the constant operand specifies whether the low (0) or high (1) half is receives the smaller vector.
553+
- go: Get128
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commutative: "false"
555+
extension: "AVX.*"
556+
documentation: !string |-
557+
// Get128 retrieves the upper (1) or lower (0) half of a 256-bit vector, depending on the constant operand.
553558
- go: Mul
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commutative: "true"
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extension: "AVX.*"

‎internal/simdgen/go.yaml‎

Lines changed: 68 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -776,23 +776,25 @@
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- class: greg
777777
base: $b
778778
lanes: 1 # Scalar, darn it!
779-
- class: immediate
779+
- &imm
780+
class: immediate
780781
immOffset: 0
781782
out:
782783
- *t
784+
783785
- go: GetElem
784786
asm: "VPEXTR[BWDQ]"
785787
in:
786788
- class: vreg
787789
base: $b
788790
elemBits: $e
789-
- class: immediate
790-
immOffset: 0
791+
- *imm
791792
out:
792793
- class: greg
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base: $b
794795
bits: $e
795796

797+
796798
- go: Set128
797799
asm: "VINSERTI128"
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in:
@@ -806,11 +808,20 @@
806808
base: $t
807809
bits: 128
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OverwriteElementBits: 8
809-
- class: immediate
811+
- &imm01 # This immediate should be only 0 or 1
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class: immediate
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immOffset: 0
811814
out:
812815
- *i8x32
813816

817+
- go: Get128
818+
asm: "VEXTRACTI128"
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in:
820+
- *i8x32
821+
- *imm01
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out:
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- *i8x16
824+
814825
- go: Set128
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asm: "VINSERTI128"
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in:
@@ -824,11 +835,18 @@
824835
base: $t
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bits: 128
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OverwriteElementBits: 16
827-
- class: immediate
828-
immOffset: 0
838+
- *imm01
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out:
830840
- *i16x16
831841

842+
- go: Get128
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asm: "VEXTRACTI128"
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in:
845+
- *i16x16
846+
- *imm01
847+
out:
848+
- *i16x8
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- go: Set128
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asm: "VINSERTI128"
834852
in:
@@ -842,11 +860,18 @@
842860
base: $t
843861
bits: 128
844862
OverwriteElementBits: 32
845-
- class: immediate
846-
immOffset: 0
863+
- *imm01
847864
out:
848865
- *i32x8
849866

867+
- go: Get128
868+
asm: "VEXTRACTI128"
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in:
870+
- *i32x8
871+
- *imm01
872+
out:
873+
- *i32x4
874+
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- go: Set128
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asm: "VINSERTI128"
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in:
@@ -860,11 +885,18 @@
860885
base: $t
861886
bits: 128
862887
OverwriteElementBits: 64
863-
- class: immediate
864-
immOffset: 0
888+
- *imm01
865889
out:
866890
- *i64x4
867891

892+
- go: Get128
893+
asm: "VEXTRACTI128"
894+
in:
895+
- *i64x4
896+
- *imm01
897+
out:
898+
- *i64x2
899+
868900
- go: Set128
869901
asm: "VINSERTF128"
870902
in:
@@ -878,11 +910,18 @@
878910
base: $t
879911
bits: 128
880912
OverwriteElementBits: 32
881-
- class: immediate
882-
immOffset: 0
913+
- *imm01
883914
out:
884915
- *f32x8
885916

917+
- go: Get128
918+
asm: "VEXTRACTF128"
919+
in:
920+
- *f32x8
921+
- *imm01
922+
out:
923+
- *f32x4
924+
886925
- go: Set128
887926
asm: "VINSERTF128"
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in:
@@ -894,10 +933,25 @@
894933
class: vreg
895934
base: $t
896935
bits: 128
897-
- class: immediate
898-
immOffset: 0
936+
- *imm01
899937
out:
900938
- *f64x4
939+
940+
- go: Get128
941+
asm: "VEXTRACTF128"
942+
in:
943+
- *f64x4
944+
- *imm01
945+
out:
946+
- *f64x2
947+
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950+
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901955
# "Normal" multiplication is only available for floats.
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# This only covers the single and double precision.
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- go: Mul

‎internal/simdgen/ops/Moves/categories.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -14,3 +14,8 @@
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extension: "AVX.*"
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documentation: !string |-
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// Set128 combines a 128-bit vector with a 256-bit vector, where the constant operand specifies whether the low (0) or high (1) half is receives the smaller vector.
17+
- go: Get128
18+
commutative: "false"
19+
extension: "AVX.*"
20+
documentation: !string |-
21+
// Get128 retrieves the upper (1) or lower (0) half of a 256-bit vector, depending on the constant operand.

‎internal/simdgen/ops/Moves/go.yaml‎

Lines changed: 68 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -8,23 +8,25 @@
88
- class: greg
99
base: $b
1010
lanes: 1 # Scalar, darn it!
11-
- class: immediate
11+
- &imm
12+
class: immediate
1213
immOffset: 0
1314
out:
1415
- *t
16+
1517
- go: GetElem
1618
asm: "VPEXTR[BWDQ]"
1719
in:
1820
- class: vreg
1921
base: $b
2022
elemBits: $e
21-
- class: immediate
22-
immOffset: 0
23+
- *imm
2324
out:
2425
- class: greg
2526
base: $b
2627
bits: $e
2728

29+
2830
- go: Set128
2931
asm: "VINSERTI128"
3032
in:
@@ -38,11 +40,20 @@
3840
base: $t
3941
bits: 128
4042
OverwriteElementBits: 8
41-
- class: immediate
43+
- &imm01 # This immediate should be only 0 or 1
44+
class: immediate
4245
immOffset: 0
4346
out:
4447
- *i8x32
4548

49+
- go: Get128
50+
asm: "VEXTRACTI128"
51+
in:
52+
- *i8x32
53+
- *imm01
54+
out:
55+
- *i8x16
56+
4657
- go: Set128
4758
asm: "VINSERTI128"
4859
in:
@@ -56,11 +67,18 @@
5667
base: $t
5768
bits: 128
5869
OverwriteElementBits: 16
59-
- class: immediate
60-
immOffset: 0
70+
- *imm01
6171
out:
6272
- *i16x16
6373

74+
- go: Get128
75+
asm: "VEXTRACTI128"
76+
in:
77+
- *i16x16
78+
- *imm01
79+
out:
80+
- *i16x8
81+
6482
- go: Set128
6583
asm: "VINSERTI128"
6684
in:
@@ -74,11 +92,18 @@
7492
base: $t
7593
bits: 128
7694
OverwriteElementBits: 32
77-
- class: immediate
78-
immOffset: 0
95+
- *imm01
7996
out:
8097
- *i32x8
8198

99+
- go: Get128
100+
asm: "VEXTRACTI128"
101+
in:
102+
- *i32x8
103+
- *imm01
104+
out:
105+
- *i32x4
106+
82107
- go: Set128
83108
asm: "VINSERTI128"
84109
in:
@@ -92,11 +117,18 @@
92117
base: $t
93118
bits: 128
94119
OverwriteElementBits: 64
95-
- class: immediate
96-
immOffset: 0
120+
- *imm01
97121
out:
98122
- *i64x4
99123

124+
- go: Get128
125+
asm: "VEXTRACTI128"
126+
in:
127+
- *i64x4
128+
- *imm01
129+
out:
130+
- *i64x2
131+
100132
- go: Set128
101133
asm: "VINSERTF128"
102134
in:
@@ -110,11 +142,18 @@
110142
base: $t
111143
bits: 128
112144
OverwriteElementBits: 32
113-
- class: immediate
114-
immOffset: 0
145+
- *imm01
115146
out:
116147
- *f32x8
117148

149+
- go: Get128
150+
asm: "VEXTRACTF128"
151+
in:
152+
- *f32x8
153+
- *imm01
154+
out:
155+
- *f32x4
156+
118157
- go: Set128
119158
asm: "VINSERTF128"
120159
in:
@@ -126,7 +165,22 @@
126165
class: vreg
127166
base: $t
128167
bits: 128
129-
- class: immediate
130-
immOffset: 0
168+
- *imm01
131169
out:
132170
- *f64x4
171+
172+
- go: Get128
173+
asm: "VEXTRACTF128"
174+
in:
175+
- *f64x4
176+
- *imm01
177+
out:
178+
- *f64x2
179+
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