cmd/compile/internal/ssa: combine shift and addition for riscv64 rva22u64

When GORISCV64 enables rva22u64, combined shift and addition using the
SH1ADD, SH2ADD and SH3ADD instructions that are available via the Zba
extension. This results in more than 2000 instructions being removed
from the Go binary on riscv64.

Change-Id: Ia62ae7dda3d8083cff315113421bee73f518eea8
Reviewed-on: https://go-review.googlesource.com/c/go/+/606636
LUCI-TryBot-Result: Go LUCI <[email protected]>
Reviewed-by: Mark Ryan <[email protected]>
Reviewed-by: Michael Pratt <[email protected]>
Reviewed-by: Cherry Mui <[email protected]>
Reviewed-by: Meng Zhuo <[email protected]>

Author: 4a6f656c

src/cmd/compile/internal/riscv64/ssa.go

@@ -289,7 +289,8 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
 		ssa.OpRISCV64FEQS, ssa.OpRISCV64FNES, ssa.OpRISCV64FLTS, ssa.OpRISCV64FLES,
 		ssa.OpRISCV64FADDD, ssa.OpRISCV64FSUBD, ssa.OpRISCV64FMULD, ssa.OpRISCV64FDIVD,
 		ssa.OpRISCV64FEQD, ssa.OpRISCV64FNED, ssa.OpRISCV64FLTD, ssa.OpRISCV64FLED, ssa.OpRISCV64FSGNJD,
-		ssa.OpRISCV64MIN, ssa.OpRISCV64MAX, ssa.OpRISCV64MINU, ssa.OpRISCV64MAXU:
+		ssa.OpRISCV64MIN, ssa.OpRISCV64MAX, ssa.OpRISCV64MINU, ssa.OpRISCV64MAXU,
+		ssa.OpRISCV64SH1ADD, ssa.OpRISCV64SH2ADD, ssa.OpRISCV64SH3ADD:
 		r := v.Reg()
 		r1 := v.Args[0].Reg()
 		r2 := v.Args[1].Reg()

src/cmd/compile/internal/ssa/_gen/RISCV64.rules

@@ -839,6 +839,11 @@
 // Optimisations for rva22u64 and above.
 //
 
+// Combine left shift and addition.
+(ADD (SLLI [1] x) y) && buildcfg.GORISCV64 >= 22 => (SH1ADD x y)
+(ADD (SLLI [2] x) y) && buildcfg.GORISCV64 >= 22 => (SH2ADD x y)
+(ADD (SLLI [3] x) y) && buildcfg.GORISCV64 >= 22 => (SH3ADD x y)
+
 // Integer minimum and maximum.
 (Min64  x y) && buildcfg.GORISCV64 >= 22 => (MIN  x y)
 (Max64  x y) && buildcfg.GORISCV64 >= 22 => (MAX  x y)

src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go

@@ -220,6 +220,11 @@ func init() {
 		{name: "SRLI", argLength: 1, reg: gp11, asm: "SRLI", aux: "Int64"},   // arg0 >> auxint, shift amount 0-63, logical right shift
 		{name: "SRLIW", argLength: 1, reg: gp11, asm: "SRLIW", aux: "Int64"}, // arg0 >> auxint, shift amount 0-31, logical right shift of 32 bit value, sign extended to 64 bits
 
+		// Shift and add
+		{name: "SH1ADD", argLength: 2, reg: gp21, asm: "SH1ADD"}, // arg0 << 1 + arg1
+		{name: "SH2ADD", argLength: 2, reg: gp21, asm: "SH2ADD"}, // arg0 << 2 + arg1
+		{name: "SH3ADD", argLength: 2, reg: gp21, asm: "SH3ADD"}, // arg0 << 3 + arg1
+
 		// Bitwise ops
 		{name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true}, // arg0 & arg1
 		{name: "ANDI", argLength: 1, reg: gp11, asm: "ANDI", aux: "Int64"},    // arg0 & auxint

src/cmd/compile/internal/ssa/opGen.go

@@ -520,3 +520,20 @@ func checkShiftToMask(u []uint64, s []int64) {
 	// amd64:-"SHR",-"SHL","ANDQ"
 	u[1] = u[1] << 5 >> 5
 }
+
+//
+// Left shift with addition.
+//
+
+func checkLeftShiftWithAddition(a int64, b int64) int64 {
+	// riscv64/rva20u64: "SLLI","ADD"
+	// riscv64/rva22u64: "SH1ADD"
+	a = a + b<<1
+	// riscv64/rva20u64: "SLLI","ADD"
+	// riscv64/rva22u64: "SH2ADD"
+	a = a + b<<2
+	// riscv64/rva20u64: "SLLI","ADD"
+	// riscv64/rva22u64: "SH3ADD"
+	a = a + b<<3
+	return a
+}