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HiFiPhileHiFiPhile
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Use DMA enable for DCache condition
Signed-off-by: HiFiPhile <[email protected]>
1 parent ffab23c commit 3287cfa

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6 files changed

+18
-29
lines changed

6 files changed

+18
-29
lines changed

‎src/common/tusb_mcu.h

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -220,8 +220,9 @@
220220
#define TUP_RHPORT_HIGHSPEED 1 // Port0: FS, Port1: HS
221221
#endif
222222

223-
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1
224-
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1
223+
// Enable dcache if DMA is enabled
224+
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE
225+
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE
225226
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32
226227

227228
#elif TU_CHECK_MCU(OPT_MCU_STM32H7)
@@ -232,8 +233,9 @@
232233
#define TUP_DCD_ENDPOINT_MAX 9
233234

234235
#if __CORTEX_M == 7
235-
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1
236-
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1
236+
// Enable dcache if DMA is enabled
237+
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE
238+
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE
237239
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32
238240
#endif
239241

@@ -333,8 +335,9 @@
333335
// MCU with on-chip HS Phy
334336
#define TUP_RHPORT_HIGHSPEED 1
335337

336-
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1
337-
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1
338+
// Enable dcache if DMA is enabled
339+
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE
340+
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE
338341
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32
339342

340343
//--------------------------------------------------------------------+

‎src/common/tusb_types.h

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -36,39 +36,39 @@
3636
#endif
3737

3838
//------------- Device DCache declaration -------------//
39-
#define TUD_EPBUF_DCACHE_SIZE(_size) (TUD_EPBUF_DCACHE_ALIGNED ? \
39+
#define TUD_EPBUF_DCACHE_SIZE(_size) (CFG_TUD_MEM_DCACHE_ENABLE ? \
4040
(TU_DIV_CEIL(_size, CFG_TUD_MEM_DCACHE_LINE_SIZE) * CFG_TUD_MEM_DCACHE_LINE_SIZE) : (_size))
4141

4242
// Declare an endpoint buffer with uint8_t[size]
4343
#define TUD_EPBUF_DEF(_name, _size) \
4444
union { \
4545
CFG_TUD_MEM_ALIGN uint8_t _name[_size]; \
46-
TU_ATTR_ALIGNED(TUD_EPBUF_DCACHE_ALIGNED ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(_size)]; \
46+
TU_ATTR_ALIGNED(CFG_TUD_MEM_DCACHE_ENABLE ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(_size)]; \
4747
}
4848

4949
// Declare an endpoint buffer with a type
5050
#define TUD_EPBUF_TYPE_DEF(_type, _name) \
5151
union { \
5252
CFG_TUD_MEM_ALIGN _type _name; \
53-
TU_ATTR_ALIGNED(TUD_EPBUF_DCACHE_ALIGNED ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
53+
TU_ATTR_ALIGNED(CFG_TUD_MEM_DCACHE_ENABLE ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
5454
}
5555

5656
//------------- Host DCache declaration -------------//
57-
#define TUH_EPBUF_DCACHE_SIZE(_size) (TUH_EPBUF_DCACHE_ALIGNED ? \
57+
#define TUH_EPBUF_DCACHE_SIZE(_size) (CFG_TUH_MEM_DCACHE_ENABLE ? \
5858
(TU_DIV_CEIL(_size, CFG_TUH_MEM_DCACHE_LINE_SIZE) * CFG_TUH_MEM_DCACHE_LINE_SIZE) : (_size))
5959

6060
// Declare an endpoint buffer with uint8_t[size]
6161
#define TUH_EPBUF_DEF(_name, _size) \
6262
union { \
6363
CFG_TUH_MEM_ALIGN uint8_t _name[_size]; \
64-
TU_ATTR_ALIGNED(TUH_EPBUF_DCACHE_ALIGNED ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(_size)]; \
64+
TU_ATTR_ALIGNED(CFG_TUH_MEM_DCACHE_ENABLE ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(_size)]; \
6565
}
6666

6767
// Declare an endpoint buffer with a type
6868
#define TUH_EPBUF_TYPE_DEF(_type, _name) \
6969
union { \
7070
CFG_TUH_MEM_ALIGN _type _name; \
71-
TU_ATTR_ALIGNED(TUH_EPBUF_DCACHE_ALIGNED ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
71+
TU_ATTR_ALIGNED(CFG_TUH_MEM_DCACHE_ENABLE ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
7272
}
7373

7474

‎src/portable/synopsys/dwc2/dcd_dwc2.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -88,7 +88,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t dwc2_ep_count(const dwc2_regs_t* dwc
8888
//--------------------------------------------------------------------
8989
// DMA
9090
//--------------------------------------------------------------------
91-
#if CFG_TUD_MEM_DCACHE_ENABLE && CFG_TUD_DWC2_DMA_ENABLE
91+
#if CFG_TUD_MEM_DCACHE_ENABLE
9292
bool dcd_dcache_clean(const void* addr, uint32_t data_size) {
9393
TU_VERIFY(addr && data_size);
9494
return dwc2_dcache_clean(addr, data_size);

‎src/portable/synopsys/dwc2/dwc2_stm32.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -280,7 +280,7 @@ static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
280280
}
281281

282282
//------------- DCache -------------//
283-
#if (CFG_TUD_MEM_DCACHE_ENABLE && CFG_TUD_DWC2_DMA_ENABLE) || (CFG_TUH_MEM_DCACHE_ENABLE && CFG_TUH_DWC2_DMA_ENABLE)
283+
#if CFG_TUD_MEM_DCACHE_ENABLE || CFG_TUH_MEM_DCACHE_ENABLE
284284

285285
typedef struct
286286
{

‎src/portable/synopsys/dwc2/hcd_dwc2.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -141,7 +141,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool dma_host_enabled(const dwc2_regs_t* dwc
141141
return CFG_TUH_DWC2_DMA_ENABLE && ghwcfg2.arch == GHWCFG2_ARCH_INTERNAL_DMA;
142142
}
143143

144-
#if CFG_TUH_MEM_DCACHE_ENABLE && CFG_TUH_DWC2_DMA_ENABLE
144+
#if CFG_TUH_MEM_DCACHE_ENABLE
145145
bool hcd_dcache_clean(const void* addr, uint32_t data_size) {
146146
TU_VERIFY(addr && data_size);
147147
return dwc2_dcache_clean(addr, data_size);

‎src/tusb_option.h

Lines changed: 0 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -465,13 +465,6 @@
465465
#define CFG_TUD_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE
466466
#endif
467467

468-
#if CFG_TUD_MEM_DCACHE_ENABLE && \
469-
(CFG_TUD_DWC2_DMA_ENABLE || defined(TUP_USBIP_CHIPIDEA_HS))
470-
#define TUD_EPBUF_DCACHE_ALIGNED 1
471-
#else
472-
#define TUD_EPBUF_DCACHE_ALIGNED 0
473-
#endif
474-
475468
#ifndef CFG_TUD_ENDPOINT0_SIZE
476469
#define CFG_TUD_ENDPOINT0_SIZE 64
477470
#endif
@@ -591,13 +584,6 @@
591584
#define CFG_TUH_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE
592585
#endif
593586

594-
#if CFG_TUH_MEM_DCACHE_ENABLE && \
595-
(CFG_TUH_DWC2_DMA_ENABLE || defined(TUP_USBIP_CHIPIDEA_HS))
596-
#define TUH_EPBUF_DCACHE_ALIGNED 1
597-
#else
598-
#define TUH_EPBUF_DCACHE_ALIGNED 0
599-
#endif
600-
601587
//------------- CLASS -------------//
602588

603589
#ifndef CFG_TUH_HUB

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