@@ -44,7 +44,7 @@ export UTILS_DIR = ./util
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export TEST_DIR = ./test
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export SIM_DIR = $(PWD ) /../simulation
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- # export MACRO_PLACEMENT = $(RESULTS_DIR)/six_stage.macro_placment.cfg
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+ export MACRO_PLACEMENT = $(RESULTS_DIR ) /six_stage.macro_placment.cfg
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# export BASE = /shared/OpenFASOC/generators/temp-sense-gen/flow
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# export LOG_DIR = $(BASE)/logs/$(PLATFORM)/$(DESIGN_NICKNAME)
@@ -195,8 +195,8 @@ $(RESULTS_DIR)/2_1_floorplan.def: $(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synt
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# STEP 1.1: DEF manipulation
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# -------------------------------------------------------------------------------
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- # $(RESULTS_DIR)/six_stage.macro_placment.cfg: $(RESULTS_DIR)/2_1_floorplan.def
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- # python3 $(UTILS_DIR)/place_six_stage.py
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+ $(RESULTS_DIR ) /six_stage.macro_placment.cfg :
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+ python3 $(UTILS_DIR ) /place_six_stage.py
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# STEP 2: IO Placement
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# -------------------------------------------------------------------------------
@@ -210,7 +210,7 @@ $(RESULTS_DIR)/2_3_floorplan_tdms.def: $(RESULTS_DIR)/2_2_floorplan_io.def $(RES
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# STEP 4: Macro Placement
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# -------------------------------------------------------------------------------
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- $(RESULTS_DIR ) /2_4_floorplan_macro.def : $(RESULTS_DIR ) /2_3_floorplan_tdms.def $(RESULTS_DIR ) /1_synth.v $(RESULTS_DIR ) /1_synth.sdc $(IP_GLOBAL_CFG )
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+ $(RESULTS_DIR ) /2_4_floorplan_macro.def : $(RESULTS_DIR ) /2_3_floorplan_tdms.def $(RESULTS_DIR ) /1_synth.v $(RESULTS_DIR ) /1_synth.sdc $(IP_GLOBAL_CFG ) $( RESULTS_DIR ) /six_stage.macro_placment.cfg
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($( TIME_CMD) $( OPENROAD_CMD) $( SCRIPTS_DIR) /macro_place.tcl -metrics $( LOG_DIR) /2_4_mplace.json) 2>&1 | tee $(LOG_DIR ) /2_4_mplace.log
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# STEP 5: Tapcell and Welltie insertion
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