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bijudas
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clk: renesas: rzv2h: Add MSTOP support
Add MSTOP support to control buses for the individual units on RZ/V2H. Signed-off-by: Biju Das <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
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3 files changed

+214
-61
lines changed

‎drivers/clk/renesas/r9a09g057-cpg.c

Lines changed: 102 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -115,57 +115,108 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
115115
};
116116

117117
static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
118-
DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5),
119-
DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3),
120-
DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4),
121-
DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5),
122-
DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6),
123-
DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7),
124-
DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8),
125-
DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9),
126-
DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10),
127-
DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11),
128-
DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12),
129-
DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13),
130-
DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14),
131-
DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15),
132-
DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16),
133-
DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17),
134-
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18),
135-
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15),
136-
DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19),
137-
DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20),
138-
DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21),
139-
DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22),
140-
DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23),
141-
DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24),
142-
DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25),
143-
DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26),
144-
DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27),
145-
DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3),
146-
DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4),
147-
DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5),
148-
DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6),
149-
DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7),
150-
DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8),
151-
DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9),
152-
DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10),
153-
DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11),
154-
DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12),
155-
DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13),
156-
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14),
157-
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18),
158-
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19),
159-
DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20),
160-
DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21),
161-
DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22),
162-
DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23),
163-
DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24),
164-
DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25),
165-
DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26),
166-
DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27),
167-
DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28),
168-
DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29),
118+
DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5,
119+
BUS_MSTOP_NONE),
120+
DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3,
121+
BUS_MSTOP(5, BIT(10))),
122+
DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4,
123+
BUS_MSTOP(5, BIT(11))),
124+
DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5,
125+
BUS_MSTOP(2, BIT(13))),
126+
DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6,
127+
BUS_MSTOP(2, BIT(14))),
128+
DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7,
129+
BUS_MSTOP(11, BIT(13))),
130+
DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8,
131+
BUS_MSTOP(11, BIT(14))),
132+
DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9,
133+
BUS_MSTOP(11, BIT(15))),
134+
DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
135+
BUS_MSTOP(12, BIT(0))),
136+
DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11,
137+
BUS_MSTOP(3, BIT(10))),
138+
DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
139+
BUS_MSTOP(3, BIT(10))),
140+
DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
141+
BUS_MSTOP(1, BIT(0))),
142+
DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
143+
BUS_MSTOP(1, BIT(0))),
144+
DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
145+
BUS_MSTOP(5, BIT(12))),
146+
DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
147+
BUS_MSTOP(5, BIT(12))),
148+
DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
149+
BUS_MSTOP(5, BIT(13))),
150+
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
151+
BUS_MSTOP(5, BIT(13))),
152+
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
153+
BUS_MSTOP(3, BIT(14))),
154+
DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
155+
BUS_MSTOP(3, BIT(13))),
156+
DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
157+
BUS_MSTOP(1, BIT(1))),
158+
DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
159+
BUS_MSTOP(1, BIT(2))),
160+
DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
161+
BUS_MSTOP(1, BIT(3))),
162+
DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
163+
BUS_MSTOP(1, BIT(4))),
164+
DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
165+
BUS_MSTOP(1, BIT(5))),
166+
DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
167+
BUS_MSTOP(1, BIT(6))),
168+
DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
169+
BUS_MSTOP(1, BIT(7))),
170+
DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
171+
BUS_MSTOP(1, BIT(8))),
172+
DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
173+
BUS_MSTOP(8, BIT(2))),
174+
DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
175+
BUS_MSTOP(8, BIT(2))),
176+
DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
177+
BUS_MSTOP(8, BIT(2))),
178+
DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
179+
BUS_MSTOP(8, BIT(2))),
180+
DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
181+
BUS_MSTOP(8, BIT(3))),
182+
DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
183+
BUS_MSTOP(8, BIT(3))),
184+
DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
185+
BUS_MSTOP(8, BIT(3))),
186+
DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
187+
BUS_MSTOP(8, BIT(3))),
188+
DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
189+
BUS_MSTOP(8, BIT(4))),
190+
DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
191+
BUS_MSTOP(8, BIT(4))),
192+
DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
193+
BUS_MSTOP(8, BIT(4))),
194+
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
195+
BUS_MSTOP(8, BIT(4))),
196+
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
197+
BUS_MSTOP(9, BIT(4))),
198+
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
199+
BUS_MSTOP(9, BIT(4))),
200+
DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
201+
BUS_MSTOP(9, BIT(4))),
202+
DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21,
203+
BUS_MSTOP(9, BIT(5))),
204+
DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22,
205+
BUS_MSTOP(9, BIT(5))),
206+
DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23,
207+
BUS_MSTOP(9, BIT(5))),
208+
DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24,
209+
BUS_MSTOP(9, BIT(6))),
210+
DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25,
211+
BUS_MSTOP(9, BIT(6))),
212+
DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26,
213+
BUS_MSTOP(9, BIT(6))),
214+
DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27,
215+
BUS_MSTOP(9, BIT(7))),
216+
DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28,
217+
BUS_MSTOP(9, BIT(7))),
218+
DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29,
219+
BUS_MSTOP(9, BIT(7))),
169220
};
170221

171222
static const struct rzv2h_reset r9a09g057_resets[] __initconst = {

‎drivers/clk/renesas/rzv2h-cpg.c

Lines changed: 96 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@
2323
#include <linux/platform_device.h>
2424
#include <linux/pm_clock.h>
2525
#include <linux/pm_domain.h>
26+
#include <linux/refcount.h>
2627
#include <linux/reset-controller.h>
2728

2829
#include <dt-bindings/clock/renesas-cpg-mssr.h>
@@ -83,6 +84,12 @@ struct rzv2h_cpg_priv {
8384

8485
#define rcdev_to_priv(x) container_of(x, struct rzv2h_cpg_priv, rcdev)
8586

87+
struct rzv2h_mstop {
88+
u16 idx;
89+
u16 mask;
90+
refcount_t ref_cnt;
91+
};
92+
8693
struct pll_clk {
8794
struct rzv2h_cpg_priv *priv;
8895
void __iomem *base;
@@ -97,6 +104,7 @@ struct pll_clk {
97104
* struct mod_clock - Module clock
98105
*
99106
* @priv: CPG private data
107+
* @mstop: handle to cpg bus mstop data
100108
* @hw: handle between common and hardware-specific interfaces
101109
* @no_pm: flag to indicate PM is not supported
102110
* @on_index: register offset
@@ -106,6 +114,7 @@ struct pll_clk {
106114
*/
107115
struct mod_clock {
108116
struct rzv2h_cpg_priv *priv;
117+
struct rzv2h_mstop *mstop;
109118
struct clk_hw hw;
110119
bool no_pm;
111120
u8 on_index;
@@ -433,6 +442,37 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core,
433442
core->name, PTR_ERR(clk));
434443
}
435444

445+
static void rzv2h_mod_clock_mstop_enable(struct rzv2h_cpg_priv *priv,
446+
struct mod_clock *clock)
447+
{
448+
unsigned long flags;
449+
u32 val;
450+
451+
spin_lock_irqsave(&priv->rmw_lock, flags);
452+
if (!refcount_read(&clock->mstop->ref_cnt)) {
453+
val = clock->mstop->mask << 16;
454+
writel(val, priv->base + CPG_BUS_MSTOP(clock->mstop->idx));
455+
refcount_set(&clock->mstop->ref_cnt, 1);
456+
} else {
457+
refcount_inc(&clock->mstop->ref_cnt);
458+
}
459+
spin_unlock_irqrestore(&priv->rmw_lock, flags);
460+
}
461+
462+
static void rzv2h_mod_clock_mstop_disable(struct rzv2h_cpg_priv *priv,
463+
struct mod_clock *clock)
464+
{
465+
unsigned long flags;
466+
u32 val;
467+
468+
spin_lock_irqsave(&priv->rmw_lock, flags);
469+
if (refcount_dec_and_test(&clock->mstop->ref_cnt)) {
470+
val = clock->mstop->mask << 16 | clock->mstop->mask;
471+
writel(val, priv->base + CPG_BUS_MSTOP(clock->mstop->idx));
472+
}
473+
spin_unlock_irqrestore(&priv->rmw_lock, flags);
474+
}
475+
436476
static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable)
437477
{
438478
struct mod_clock *clock = to_mod_clock(hw);
@@ -447,10 +487,16 @@ static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable)
447487
enable ? "ON" : "OFF");
448488

449489
value = bitmask << 16;
450-
if (enable)
490+
if (enable) {
451491
value |= bitmask;
452-
453-
writel(value, priv->base + reg);
492+
writel(value, priv->base + reg);
493+
if (clock->mstop)
494+
rzv2h_mod_clock_mstop_enable(priv, clock);
495+
} else {
496+
if (clock->mstop)
497+
rzv2h_mod_clock_mstop_disable(priv, clock);
498+
writel(value, priv->base + reg);
499+
}
454500

455501
if (!enable || clock->mon_index < 0)
456502
return 0;
@@ -500,6 +546,45 @@ static const struct clk_ops rzv2h_mod_clock_ops = {
500546
.is_enabled = rzv2h_mod_clock_is_enabled,
501547
};
502548

549+
static struct rzv2h_mstop
550+
*rzv2h_cpg_get_mstop(struct rzv2h_cpg_priv *priv, struct mod_clock *clock, u32 mstop_data)
551+
{
552+
struct rzv2h_mstop *mstop;
553+
unsigned int i;
554+
555+
for (i = 0; i < priv->num_mod_clks; i++) {
556+
struct mod_clock *clk;
557+
struct clk_hw *hw;
558+
559+
if (priv->clks[priv->num_core_clks + i] == ERR_PTR(-ENOENT))
560+
continue;
561+
562+
hw = __clk_get_hw(priv->clks[priv->num_core_clks + i]);
563+
clk = to_mod_clock(hw);
564+
if (!clk->mstop)
565+
continue;
566+
567+
if (BUS_MSTOP(clk->mstop->idx, clk->mstop->mask) == mstop_data) {
568+
if (rzv2h_mod_clock_is_enabled(&clock->hw))
569+
refcount_inc(&clk->mstop->ref_cnt);
570+
return clk->mstop;
571+
}
572+
}
573+
574+
mstop = devm_kzalloc(priv->dev, sizeof(*mstop), GFP_KERNEL);
575+
if (!mstop)
576+
return NULL;
577+
578+
mstop->idx = (mstop_data >> 16) & 0xffff;
579+
mstop->mask = mstop_data & 0xffff;
580+
if (rzv2h_mod_clock_is_enabled(&clock->hw))
581+
refcount_set(&mstop->ref_cnt, 1);
582+
else
583+
refcount_set(&mstop->ref_cnt, 0);
584+
585+
return mstop;
586+
}
587+
503588
static void __init
504589
rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
505590
struct rzv2h_cpg_priv *priv)
@@ -555,6 +640,14 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
555640

556641
priv->clks[id] = clock->hw.clk;
557642

643+
if (mod->mstop_data != BUS_MSTOP_NONE) {
644+
clock->mstop = rzv2h_cpg_get_mstop(priv, clock, mod->mstop_data);
645+
if (!clock->mstop) {
646+
clk = ERR_PTR(-ENOMEM);
647+
goto fail;
648+
}
649+
}
650+
558651
return;
559652

560653
fail:

‎drivers/clk/renesas/rzv2h-cpg.h

Lines changed: 16 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,7 @@ struct ddiv {
3535
#define CPG_CDDIV1 (0x404)
3636
#define CPG_CDDIV3 (0x40C)
3737
#define CPG_CDDIV4 (0x410)
38+
#define CPG_BUS_1_MSTOP (0xd00)
3839

3940
#define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2)
4041
#define CDDIV1_DIVCTL0 DDIV_PACK(CPG_CDDIV1, 0, 2, 4)
@@ -46,6 +47,11 @@ struct ddiv {
4647
#define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17)
4748
#define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18)
4849

50+
#define CPG_BUS_MSTOP(m) (CPG_BUS_1_MSTOP + ((m) - 1) * 4)
51+
52+
#define BUS_MSTOP(idx, mask) (((idx) & 0xffff) << 16 | (mask))
53+
#define BUS_MSTOP_NONE GENMASK(31, 0)
54+
4955
/**
5056
* Definitions of CPG Core Clocks
5157
*
@@ -104,6 +110,7 @@ enum clk_types {
104110
* struct rzv2h_mod_clk - Module Clocks definitions
105111
*
106112
* @name: handle between common and hardware-specific interfaces
113+
* @mstop_data: packed data mstop register offset and mask
107114
* @parent: id of parent clock
108115
* @critical: flag to indicate the clock is critical
109116
* @no_pm: flag to indicate PM is not supported
@@ -114,6 +121,7 @@ enum clk_types {
114121
*/
115122
struct rzv2h_mod_clk {
116123
const char *name;
124+
u32 mstop_data;
117125
u16 parent;
118126
bool critical;
119127
bool no_pm;
@@ -123,9 +131,10 @@ struct rzv2h_mod_clk {
123131
u8 mon_bit;
124132
};
125133

126-
#define DEF_MOD_BASE(_name, _parent, _critical, _no_pm, _onindex, _onbit, _monindex, _monbit) \
134+
#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, _onbit, _monindex, _monbit) \
127135
{ \
128136
.name = (_name), \
137+
.mstop_data = (_mstop), \
129138
.parent = (_parent), \
130139
.critical = (_critical), \
131140
.no_pm = (_no_pm), \
@@ -135,14 +144,14 @@ struct rzv2h_mod_clk {
135144
.mon_bit = (_monbit), \
136145
}
137146

138-
#define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit) \
139-
DEF_MOD_BASE(_name, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
147+
#define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
148+
DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
140149

141-
#define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit) \
142-
DEF_MOD_BASE(_name, _parent, true, false, _onindex, _onbit, _monindex, _monbit)
150+
#define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
151+
DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit)
143152

144-
#define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit) \
145-
DEF_MOD_BASE(_name, _parent, false, true, _onindex, _onbit, _monindex, _monbit)
153+
#define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
154+
DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit)
146155

147156
/**
148157
* struct rzv2h_reset - Reset definitions

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