13
13
#include <linux/of_gpio.h>
14
14
#include <linux/of_device.h>
15
15
#include <linux/clk.h>
16
+ #include <linux/pinctrl/consumer.h>
16
17
#include <linux/pm_runtime.h>
17
18
#include <linux/regmap.h>
18
19
#include <linux/spinlock.h>
@@ -54,8 +55,40 @@ struct rk_i2s_dev {
54
55
const struct rk_i2s_pins * pins ;
55
56
unsigned int bclk_ratio ;
56
57
spinlock_t lock ; /* tx/rx lock */
58
+ struct pinctrl * pinctrl ;
59
+ struct pinctrl_state * bclk_on ;
60
+ struct pinctrl_state * bclk_off ;
57
61
};
58
62
63
+ static int i2s_pinctrl_select_bclk_on (struct rk_i2s_dev * i2s )
64
+ {
65
+ int ret = 0 ;
66
+
67
+ if (!IS_ERR (i2s -> pinctrl ) && !IS_ERR_OR_NULL (i2s -> bclk_on ))
68
+ ret = pinctrl_select_state (i2s -> pinctrl ,
69
+ i2s -> bclk_on );
70
+
71
+ if (ret )
72
+ dev_err (i2s -> dev , "bclk enable failed %d\n" , ret );
73
+
74
+ return ret ;
75
+ }
76
+
77
+ static int i2s_pinctrl_select_bclk_off (struct rk_i2s_dev * i2s )
78
+ {
79
+
80
+ int ret = 0 ;
81
+
82
+ if (!IS_ERR (i2s -> pinctrl ) && !IS_ERR_OR_NULL (i2s -> bclk_off ))
83
+ ret = pinctrl_select_state (i2s -> pinctrl ,
84
+ i2s -> bclk_off );
85
+
86
+ if (ret )
87
+ dev_err (i2s -> dev , "bclk disable failed %d\n" , ret );
88
+
89
+ return ret ;
90
+ }
91
+
59
92
static int i2s_runtime_suspend (struct device * dev )
60
93
{
61
94
struct rk_i2s_dev * i2s = dev_get_drvdata (dev );
@@ -92,38 +125,49 @@ static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
92
125
return snd_soc_dai_get_drvdata (dai );
93
126
}
94
127
95
- static void rockchip_snd_txctrl (struct rk_i2s_dev * i2s , int on )
128
+ static int rockchip_snd_txctrl (struct rk_i2s_dev * i2s , int on )
96
129
{
97
130
unsigned int val = 0 ;
98
131
int retry = 10 ;
132
+ int ret = 0 ;
99
133
100
134
spin_lock (& i2s -> lock );
101
135
if (on ) {
102
- regmap_update_bits (i2s -> regmap , I2S_DMACR ,
103
- I2S_DMACR_TDE_ENABLE , I2S_DMACR_TDE_ENABLE );
136
+ ret = regmap_update_bits (i2s -> regmap , I2S_DMACR ,
137
+ I2S_DMACR_TDE_ENABLE , I2S_DMACR_TDE_ENABLE );
138
+ if (ret < 0 )
139
+ goto end ;
104
140
105
- regmap_update_bits (i2s -> regmap , I2S_XFER ,
106
- I2S_XFER_TXS_START | I2S_XFER_RXS_START ,
107
- I2S_XFER_TXS_START | I2S_XFER_RXS_START );
141
+ ret = regmap_update_bits (i2s -> regmap , I2S_XFER ,
142
+ I2S_XFER_TXS_START | I2S_XFER_RXS_START ,
143
+ I2S_XFER_TXS_START | I2S_XFER_RXS_START );
144
+ if (ret < 0 )
145
+ goto end ;
108
146
109
147
i2s -> tx_start = true;
110
148
} else {
111
149
i2s -> tx_start = false;
112
150
113
- regmap_update_bits (i2s -> regmap , I2S_DMACR ,
114
- I2S_DMACR_TDE_ENABLE , I2S_DMACR_TDE_DISABLE );
151
+ ret = regmap_update_bits (i2s -> regmap , I2S_DMACR ,
152
+ I2S_DMACR_TDE_ENABLE , I2S_DMACR_TDE_DISABLE );
153
+ if (ret < 0 )
154
+ goto end ;
115
155
116
156
if (!i2s -> rx_start ) {
117
- regmap_update_bits (i2s -> regmap , I2S_XFER ,
118
- I2S_XFER_TXS_START |
119
- I2S_XFER_RXS_START ,
120
- I2S_XFER_TXS_STOP |
121
- I2S_XFER_RXS_STOP );
157
+ ret = regmap_update_bits (i2s -> regmap , I2S_XFER ,
158
+ I2S_XFER_TXS_START |
159
+ I2S_XFER_RXS_START ,
160
+ I2S_XFER_TXS_STOP |
161
+ I2S_XFER_RXS_STOP );
162
+ if (ret < 0 )
163
+ goto end ;
122
164
123
165
udelay (150 );
124
- regmap_update_bits (i2s -> regmap , I2S_CLR ,
125
- I2S_CLR_TXC | I2S_CLR_RXC ,
126
- I2S_CLR_TXC | I2S_CLR_RXC );
166
+ ret = regmap_update_bits (i2s -> regmap , I2S_CLR ,
167
+ I2S_CLR_TXC | I2S_CLR_RXC ,
168
+ I2S_CLR_TXC | I2S_CLR_RXC );
169
+ if (ret < 0 )
170
+ goto end ;
127
171
128
172
regmap_read (i2s -> regmap , I2S_CLR , & val );
129
173
@@ -138,44 +182,57 @@ static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
138
182
}
139
183
}
140
184
}
185
+ end :
141
186
spin_unlock (& i2s -> lock );
187
+ if (ret < 0 )
188
+ dev_err (i2s -> dev , "lrclk update failed\n" );
189
+
190
+ return ret ;
142
191
}
143
192
144
- static void rockchip_snd_rxctrl (struct rk_i2s_dev * i2s , int on )
193
+ static int rockchip_snd_rxctrl (struct rk_i2s_dev * i2s , int on )
145
194
{
146
195
unsigned int val = 0 ;
147
196
int retry = 10 ;
197
+ int ret = 0 ;
148
198
149
199
spin_lock (& i2s -> lock );
150
200
if (on ) {
151
- regmap_update_bits (i2s -> regmap , I2S_DMACR ,
201
+ ret = regmap_update_bits (i2s -> regmap , I2S_DMACR ,
152
202
I2S_DMACR_RDE_ENABLE , I2S_DMACR_RDE_ENABLE );
203
+ if (ret < 0 )
204
+ goto end ;
153
205
154
- regmap_update_bits (i2s -> regmap , I2S_XFER ,
206
+ ret = regmap_update_bits (i2s -> regmap , I2S_XFER ,
155
207
I2S_XFER_TXS_START | I2S_XFER_RXS_START ,
156
208
I2S_XFER_TXS_START | I2S_XFER_RXS_START );
209
+ if (ret < 0 )
210
+ goto end ;
157
211
158
212
i2s -> rx_start = true;
159
213
} else {
160
214
i2s -> rx_start = false;
161
215
162
- regmap_update_bits (i2s -> regmap , I2S_DMACR ,
216
+ ret = regmap_update_bits (i2s -> regmap , I2S_DMACR ,
163
217
I2S_DMACR_RDE_ENABLE , I2S_DMACR_RDE_DISABLE );
218
+ if (ret < 0 )
219
+ goto end ;
164
220
165
221
if (!i2s -> tx_start ) {
166
- regmap_update_bits (i2s -> regmap , I2S_XFER ,
222
+ ret = regmap_update_bits (i2s -> regmap , I2S_XFER ,
167
223
I2S_XFER_TXS_START |
168
224
I2S_XFER_RXS_START ,
169
225
I2S_XFER_TXS_STOP |
170
226
I2S_XFER_RXS_STOP );
171
-
227
+ if (ret < 0 )
228
+ goto end ;
172
229
udelay (150 );
173
- regmap_update_bits (i2s -> regmap , I2S_CLR ,
230
+ ret = regmap_update_bits (i2s -> regmap , I2S_CLR ,
174
231
I2S_CLR_TXC | I2S_CLR_RXC ,
175
232
I2S_CLR_TXC | I2S_CLR_RXC );
176
-
233
+ if (ret < 0 )
234
+ goto end ;
177
235
regmap_read (i2s -> regmap , I2S_CLR , & val );
178
-
179
236
/* Should wait for clear operation to finish */
180
237
while (val ) {
181
238
regmap_read (i2s -> regmap , I2S_CLR , & val );
@@ -187,7 +244,12 @@ static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
187
244
}
188
245
}
189
246
}
247
+ end :
190
248
spin_unlock (& i2s -> lock );
249
+ if (ret < 0 )
250
+ dev_err (i2s -> dev , "lrclk update failed\n" );
251
+
252
+ return ret ;
191
253
}
192
254
193
255
static int rockchip_i2s_set_fmt (struct snd_soc_dai * cpu_dai ,
@@ -425,17 +487,26 @@ static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
425
487
case SNDRV_PCM_TRIGGER_RESUME :
426
488
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE :
427
489
if (substream -> stream == SNDRV_PCM_STREAM_CAPTURE )
428
- rockchip_snd_rxctrl (i2s , 1 );
490
+ ret = rockchip_snd_rxctrl (i2s , 1 );
429
491
else
430
- rockchip_snd_txctrl (i2s , 1 );
492
+ ret = rockchip_snd_txctrl (i2s , 1 );
493
+ /* Do not turn on bclk if lrclk open fails. */
494
+ if (ret < 0 )
495
+ return ret ;
496
+ i2s_pinctrl_select_bclk_on (i2s );
431
497
break ;
432
498
case SNDRV_PCM_TRIGGER_SUSPEND :
433
499
case SNDRV_PCM_TRIGGER_STOP :
434
500
case SNDRV_PCM_TRIGGER_PAUSE_PUSH :
435
- if (substream -> stream == SNDRV_PCM_STREAM_CAPTURE )
436
- rockchip_snd_rxctrl (i2s , 0 );
437
- else
438
- rockchip_snd_txctrl (i2s , 0 );
501
+ if (substream -> stream == SNDRV_PCM_STREAM_CAPTURE ) {
502
+ if (!i2s -> tx_start )
503
+ i2s_pinctrl_select_bclk_off (i2s );
504
+ ret = rockchip_snd_rxctrl (i2s , 0 );
505
+ } else {
506
+ if (!i2s -> rx_start )
507
+ i2s_pinctrl_select_bclk_off (i2s );
508
+ ret = rockchip_snd_txctrl (i2s , 0 );
509
+ }
439
510
break ;
440
511
default :
441
512
ret = - EINVAL ;
@@ -736,6 +807,33 @@ static int rockchip_i2s_probe(struct platform_device *pdev)
736
807
}
737
808
738
809
i2s -> bclk_ratio = 64 ;
810
+ i2s -> pinctrl = devm_pinctrl_get (& pdev -> dev );
811
+ if (IS_ERR (i2s -> pinctrl ))
812
+ dev_err (& pdev -> dev , "failed to find i2s pinctrl\n" );
813
+
814
+ i2s -> bclk_on = pinctrl_lookup_state (i2s -> pinctrl ,
815
+ "bclk_on" );
816
+ if (IS_ERR_OR_NULL (i2s -> bclk_on ))
817
+ dev_err (& pdev -> dev , "failed to find i2s default state\n" );
818
+ else
819
+ dev_dbg (& pdev -> dev , "find i2s bclk state\n" );
820
+
821
+ i2s -> bclk_off = pinctrl_lookup_state (i2s -> pinctrl ,
822
+ "bclk_off" );
823
+ if (IS_ERR_OR_NULL (i2s -> bclk_off ))
824
+ dev_err (& pdev -> dev , "failed to find i2s gpio state\n" );
825
+ else
826
+ dev_dbg (& pdev -> dev , "find i2s bclk_off state\n" );
827
+
828
+ i2s_pinctrl_select_bclk_off (i2s );
829
+
830
+ i2s -> playback_dma_data .addr = res -> start + I2S_TXDR ;
831
+ i2s -> playback_dma_data .addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES ;
832
+ i2s -> playback_dma_data .maxburst = 4 ;
833
+
834
+ i2s -> capture_dma_data .addr = res -> start + I2S_RXDR ;
835
+ i2s -> capture_dma_data .addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES ;
836
+ i2s -> capture_dma_data .maxburst = 4 ;
739
837
740
838
dev_set_drvdata (& pdev -> dev , i2s );
741
839
0 commit comments