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Dimus77igcbot
Dimus77
authored and
igcbot
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Revert of c129ab8 Int64b support refactoring (#9)
1 parent 06d6118 commit 1d6feed

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4 files changed

+23
-34
lines changed

4 files changed

+23
-34
lines changed

‎IGC/Compiler/CISACodeGen/EmitVISAPass.cpp

+21-21
Original file line numberDiff line numberDiff line change
@@ -2647,7 +2647,7 @@ void EmitPass::emitCmpSADs(llvm::GenIntrinsicInst* inst)
26472647
m_encoder->Push();
26482648

26492649
// Collect the MVs
2650-
if (m_currShader->m_Platform->hasNoFullI64Support()) {
2650+
if (m_currShader->m_Platform->hasNoInt64Inst()) {
26512651
CVariable* pMVMinAlias = m_currShader->GetNewAlias(pMVMin, ISA_TYPE_UD, 0, 32);
26522652
CVariable* pMVCurrAlias = m_currShader->GetNewAlias(pMVCurr, ISA_TYPE_UD, 0, 32);
26532653

@@ -5267,7 +5267,7 @@ void EmitPass::emitLegacySimdBlockWrite(llvm::Instruction* inst, llvm::Value* pt
52675267
activelanes, eOffset->GetType(), eOffset->GetAlign(), true, "ScatterOff");
52685268

52695269
CVariable* immVar = m_currShader->ImmToVariable(0x40, ISA_TYPE_UV);
5270-
if (useA64 && m_currShader->m_Platform->hasNoInt64AddInst()) {
5270+
if (useA64 && m_currShader->m_Platform->hasNoInt64Inst()) {
52715271
emitAddPair(ScatterOff, eOffset, immVar);
52725272
}
52735273
else {
@@ -5329,7 +5329,7 @@ void EmitPass::emitLegacySimdBlockWrite(llvm::Instruction* inst, llvm::Value* pt
53295329

53305330
if (bytesRemaining)
53315331
{
5332-
if (m_currShader->m_Platform->hasNoInt64AddInst()) {
5332+
if (m_currShader->m_Platform->hasNoInt64Inst()) {
53335333
CVariable* ImmVar = m_currShader->ImmToVariable(bytesToRead, ISA_TYPE_UD);
53345334
emitAddPair(pTempVar, pTempVar, ImmVar);
53355335
}
@@ -5463,7 +5463,7 @@ void EmitPass::emitLegacySimdBlockRead(llvm::Instruction* inst, llvm::Value* ptr
54635463
activelanes, eOffset->GetType(), eOffset->GetAlign(), true, "GatherOff");
54645464

54655465
CVariable* immVar = m_currShader->ImmToVariable(0x40, ISA_TYPE_UV);
5466-
if (useA64 && m_currShader->m_Platform->hasNoInt64AddInst()) {
5466+
if (useA64 && m_currShader->m_Platform->hasNoInt64Inst()) {
54675467
emitAddPair(gatherOff, eOffset, immVar);
54685468
}
54695469
else {
@@ -5524,7 +5524,7 @@ void EmitPass::emitLegacySimdBlockRead(llvm::Instruction* inst, llvm::Value* ptr
55245524

55255525
if (bytesRemaining)
55265526
{
5527-
if (m_currShader->m_Platform->hasNoInt64AddInst()) {
5527+
if (m_currShader->m_Platform->hasNoInt64Inst()) {
55285528
CVariable* ImmVar = m_currShader->ImmToVariable(bytesToRead, ISA_TYPE_UD);
55295529
emitAddPair(pTempVar, pTempVar, ImmVar);
55305530
}
@@ -8842,7 +8842,7 @@ void EmitPass::emitAddrSpaceCast(llvm::AddrSpaceCastInst* addrSpaceCast)
88428842

88438843
if (sourceAddrSpace == ADDRESS_SPACE_PRIVATE)
88448844
{
8845-
if (m_pCtx->m_hasEmu64BitInsts && m_currShader->m_Platform->hasNoFullI64Support())
8845+
if (m_pCtx->m_hasEmu64BitInsts && m_currShader->m_Platform->hasNoInt64Inst())
88468846
{
88478847
if (m_currShader->GetContext()->getRegisterPointerSizeInBits(sourceAddrSpace) == 32)
88488848
{
@@ -8913,7 +8913,7 @@ void EmitPass::emitAddrSpaceCast(llvm::AddrSpaceCastInst* addrSpaceCast)
89138913
}
89148914
else if (sourceAddrSpace == ADDRESS_SPACE_LOCAL)
89158915
{
8916-
if (m_pCtx->m_hasEmu64BitInsts && m_currShader->m_Platform->hasNoFullI64Support())
8916+
if (m_pCtx->m_hasEmu64BitInsts && m_currShader->m_Platform->hasNoInt64Inst())
89178917
{
89188918
if (m_currShader->GetContext()->getRegisterPointerSizeInBits(sourceAddrSpace) == 32)
89198919
{
@@ -8995,7 +8995,7 @@ void EmitPass::emitAddrSpaceCast(llvm::AddrSpaceCastInst* addrSpaceCast)
89958995
// Address space cast is in the form of generic -> {private, local, global}
89968996
// Tag is removed according to the address space of the destination
89978997

8998-
if (m_pCtx->m_hasEmu64BitInsts && m_currShader->m_Platform->hasNoFullI64Support())
8998+
if (m_pCtx->m_hasEmu64BitInsts && m_currShader->m_Platform->hasNoInt64Inst())
89998999
{
90009000
if (m_currShader->GetContext()->getRegisterPointerSizeInBits(destAddrSpace) == 32)
90019001
{
@@ -9081,7 +9081,7 @@ CVariable* EmitPass::createAddressSpaceTag(CVariable* src, unsigned int addrSpac
90819081
CVariable* taggedSrc = nullptr;
90829082
if (addrSpace == ADDRESS_SPACE_PRIVATE)
90839083
{
9084-
if (m_pCtx->m_hasEmu64BitInsts && m_currShader->m_Platform->hasNoFullI64Support())
9084+
if (m_pCtx->m_hasEmu64BitInsts && m_currShader->m_Platform->hasNoInt64Inst())
90859085
{
90869086
if (m_currShader->GetContext()->getRegisterPointerSizeInBits(addrSpace) == 32)
90879087
{
@@ -9151,7 +9151,7 @@ CVariable* EmitPass::createAddressSpaceTag(CVariable* src, unsigned int addrSpac
91519151
}
91529152
else if (addrSpace == ADDRESS_SPACE_LOCAL)
91539153
{
9154-
if (m_pCtx->m_hasEmu64BitInsts && m_currShader->m_Platform->hasNoFullI64Support())
9154+
if (m_pCtx->m_hasEmu64BitInsts && m_currShader->m_Platform->hasNoInt64Inst())
91559155
{
91569156
if (m_currShader->GetContext()->getRegisterPointerSizeInBits(addrSpace) == 32)
91579157
{
@@ -11031,7 +11031,7 @@ CVariable* EmitPass::BroadcastIfUniform(CVariable* pVar)
1103111031
{
1103211032
IGC_ASSERT_MESSAGE(nullptr != pVar, "pVar is null");
1103311033
VISA_Type VarT = pVar->GetType();
11034-
bool Need64BitEmu = m_currShader->m_Platform->hasNoFullI64Support() &&
11034+
bool Need64BitEmu = m_currShader->m_Platform->hasNoInt64Inst() &&
1103511035
(VarT == ISA_TYPE_Q || VarT == ISA_TYPE_UQ);
1103611036
bool IsImm = pVar->IsImmediate();
1103711037
if (pVar->IsUniform())
@@ -11898,7 +11898,7 @@ void EmitPass::emitReductionClustered(const e_opcode op, const uint64_t identity
1189811898
IGC_ASSERT_MESSAGE(iSTD::BitCount(clusterSize) == 1, "Cluster size must be a power of two.");
1189911899
IGC_ASSERT_MESSAGE(!is64bitType || CEncoder::GetCISADataTypeSize(type) == 8, "Unsupported 64-bit type.");
1190011900

11901-
IGC_ASSERT_MESSAGE(!isInt64Type || !m_currShader->m_Platform->hasNoFullI64Support(), "Int64 emulation is not supported.");
11901+
IGC_ASSERT_MESSAGE(!isInt64Type || !m_currShader->m_Platform->hasNoInt64Inst(), "Int64 emulation is not supported.");
1190211902
IGC_ASSERT_MESSAGE(!isFP64Type || !m_currShader->m_Platform->hasNoFP64Inst(), "FP64 emulation is not supported.");
1190311903
// Src might be uniform, as its value will be broadcasted during src preparation.
1190411904
// Dst uniformness depends on actual support in WIAnalysis, so far implemented for 32-clusters only.
@@ -15224,7 +15224,7 @@ void EmitPass::emitVectorLoad(LoadInst* inst, Value* offset, ConstantInt* immOff
1522415224
// on platform that does not support 64bit integer add.
1522515225
//Note: it doesn't seem to be necessary to check hasNoFP64Inst() here.
1522615226
if (srcUniform && (totalBytes == 4 || totalBytes == 8 || totalBytes == 12 || totalBytes == 16 ||
15227-
(totalBytes == 32 && (useA32 || !m_currShader->m_Platform->hasNoFullI64Support()))))
15227+
(totalBytes == 32 && (useA32 || !m_currShader->m_Platform->hasNoInt64Inst()))))
1522815228
{
1522915229
bool needTemp = !destUniform ||
1523015230
!IsGRFAligned(m_destination, EALIGN_GRF) ||
@@ -15310,7 +15310,7 @@ void EmitPass::emitVectorLoad(LoadInst* inst, Value* offset, ConstantInt* immOff
1531015310
}
1531115311

1531215312
CVariable* immVar = m_currShader->ImmToVariable(incImm, ISA_TYPE_UV);
15313-
if (!useA32 && m_currShader->m_Platform->hasNoInt64AddInst()) {
15313+
if (!useA32 && m_currShader->m_Platform->hasNoInt64Inst()) {
1531415314
emitAddPair(gatherOff, eOffset, immVar);
1531515315
}
1531615316
else {
@@ -15391,7 +15391,7 @@ void EmitPass::emitVectorLoad(LoadInst* inst, Value* offset, ConstantInt* immOff
1539115391
// Calculate the new element offset
1539215392
rawAddrVar = m_currShader->GetNewVariable(eOffset);
1539315393
CVariable* ImmVar = m_currShader->ImmToVariable(eltOffBytes, ISA_TYPE_UD);
15394-
if (!useA32 && m_currShader->m_Platform->hasNoInt64AddInst()) {
15394+
if (!useA32 && m_currShader->m_Platform->hasNoInt64Inst()) {
1539515395
emitAddPair(rawAddrVar, eOffset, ImmVar);
1539615396
}
1539715397
else {
@@ -15464,7 +15464,7 @@ void EmitPass::emitVectorLoad(LoadInst* inst, Value* offset, ConstantInt* immOff
1546415464
// Calculate the new element offset
1546515465
rawAddrVar = m_currShader->GetNewVariable(eOffset);
1546615466
CVariable* ImmVar = m_currShader->ImmToVariable(VecMessInfo.insts[i].startByte, ISA_TYPE_UD);
15467-
if (!useA32 && m_currShader->m_Platform->hasNoInt64AddInst()) {
15467+
if (!useA32 && m_currShader->m_Platform->hasNoInt64Inst()) {
1546815468
emitAddPair(rawAddrVar, eOffset, ImmVar);
1546915469
}
1547015470
else {
@@ -15624,7 +15624,7 @@ void EmitPass::emitVectorStore(StoreInst* inst, Value* offset, ConstantInt* immO
1562415624
// When work-around of A64 SKL Si limitation of SIMD4, we use SIMD8 (nbelts > nbeltsWanted)
1562515625
// in which all upper four channels are zero, meaning eOffset[0], Later, stored value
1562615626
// must use storvedVar[0] for those extra lanes.
15627-
if (!useA32 && m_currShader->m_Platform->hasNoInt64AddInst()) {
15627+
if (!useA32 && m_currShader->m_Platform->hasNoInt64Inst()) {
1562815628
emitAddPair(NewOff, eOffset, immVar);
1562915629
}
1563015630
else {
@@ -15783,7 +15783,7 @@ void EmitPass::emitVectorStore(StoreInst* inst, Value* offset, ConstantInt* immO
1578315783
// Calculate the new element offset
1578415784
rawAddrVar = m_currShader->GetNewVariable(eOffset);
1578515785
CVariable* ImmVar = m_currShader->ImmToVariable(VecMessInfo.insts[i].startByte, ISA_TYPE_UD);
15786-
if (!useA32 && m_currShader->m_Platform->hasNoInt64AddInst()) {
15786+
if (!useA32 && m_currShader->m_Platform->hasNoInt64Inst()) {
1578715787
emitAddPair(rawAddrVar, eOffset, ImmVar);
1578815788
}
1578915789
else {
@@ -15929,7 +15929,7 @@ CVariable* EmitPass::prepareAddressForUniform(
1592915929
CVariable* offHi = m_currShader->GetNewAlias(off, off->GetType(), 0, halfNElts);
1593015930
CVariable* offLo = m_currShader->GetNewAlias(off, off->GetType(), bytes2, halfNElts);
1593115931

15932-
if (isA64 && m_currShader->m_Platform->hasNoInt64AddInst())
15932+
if (isA64 && m_currShader->m_Platform->hasNoInt64Inst())
1593315933
{
1593415934
emitAddPair(newVarHi, AddrVar, offHi);
1593515935
emitAddPair(newVarLo, AddrVar, offLo);
@@ -15952,7 +15952,7 @@ CVariable* EmitPass::prepareAddressForUniform(
1595215952
m_encoder->Push();
1595315953
}
1595415954
}
15955-
else if (isA64 && m_currShader->m_Platform->hasNoInt64AddInst() && pow2NElts > 1)
15955+
else if (isA64 && m_currShader->m_Platform->hasNoInt64Inst() && pow2NElts > 1)
1595615956
{
1595715957
emitAddPair(newVar, AddrVar, off);
1595815958
}
@@ -16213,7 +16213,7 @@ void EmitPass::emitPushFrameToStack(unsigned& pushSize)
1621316213

1621416214
void EmitPass::emitAddPointer(CVariable* Dst, CVariable* Src, CVariable* offset)
1621516215
{
16216-
if (m_currShader->m_Platform->hasNoInt64AddInst() &&
16216+
if (m_currShader->m_Platform->hasNoInt64Inst() &&
1621716217
(Dst->GetType() == ISA_TYPE_Q || Dst->GetType() == ISA_TYPE_UQ) &&
1621816218
(Src->GetType() == ISA_TYPE_Q || Src->GetType() == ISA_TYPE_UQ))
1621916219
{

‎IGC/Compiler/CISACodeGen/LowerGEPForPrivMem.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -257,7 +257,7 @@ static void GetAllocaLiverange(Instruction* I, unsigned int& liverangeStart, uns
257257
bool LowerGEPForPrivMem::IsNativeType(Type* type)
258258
{
259259
if ((type->isDoubleTy() && m_ctx->platform.hasNoFP64Inst()) ||
260-
(type->isIntegerTy(64) && m_ctx->platform.hasNoFullI64Support()))
260+
(type->isIntegerTy(64) && m_ctx->platform.hasNoInt64Inst()))
261261
{
262262
return false;
263263
}

‎IGC/Compiler/CISACodeGen/Platform.hpp

-10
Original file line numberDiff line numberDiff line change
@@ -410,16 +410,6 @@ bool supportsSIMD16TypedRW() const
410410
return false;
411411
}
412412

413-
bool hasNoFullI64Support() const
414-
{
415-
return hasNoInt64Inst();
416-
}
417-
418-
bool hasNoInt64AddInst() const
419-
{
420-
return hasNoFullI64Support();
421-
}
422-
423413
//all the platforms which DONOT support 64 bit int operations
424414
bool hasNoInt64Inst() const {
425415
return m_platformInfo.eProductFamily == IGFX_ICELAKE_LP ||

‎IGC/Compiler/CISACodeGen/ShaderCodeGen.cpp

+1-2
Original file line numberDiff line numberDiff line change
@@ -667,8 +667,7 @@ static void AddLegalizationPasses(CodeGenContext& ctx, IGCPassManager& mpm, PSSi
667667
(ctx.m_DriverInfo.Enable64BitEmu() &&
668668
(IGC_GET_FLAG_VALUE(Enable64BitEmulation) ||
669669
(IGC_GET_FLAG_VALUE(Enable64BitEmulationOnSelectedPlatform) &&
670-
ctx.platform.need64BitEmulation())))
671-
)
670+
ctx.platform.need64BitEmulation()))))
672671
{
673672
mpm.add(new BreakConstantExpr());
674673

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