@@ -504,8 +504,8 @@ int IR_Builder::translateVISAArithmeticDoubleInst(ISA_Opcode opcode, Common_ISA_
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G4_SrcRegRegion regSrcCR0(Mod_src_undef, Direct, phyregpool.getCr0Reg() ,0, 0, getRegionScalar(), Type_UD );
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// r0 = 0.0:df, r1 = 1.0:df
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- G4_Declare *t0 = getImmDcl(dbl_constant_0, 4 );
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- G4_Declare *t1 = getImmDcl(dbl_constant_1, 4 );
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+ G4_Declare *t0 = getImmDcl(dbl_constant_0, element_size );
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+ G4_Declare *t1 = getImmDcl(dbl_constant_1, element_size );
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inst = createPseudoKills({ t6, t7, t8, t9, t10, t11, t12, t13, tmpFlag });
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@@ -1482,9 +1482,9 @@ int IR_Builder::translateVISAArithmeticDoubleSQRTInst(ISA_Opcode opcode, Common_
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G4_Predicate_Control predCtrlValue = PRED_DEFAULT;
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// temp registers
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- G4_Declare *t0 = getImmDcl(createDFImm(0.0), 4 );
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- G4_Declare *t1 = getImmDcl(createDFImm(1.0), 4 );
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- G4_Declare *t2 = getImmDcl(createDFImm(0.5), 4 );
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+ G4_Declare *t0 = getImmDcl(createDFImm(0.0), element_size );
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+ G4_Declare *t1 = getImmDcl(createDFImm(1.0), element_size );
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+ G4_Declare *t2 = getImmDcl(createDFImm(0.5), element_size );
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G4_Declare *t6 = createTempVarWithNoSpill(element_size, Type_DF, reg_align, Any);
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G4_Declare *t7 = createTempVarWithNoSpill(element_size, Type_DF, reg_align, Any);
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G4_Declare *t8 = createTempVarWithNoSpill(element_size, Type_DF, reg_align, Any);
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