@@ -1663,7 +1663,7 @@ MachineInstr *Z80InstrInfo::optimizeLoadInstr(MachineInstr &MI,
1663
1663
Register &FoldAsLoadDefReg,
1664
1664
MachineInstr *&DefMI) const {
1665
1665
// Check whether we can move DefMI here.
1666
- DefMI = MRI->getVRegDef (FoldAsLoadDefReg);
1666
+ DefMI = MRI->getUniqueVRegDef (FoldAsLoadDefReg);
1667
1667
bool SawStore = false ;
1668
1668
if (!DefMI || !DefMI->isSafeToMove (nullptr , SawStore))
1669
1669
return nullptr ;
@@ -1734,18 +1734,29 @@ MachineInstr *Z80InstrInfo::foldMemoryOperandImpl(
1734
1734
1735
1735
unsigned Opc;
1736
1736
unsigned OpSize = 1 ;
1737
- switch (MI.getOpcode ()) {
1738
- case Z80::BIT8bg: Opc = IsOff ? Z80::BIT8bo : Z80::BIT8bp; break ;
1739
- case Z80::ADD8ar: Opc = IsOff ? Z80::ADD8ao : Z80::ADD8ap; break ;
1740
- case Z80::ADC8ar: Opc = IsOff ? Z80::ADC8ao : Z80::ADC8ap; break ;
1741
- case Z80::SUB8ar: Opc = IsOff ? Z80::SUB8ao : Z80::SUB8ap; break ;
1742
- case Z80::SBC8ar: Opc = IsOff ? Z80::SBC8ao : Z80::SBC8ap; break ;
1743
- case Z80::AND8ar: Opc = IsOff ? Z80::AND8ao : Z80::AND8ap; break ;
1744
- case Z80::XOR8ar: Opc = IsOff ? Z80::XOR8ao : Z80::XOR8ap; break ;
1745
- case Z80:: OR8ar: Opc = IsOff ? Z80:: OR8ao : Z80:: OR8ap; break ;
1746
- case Z80::TST8ar: Opc = IsOff ? Z80::TST8ao : Z80::TST8ap; break ;
1747
- case TargetOpcode::COPY: Opc = IsOff ? Z80::LD8ro : Z80::LD8rp; break ;
1737
+ switch (OpNum) {
1748
1738
default : return nullptr ;
1739
+ case 0 :
1740
+ switch (MI.getOpcode ()) {
1741
+ default : return nullptr ;
1742
+ case TargetOpcode:: COPY: Opc = IsOff ? Z80:: LD8or : Z80:: LD8pr; break ;
1743
+ }
1744
+ break ;
1745
+ case 1 :
1746
+ switch (MI.getOpcode ()) {
1747
+ default : return nullptr ;
1748
+ case Z80::BIT8bg: Opc = IsOff ? Z80::BIT8bo : Z80::BIT8bp; break ;
1749
+ case Z80::ADD8ar: Opc = IsOff ? Z80::ADD8ao : Z80::ADD8ap; break ;
1750
+ case Z80::ADC8ar: Opc = IsOff ? Z80::ADC8ao : Z80::ADC8ap; break ;
1751
+ case Z80::SUB8ar: Opc = IsOff ? Z80::SUB8ao : Z80::SUB8ap; break ;
1752
+ case Z80::SBC8ar: Opc = IsOff ? Z80::SBC8ao : Z80::SBC8ap; break ;
1753
+ case Z80::AND8ar: Opc = IsOff ? Z80::AND8ao : Z80::AND8ap; break ;
1754
+ case Z80::XOR8ar: Opc = IsOff ? Z80::XOR8ao : Z80::XOR8ap; break ;
1755
+ case Z80:: OR8ar: Opc = IsOff ? Z80:: OR8ao : Z80:: OR8ap; break ;
1756
+ case Z80::TST8ar: Opc = IsOff ? Z80::TST8ao : Z80::TST8ap; break ;
1757
+ case TargetOpcode:: COPY: Opc = IsOff ? Z80:: LD8ro : Z80:: LD8rp; break ;
1758
+ }
1759
+ break ;
1749
1760
}
1750
1761
1751
1762
if (Size && Size < OpSize)
0 commit comments