Skip to content

Commit d2b6560

Browse files
jyknightjyknight
committed
LLVM: Remove support for 3DNow! intrinsics.
This set of instructions was only supported by AMD chips starting in the K6-2 (introduced 1998), and before the "Bulldozer" family (2011). They were never much used, as they were effectively superseded by the more-widely-implemented SSE (first implemented on the AMD side in Athlon XP in 2001). This is being done as a predecessor towards general removal of MMX register usage. Since there is almost no usage of the 3DNow! intrinsics, and no modern hardware even implements them, simple removal seems like the best option. Works towards issue llvm#41665.
1 parent 28be235 commit d2b6560

17 files changed

+70
-1800
lines changed

‎llvm/docs/ReleaseNotes.rst

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -196,6 +196,9 @@ Changes to the X86 Backend
196196
- Removed knl/knm specific ISA intrinsics: AVX512PF, AVX512ER, PREFETCHWT1,
197197
while assembly encoding/decoding supports are kept.
198198

199+
- Removed ``3DNow!``-specific ISA intrinsics and codegen support. The ``3dnow`` and ``3dnowa`` target features are no longer supported. The intrinsics ``llvm.x86.3dnow.*``, ``llvm.x86.3dnowa.*``, and ``llvm.x86.mmx.femms`` have been removed. Assembly encoding/decoding for the corresponding instructions remains supported.
200+
201+
199202
Changes to the OCaml bindings
200203
-----------------------------
201204

‎llvm/include/llvm/IR/IntrinsicsX86.td

Lines changed: 0 additions & 80 deletions
Original file line numberDiff line numberDiff line change
@@ -129,83 +129,6 @@ let TargetPrefix = "x86" in {
129129
Intrinsic<[], [llvm_ptr_ty], []>;
130130
}
131131

132-
//===----------------------------------------------------------------------===//
133-
// 3DNow!
134-
135-
let TargetPrefix = "x86" in {
136-
def int_x86_3dnow_pavgusb :
137-
DefaultAttrsIntrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
138-
[IntrNoMem]>;
139-
def int_x86_3dnow_pf2id :
140-
DefaultAttrsIntrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
141-
def int_x86_3dnow_pfacc :
142-
DefaultAttrsIntrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
143-
[IntrNoMem]>;
144-
def int_x86_3dnow_pfadd :
145-
DefaultAttrsIntrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
146-
[IntrNoMem]>;
147-
def int_x86_3dnow_pfcmpeq :
148-
DefaultAttrsIntrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
149-
[IntrNoMem]>;
150-
def int_x86_3dnow_pfcmpge :
151-
DefaultAttrsIntrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
152-
[IntrNoMem]>;
153-
def int_x86_3dnow_pfcmpgt :
154-
DefaultAttrsIntrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
155-
[IntrNoMem]>;
156-
def int_x86_3dnow_pfmax :
157-
DefaultAttrsIntrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
158-
[IntrNoMem]>;
159-
def int_x86_3dnow_pfmin :
160-
DefaultAttrsIntrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
161-
[IntrNoMem]>;
162-
def int_x86_3dnow_pfmul :
163-
DefaultAttrsIntrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
164-
[IntrNoMem]>;
165-
def int_x86_3dnow_pfrcp :
166-
DefaultAttrsIntrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
167-
def int_x86_3dnow_pfrcpit1 :
168-
DefaultAttrsIntrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
169-
[IntrNoMem]>;
170-
def int_x86_3dnow_pfrcpit2 :
171-
DefaultAttrsIntrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
172-
[IntrNoMem]>;
173-
def int_x86_3dnow_pfrsqrt :
174-
DefaultAttrsIntrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
175-
def int_x86_3dnow_pfrsqit1 :
176-
DefaultAttrsIntrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
177-
[IntrNoMem]>;
178-
def int_x86_3dnow_pfsub :
179-
DefaultAttrsIntrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
180-
[IntrNoMem]>;
181-
def int_x86_3dnow_pfsubr :
182-
DefaultAttrsIntrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
183-
[IntrNoMem]>;
184-
def int_x86_3dnow_pi2fd :
185-
DefaultAttrsIntrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
186-
def int_x86_3dnow_pmulhrw :
187-
DefaultAttrsIntrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
188-
[IntrNoMem]>;
189-
}
190-
191-
//===----------------------------------------------------------------------===//
192-
// 3DNow! extensions
193-
194-
let TargetPrefix = "x86" in {
195-
def int_x86_3dnowa_pf2iw :
196-
DefaultAttrsIntrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
197-
def int_x86_3dnowa_pfnacc :
198-
DefaultAttrsIntrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
199-
[IntrNoMem]>;
200-
def int_x86_3dnowa_pfpnacc :
201-
DefaultAttrsIntrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
202-
[IntrNoMem]>;
203-
def int_x86_3dnowa_pi2fw :
204-
DefaultAttrsIntrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
205-
def int_x86_3dnowa_pswapd :
206-
DefaultAttrsIntrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
207-
}
208-
209132
//===----------------------------------------------------------------------===//
210133
// SSE1
211134

@@ -2332,9 +2255,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
23322255
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
23332256
def int_x86_mmx_emms : ClangBuiltin<"__builtin_ia32_emms">,
23342257
Intrinsic<[], [], []>;
2335-
// 3DNow! extension
2336-
def int_x86_mmx_femms :
2337-
Intrinsic<[], [], []>;
23382258
}
23392259

23402260
// Integer arithmetic ops.

‎llvm/lib/Target/X86/X86.td

Lines changed: 10 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -86,14 +86,8 @@ def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
8686
// The MMX subtarget feature is separate from the rest of the SSE features
8787
// because it's important (for odd compatibility reasons) to be able to
8888
// turn it off explicitly while allowing SSE+ to be on.
89-
def FeatureMMX : SubtargetFeature<"mmx","X863DNowLevel", "MMX",
89+
def FeatureMMX : SubtargetFeature<"mmx","HasMMX", "true",
9090
"Enable MMX instructions">;
91-
def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
92-
"Enable 3DNow! instructions",
93-
[FeatureMMX]>;
94-
def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
95-
"Enable 3DNow! Athlon instructions",
96-
[Feature3DNow]>;
9791
// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
9892
// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
9993
// without disabling 64-bit mode. Nothing should imply this feature bit. It
@@ -1332,7 +1326,6 @@ def ProcessorFeatures {
13321326
list<SubtargetFeature> BarcelonaFeatures = [FeatureX87,
13331327
FeatureCX8,
13341328
FeatureSSE4A,
1335-
Feature3DNowA,
13361329
FeatureFXSR,
13371330
FeatureNOPL,
13381331
FeatureCX16,
@@ -1825,32 +1818,32 @@ def : ProcModel<P, SapphireRapidsModel,
18251818

18261819
def : Proc<"k6", [FeatureX87, FeatureCX8, FeatureMMX],
18271820
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1828-
def : Proc<"k6-2", [FeatureX87, FeatureCX8, Feature3DNow],
1821+
def : Proc<"k6-2", [FeatureX87, FeatureCX8],
18291822
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1830-
def : Proc<"k6-3", [FeatureX87, FeatureCX8, Feature3DNow],
1823+
def : Proc<"k6-3", [FeatureX87, FeatureCX8],
18311824
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
18321825

18331826
foreach P = ["athlon", "athlon-tbird"] in {
1834-
def : Proc<P, [FeatureX87, FeatureCX8, FeatureCMOV, Feature3DNowA,
1827+
def : Proc<P, [FeatureX87, FeatureCX8, FeatureCMOV,
18351828
FeatureNOPL],
18361829
[TuningSlowSHLD, TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
18371830
}
18381831

18391832
foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in {
18401833
def : Proc<P, [FeatureX87, FeatureCX8, FeatureCMOV,
1841-
FeatureSSE1, Feature3DNowA, FeatureFXSR, FeatureNOPL],
1834+
FeatureSSE1, FeatureFXSR, FeatureNOPL],
18421835
[TuningSlowSHLD, TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
18431836
}
18441837

18451838
foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in {
1846-
def : Proc<P, [FeatureX87, FeatureCX8, FeatureSSE2, Feature3DNowA,
1839+
def : Proc<P, [FeatureX87, FeatureCX8, FeatureSSE2,
18471840
FeatureFXSR, FeatureNOPL, FeatureX86_64, FeatureCMOV],
18481841
[TuningFastScalarShiftMasks, TuningSlowSHLD, TuningSlowUAMem16,
18491842
TuningSBBDepBreaking, TuningInsertVZEROUPPER]>;
18501843
}
18511844

18521845
foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in {
1853-
def : Proc<P, [FeatureX87, FeatureCX8, FeatureSSE3, Feature3DNowA,
1846+
def : Proc<P, [FeatureX87, FeatureCX8, FeatureSSE3,
18541847
FeatureFXSR, FeatureNOPL, FeatureCX16, FeatureCMOV,
18551848
FeatureX86_64],
18561849
[TuningFastScalarShiftMasks, TuningSlowSHLD, TuningSlowUAMem16,
@@ -1891,14 +1884,14 @@ def : ProcModel<"znver3", Znver3Model, ProcessorFeatures.ZN3Features,
18911884
def : ProcModel<"znver4", Znver4Model, ProcessorFeatures.ZN4Features,
18921885
ProcessorFeatures.ZN4Tuning>;
18931886

1894-
def : Proc<"geode", [FeatureX87, FeatureCX8, Feature3DNowA],
1887+
def : Proc<"geode", [FeatureX87, FeatureCX8],
18951888
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
18961889

18971890
def : Proc<"winchip-c6", [FeatureX87, FeatureMMX],
18981891
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1899-
def : Proc<"winchip2", [FeatureX87, Feature3DNow],
1892+
def : Proc<"winchip2", [FeatureX87],
19001893
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1901-
def : Proc<"c3", [FeatureX87, Feature3DNow],
1894+
def : Proc<"c3", [FeatureX87],
19021895
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
19031896
def : Proc<"c3-2", [FeatureX87, FeatureCX8, FeatureMMX,
19041897
FeatureSSE1, FeatureFXSR, FeatureCMOV],

‎llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -535,7 +535,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
535535
setOperationAction(ISD::SRL_PARTS, VT, Custom);
536536
}
537537

538-
if (Subtarget.hasSSEPrefetch() || Subtarget.hasThreeDNow())
538+
if (Subtarget.hasSSEPrefetch())
539539
setOperationAction(ISD::PREFETCH , MVT::Other, Custom);
540540

541541
setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);

‎llvm/lib/Target/X86/X86Instr3DNow.td

Lines changed: 37 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
//===----------------------------------------------------------------------===//
1313

1414
class I3DNow<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pat>
15-
: I<o, F, outs, ins, asm, pat>, Requires<[Has3DNow]> {
15+
: I<o, F, outs, ins, asm, pat> {
1616
}
1717

1818
class I3DNow_binop<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat>
@@ -25,66 +25,53 @@ class I3DNow_conv<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat>
2525
: I3DNow<o, F, (outs VR64:$dst), ins,
2626
!strconcat(Mnemonic, "\t{$src, $dst|$dst, $src}"), pat>, ThreeDNow;
2727

28-
multiclass I3DNow_binop_rm_int<bits<8> opc, string Mn,
29-
X86FoldableSchedWrite sched, bit Commutable = 0,
30-
string Ver = ""> {
28+
multiclass I3DNow_binop_rm<bits<8> opc, string Mn,
29+
X86FoldableSchedWrite sched, bit Commutable = 0> {
3130
let isCommutable = Commutable in
3231
def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn,
33-
[(set VR64:$dst, (!cast<Intrinsic>(
34-
!strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1, VR64:$src2))]>,
35-
Sched<[sched]>;
32+
[]>, Sched<[sched]>;
3633
def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn,
37-
[(set VR64:$dst, (!cast<Intrinsic>(
38-
!strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1,
39-
(bitconvert (load_mmx addr:$src2))))]>,
40-
Sched<[sched.Folded, sched.ReadAfterFold]>;
34+
[]>, Sched<[sched.Folded, sched.ReadAfterFold]>;
4135
}
4236

43-
multiclass I3DNow_conv_rm_int<bits<8> opc, string Mn,
44-
X86FoldableSchedWrite sched, string Ver = ""> {
37+
multiclass I3DNow_conv_rm<bits<8> opc, string Mn,
38+
X86FoldableSchedWrite sched> {
4539
def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src), Mn,
46-
[(set VR64:$dst, (!cast<Intrinsic>(
47-
!strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src))]>,
48-
Sched<[sched]>;
40+
[]>, Sched<[sched]>;
4941
def rm : I3DNow_conv<opc, MRMSrcMem, (ins i64mem:$src), Mn,
50-
[(set VR64:$dst, (!cast<Intrinsic>(
51-
!strconcat("int_x86_3dnow", Ver, "_", Mn))
52-
(bitconvert (load_mmx addr:$src))))]>,
53-
Sched<[sched.Folded, sched.ReadAfterFold]>;
42+
[]>, Sched<[sched.Folded, sched.ReadAfterFold]>;
5443
}
5544

56-
defm PAVGUSB : I3DNow_binop_rm_int<0xBF, "pavgusb", SchedWriteVecALU.MMX, 1>;
57-
defm PF2ID : I3DNow_conv_rm_int<0x1D, "pf2id", WriteCvtPS2I>;
58-
defm PFACC : I3DNow_binop_rm_int<0xAE, "pfacc", WriteFAdd>;
59-
defm PFADD : I3DNow_binop_rm_int<0x9E, "pfadd", WriteFAdd, 1>;
60-
defm PFCMPEQ : I3DNow_binop_rm_int<0xB0, "pfcmpeq", WriteFAdd, 1>;
61-
defm PFCMPGE : I3DNow_binop_rm_int<0x90, "pfcmpge", WriteFAdd>;
62-
defm PFCMPGT : I3DNow_binop_rm_int<0xA0, "pfcmpgt", WriteFAdd>;
63-
defm PFMAX : I3DNow_binop_rm_int<0xA4, "pfmax", WriteFAdd>;
64-
defm PFMIN : I3DNow_binop_rm_int<0x94, "pfmin", WriteFAdd>;
65-
defm PFMUL : I3DNow_binop_rm_int<0xB4, "pfmul", WriteFAdd, 1>;
66-
defm PFRCP : I3DNow_conv_rm_int<0x96, "pfrcp", WriteFAdd>;
67-
defm PFRCPIT1 : I3DNow_binop_rm_int<0xA6, "pfrcpit1", WriteFAdd>;
68-
defm PFRCPIT2 : I3DNow_binop_rm_int<0xB6, "pfrcpit2", WriteFAdd>;
69-
defm PFRSQIT1 : I3DNow_binop_rm_int<0xA7, "pfrsqit1", WriteFAdd>;
70-
defm PFRSQRT : I3DNow_conv_rm_int<0x97, "pfrsqrt", WriteFAdd>;
71-
defm PFSUB : I3DNow_binop_rm_int<0x9A, "pfsub", WriteFAdd, 1>;
72-
defm PFSUBR : I3DNow_binop_rm_int<0xAA, "pfsubr", WriteFAdd, 1>;
73-
defm PI2FD : I3DNow_conv_rm_int<0x0D, "pi2fd", WriteCvtI2PS>;
74-
defm PMULHRW : I3DNow_binop_rm_int<0xB7, "pmulhrw", SchedWriteVecIMul.MMX, 1>;
45+
defm PAVGUSB : I3DNow_binop_rm<0xBF, "pavgusb", SchedWriteVecALU.MMX, 1>;
46+
defm PF2ID : I3DNow_conv_rm<0x1D, "pf2id", WriteCvtPS2I>;
47+
defm PFACC : I3DNow_binop_rm<0xAE, "pfacc", WriteFAdd>;
48+
defm PFADD : I3DNow_binop_rm<0x9E, "pfadd", WriteFAdd, 1>;
49+
defm PFCMPEQ : I3DNow_binop_rm<0xB0, "pfcmpeq", WriteFAdd, 1>;
50+
defm PFCMPGE : I3DNow_binop_rm<0x90, "pfcmpge", WriteFAdd>;
51+
defm PFCMPGT : I3DNow_binop_rm<0xA0, "pfcmpgt", WriteFAdd>;
52+
defm PFMAX : I3DNow_binop_rm<0xA4, "pfmax", WriteFAdd>;
53+
defm PFMIN : I3DNow_binop_rm<0x94, "pfmin", WriteFAdd>;
54+
defm PFMUL : I3DNow_binop_rm<0xB4, "pfmul", WriteFAdd, 1>;
55+
defm PFRCP : I3DNow_conv_rm<0x96, "pfrcp", WriteFAdd>;
56+
defm PFRCPIT1 : I3DNow_binop_rm<0xA6, "pfrcpit1", WriteFAdd>;
57+
defm PFRCPIT2 : I3DNow_binop_rm<0xB6, "pfrcpit2", WriteFAdd>;
58+
defm PFRSQIT1 : I3DNow_binop_rm<0xA7, "pfrsqit1", WriteFAdd>;
59+
defm PFRSQRT : I3DNow_conv_rm<0x97, "pfrsqrt", WriteFAdd>;
60+
defm PFSUB : I3DNow_binop_rm<0x9A, "pfsub", WriteFAdd, 1>;
61+
defm PFSUBR : I3DNow_binop_rm<0xAA, "pfsubr", WriteFAdd, 1>;
62+
defm PI2FD : I3DNow_conv_rm<0x0D, "pi2fd", WriteCvtI2PS>;
63+
defm PMULHRW : I3DNow_binop_rm<0xB7, "pmulhrw", SchedWriteVecIMul.MMX, 1>;
7564

76-
let SchedRW = [WriteEMMS],
77-
Defs = [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
78-
ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] in
65+
let SchedRW = [WriteEMMS] in
7966
def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms",
80-
[(int_x86_mmx_femms)]>, TB;
67+
[]>, TB;
8168

8269
let SchedRW = [WriteLoad] in {
83-
let Predicates = [Has3DNow, NoSSEPrefetch] in
8470
def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i8mem:$addr),
8571
"prefetch\t$addr",
86-
[(prefetch addr:$addr, timm, timm, (i32 1))]>, TB;
72+
[]>, TB;
8773

74+
// Note: PREFETCHW is the only instruction in this file which is NOT specific to 3DNow!
8875
def PREFETCHW : I<0x0D, MRM1m, (outs), (ins i8mem:$addr), "prefetchw\t$addr",
8976
[(prefetch addr:$addr, (i32 1), (i32 PrefetchWLevel), (i32 1))]>,
9077
TB, Requires<[HasPrefetchW]>;
@@ -94,8 +81,8 @@ def PREFETCHWT1 : I<0x0D, MRM2m, (outs), (ins i8mem:$addr), "prefetchwt1\t$addr"
9481
}
9582

9683
// "3DNowA" instructions
97-
defm PF2IW : I3DNow_conv_rm_int<0x1C, "pf2iw", WriteCvtPS2I, "a">;
98-
defm PI2FW : I3DNow_conv_rm_int<0x0C, "pi2fw", WriteCvtI2PS, "a">;
99-
defm PFNACC : I3DNow_binop_rm_int<0x8A, "pfnacc", WriteFAdd, 0, "a">;
100-
defm PFPNACC : I3DNow_binop_rm_int<0x8E, "pfpnacc", WriteFAdd, 0, "a">;
101-
defm PSWAPD : I3DNow_conv_rm_int<0xBB, "pswapd", SchedWriteShuffle.MMX, "a">;
84+
defm PF2IW : I3DNow_conv_rm<0x1C, "pf2iw", WriteCvtPS2I>;
85+
defm PI2FW : I3DNow_conv_rm<0x0C, "pi2fw", WriteCvtI2PS>;
86+
defm PFNACC : I3DNow_binop_rm<0x8A, "pfnacc", WriteFAdd, 0>;
87+
defm PFPNACC : I3DNow_binop_rm<0x8E, "pfpnacc", WriteFAdd, 0>;
88+
defm PSWAPD : I3DNow_conv_rm<0xBB, "pswapd", SchedWriteShuffle.MMX>;

‎llvm/lib/Target/X86/X86InstrPredicates.td

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -50,8 +50,6 @@ def HasCMOV : Predicate<"Subtarget->canUseCMOV()">;
5050
def NoCMOV : Predicate<"!Subtarget->canUseCMOV()">;
5151
def HasNOPL : Predicate<"Subtarget->hasNOPL()">;
5252
def HasMMX : Predicate<"Subtarget->hasMMX()">;
53-
def Has3DNow : Predicate<"Subtarget->hasThreeDNow()">;
54-
def Has3DNowA : Predicate<"Subtarget->hasThreeDNowA()">;
5553
def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
5654
def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
5755
def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
@@ -141,7 +139,6 @@ def HasSGX : Predicate<"Subtarget->hasSGX()">;
141139
def HasSM3 : Predicate<"Subtarget->hasSM3()">;
142140
def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
143141
def HasSSEPrefetch : Predicate<"Subtarget->hasSSEPrefetch()">;
144-
def NoSSEPrefetch : Predicate<"!Subtarget->hasSSEPrefetch()">;
145142
def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
146143
def HasPREFETCHI : Predicate<"Subtarget->hasPREFETCHI()">;
147144
def HasPrefetchW : Predicate<"Subtarget->hasPrefetchW()">;

‎llvm/lib/Target/X86/X86Schedule.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -481,7 +481,7 @@ defm WriteAESKeyGen : X86SchedWritePair<ReadAfterVecXLd>; // Key Generation.
481481
// Carry-less multiplication instructions.
482482
defm WriteCLMul : X86SchedWritePair<ReadAfterVecXLd>;
483483

484-
// EMMS/FEMMS
484+
// EMMS
485485
def WriteEMMS : SchedWrite;
486486

487487
// Load/store MXCSR

‎llvm/lib/Target/X86/X86ScheduleZnver3.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1301,7 +1301,7 @@ defm : Zn3WriteResXMMPair<WriteAESKeyGen, [Zn3FPAES01], 4, [1], 1>; // Key Gener
13011301
// Carry-less multiplication instructions.
13021302
defm : Zn3WriteResXMMPair<WriteCLMul, [Zn3FPCLM01], 4, [4], 4>;
13031303

1304-
// EMMS/FEMMS
1304+
// EMMS
13051305
defm : Zn3WriteResInt<WriteEMMS, [Zn3ALU0123], 2, [1], 1>; // FIXME: latency not from llvm-exegesis
13061306

13071307
// Load/store MXCSR

‎llvm/lib/Target/X86/X86ScheduleZnver4.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1341,7 +1341,7 @@ defm : Zn4WriteResXMMPair<WriteAESKeyGen, [Zn4FPAES01], 4, [1], 1>; // Key Gener
13411341
// Carry-less multiplication instructions.
13421342
defm : Zn4WriteResXMMPair<WriteCLMul, [Zn4FPCLM01], 4, [4], 4>;
13431343

1344-
// EMMS/FEMMS
1344+
// EMMS
13451345
defm : Zn4WriteResInt<WriteEMMS, [Zn4ALU0123], 2, [1], 1>; // FIXME: latency not from llvm-exegesis
13461346

13471347
// Load/store MXCSR

‎llvm/lib/Target/X86/X86Subtarget.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -289,7 +289,7 @@ void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU,
289289
IsUnalignedMem16Slow = false;
290290

291291
LLVM_DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
292-
<< ", 3DNowLevel " << X863DNowLevel << ", 64bit "
292+
<< ", MMX " << HasMMX << ", 64bit "
293293
<< HasX86_64 << "\n");
294294
if (Is64Bit && !HasX86_64)
295295
report_fatal_error("64-bit code requested on a subtarget that doesn't "

0 commit comments

Comments
 (0)