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[SVE ACLE] Support FMAX and FMIN with #0.0 and #1.0
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10 files changed

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-157
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10 files changed

+997
-157
lines changed

‎gcc/config/aarch64/aarch64-sve.md

Lines changed: 48 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -2794,22 +2794,23 @@
27942794
[(set_attr "movprfx" "*,*,*,*,yes,yes")]
27952795
)
27962796

2797-
;; Unpredicated floating-point multiplication.
2798-
(define_expand "mul<mode>3"
2797+
;; Unpredicated floating-point binary operations that can take a single-bit
2798+
;; immediate.
2799+
(define_expand "<optab><mode>3"
27992800
[(set (match_operand:SVE_F 0 "register_operand")
28002801
(unspec:SVE_F
28012802
[(match_dup 3)
28022803
(const_int SVE_ALLOW_NEW_FAULTS)
28032804
(match_operand:SVE_F 1 "register_operand")
28042805
(match_operand:SVE_F 2 "aarch64_sve_float_mul_operand")]
2805-
UNSPEC_COND_MUL))]
2806+
SVE_COND_FP_BINARY_I1))]
28062807
"TARGET_SVE"
28072808
{
28082809
operands[3] = force_reg (<VPRED>mode, CONSTM1_RTX (<VPRED>mode));
28092810
}
28102811
)
28112812

2812-
;; Floating-point multiplication predicated with a PTRUE.
2813+
;; Predicated floating-point multiplication.
28132814
(define_insn_and_split "@aarch64_pred_mul<mode>"
28142815
[(set (match_operand:SVE_F 0 "register_operand" "=w, w, w, ?&w, ?&w")
28152816
(unspec:SVE_F
@@ -2835,6 +2836,24 @@
28352836
[(set_attr "movprfx" "*,*,*,yes,yes")]
28362837
)
28372838

2839+
;; Predicated floating-point MAX/MIN.
2840+
(define_insn "@aarch64_pred_<optab><mode>"
2841+
[(set (match_operand:SVE_F 0 "register_operand" "=w, w, ?&w, ?&w")
2842+
(unspec:SVE_F
2843+
[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl, Upl")
2844+
(match_operand:SI 4 "const_int_operand")
2845+
(match_operand:SVE_F 2 "register_operand" "%0, 0, w, w")
2846+
(match_operand:SVE_F 3 "aarch64_sve_float_maxmin_operand" "vsB, w, vsB, w")]
2847+
SVE_COND_MAXMIN))]
2848+
"TARGET_SVE"
2849+
"@
2850+
<sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, #%3
2851+
<sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
2852+
movprfx\t%0, %2\;<sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, #%3
2853+
movprfx\t%0, %2\;<sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>"
2854+
[(set_attr "movprfx" "*,*,yes,yes")]
2855+
)
2856+
28382857
;; Unpredicated floating-point binary operations (post-RA only).
28392858
;; These are generated by splitting a predicated instruction whose
28402859
;; predicate is unused.
@@ -3451,26 +3470,28 @@
34513470
[(set_attr "movprfx" "yes")]
34523471
)
34533472

3454-
;; Predicated FMUL operations with select.
3455-
(define_expand "@cond_mul<mode>"
3473+
;; Predicated floating-point binary operations with select, covering
3474+
;; operations that can take a single-bit immediate.
3475+
(define_expand "@cond_<optab><mode>"
34563476
[(set (match_operand:SVE_F 0 "register_operand")
34573477
(unspec:SVE_F
34583478
[(match_operand:<VPRED> 1 "register_operand")
34593479
(unspec:SVE_F
34603480
[(match_dup 1)
34613481
(const_int SVE_FORBID_NEW_FAULTS)
34623482
(match_operand:SVE_F 2 "register_operand")
3463-
(match_operand:SVE_F 3 "aarch64_sve_float_mul_operand")]
3464-
UNSPEC_COND_MUL)
3483+
(match_operand:SVE_F 3 "aarch64_sve_float_<sve_imm_pred>_operand")]
3484+
SVE_COND_FP_BINARY_I1)
34653485
(match_operand:SVE_F 4 "aarch64_simd_reg_or_zero")]
34663486
UNSPEC_SEL))]
34673487
"TARGET_SVE"
34683488
{
3469-
if (rtx_equal_p (operands[3], operands[4]))
3489+
if (!CONSTANT_P (operands[4]) && rtx_equal_p (operands[3], operands[4]))
34703490
std::swap (operands[2], operands[3]);
34713491
})
34723492

3473-
;; Predicated FMUL operations with select matching second operand.
3493+
;; Predicated floating-point binary operations with select matching second
3494+
;; operand, covering operations that can take a single-bit immediate.
34743495
(define_insn "*cond_mul<mode>_2"
34753496
[(set (match_operand:SVE_F 0 "register_operand" "=w, w, ?&w, ?&w")
34763497
(unspec:SVE_F
@@ -3479,21 +3500,22 @@
34793500
[(match_dup 1)
34803501
(match_operand 4)
34813502
(match_operand:SVE_F 2 "register_operand" "0, 0, w, w")
3482-
(match_operand:SVE_F 3 "aarch64_sve_float_mul_operand" "vsM, w, vsM, w")]
3483-
UNSPEC_COND_MUL)
3503+
(match_operand:SVE_F 3 "aarch64_sve_float_<sve_imm_pred>_operand" "<sve_imm_con>, w, <sve_imm_con>, w")]
3504+
SVE_COND_FP_BINARY_I1)
34843505
(match_dup 2)]
34853506
UNSPEC_SEL))]
34863507
"TARGET_SVE"
34873508
"@
3488-
fmul\t%0.<Vetype>, %1/m, %0.<Vetype>, #%3
3489-
fmul\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
3490-
movprfx\t%0, %2\;fmul\t%0.<Vetype>, %1/m, %0.<Vetype>, #%3
3491-
movprfx\t%0, %2\;fmul\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>"
3509+
<sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, #%3
3510+
<sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
3511+
movprfx\t%0, %2\;<sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, #%3
3512+
movprfx\t%0, %2\;<sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>"
34923513
[(set_attr "movprfx" "*,*,yes,yes")]
34933514
)
34943515

3495-
;; Predicated FMUL operations in which the values of inactive lanes are
3496-
;; distinct from the other inputs.
3516+
;; Predicated floating-point binary operations in which the values of inactive
3517+
;; lanes are distinct from the other inputs, covering operations that can take
3518+
;; a single-bit immediate.
34973519
(define_insn "*cond_mul<mode>_any"
34983520
[(set (match_operand:SVE_F 0 "register_operand" "=&w, &w, &w, &w, &w, &w, ?&w, ?&w")
34993521
(unspec:SVE_F
@@ -3502,18 +3524,18 @@
35023524
[(match_dup 1)
35033525
(match_operand 5)
35043526
(match_operand:SVE_F 2 "register_operand" "%0, 0, w, w, w, w, w, w")
3505-
(match_operand:SVE_F 3 "aarch64_sve_float_mul_operand" "vsM, w, vsM, w, vsM, w, vsM, w")]
3506-
UNSPEC_COND_MUL)
3527+
(match_operand:SVE_F 3 "aarch64_sve_float_<sve_imm_pred>_operand" "<sve_imm_con>, w, <sve_imm_con>, w, <sve_imm_con>, w, <sve_imm_con>, w")]
3528+
SVE_COND_FP_BINARY_I1)
35073529
(match_operand:SVE_F 4 "aarch64_simd_reg_or_zero" "Dz, Dz, Dz, Dz, 0, 0, w, w")]
35083530
UNSPEC_SEL))]
35093531
"TARGET_SVE"
35103532
"@
3511-
movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;fmul\t%0.<Vetype>, %1/m, %0.<Vetype>, #%3
3512-
movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;fmul\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
3513-
movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;fmul\t%0.<Vetype>, %1/m, %0.<Vetype>, #%3
3514-
movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;fmul\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
3515-
movprfx\t%0.<Vetype>, %1/m, %2.<Vetype>\;fmul\t%0.<Vetype>, %1/m, %0.<Vetype>, #%3
3516-
movprfx\t%0.<Vetype>, %1/m, %2.<Vetype>\;fmul\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
3533+
movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;<sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, #%3
3534+
movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;<sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
3535+
movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;<sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, #%3
3536+
movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;<sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
3537+
movprfx\t%0.<Vetype>, %1/m, %2.<Vetype>\;<sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, #%3
3538+
movprfx\t%0.<Vetype>, %1/m, %2.<Vetype>\;<sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
35173539
#
35183540
#"
35193541
[(set_attr "movprfx" "yes")]

‎gcc/config/aarch64/constraints.md

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -439,6 +439,13 @@
439439
and FSUB operations."
440440
(match_operand 0 "aarch64_sve_float_arith_immediate"))
441441

442+
;; "B" for "bound".
443+
(define_constraint "vsB"
444+
"@internal
445+
A constraint that matches an immediate operand valid for SVE FMAX
446+
and FMIN operations."
447+
(match_operand 0 "aarch64_sve_float_maxmin_immediate"))
448+
442449
(define_constraint "vsM"
443450
"@internal
444451
A constraint that matches an imediate operand valid for SVE FMUL

‎gcc/config/aarch64/iterators.md

Lines changed: 21 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1628,14 +1628,16 @@
16281628
UNSPEC_COND_FMAXNM
16291629
UNSPEC_COND_FMINNM])
16301630

1631+
(define_int_iterator SVE_COND_FP_BINARY_I1 [UNSPEC_COND_MUL
1632+
UNSPEC_COND_FMAX UNSPEC_COND_FMIN
1633+
UNSPEC_COND_FMAXNM
1634+
UNSPEC_COND_FMINNM])
1635+
16311636
(define_int_iterator SVE_COND_FP_BINARY_REG [UNSPEC_COND_FABD
1632-
UNSPEC_COND_DIV
1633-
UNSPEC_COND_FMAX UNSPEC_COND_FMIN
1634-
UNSPEC_COND_FMAXNM
1635-
UNSPEC_COND_FMINNM])
1637+
UNSPEC_COND_DIV])
16361638

16371639
(define_int_iterator SVE_COND_MAXMIN [UNSPEC_COND_FMAXNM UNSPEC_COND_FMINNM
1638-
UNSPEC_COND_FMAX UNSPEC_COND_FMIN])
1640+
UNSPEC_COND_FMAX UNSPEC_COND_FMIN])
16391641

16401642
(define_int_iterator SVE_COND_FP_TERNARY [UNSPEC_COND_FMLA
16411643
UNSPEC_COND_FMLS
@@ -1975,3 +1977,17 @@
19751977
(UNSPEC_COND_FMAX "true")
19761978
(UNSPEC_COND_FMINNM "true")
19771979
(UNSPEC_COND_FMAXNM "true")])
1980+
1981+
;; The fragment of an SVE immediate predicate to use for an unspec code.
1982+
(define_int_attr sve_imm_pred [(UNSPEC_COND_MUL "mul")
1983+
(UNSPEC_COND_FMAX "maxmin")
1984+
(UNSPEC_COND_FMIN "maxmin")
1985+
(UNSPEC_COND_FMAXNM "maxmin")
1986+
(UNSPEC_COND_FMINNM "maxmin")])
1987+
1988+
;; The SVE immediate constraint to use for an unspec code.
1989+
(define_int_attr sve_imm_con [(UNSPEC_COND_MUL "vsM")
1990+
(UNSPEC_COND_FMAX "vsB")
1991+
(UNSPEC_COND_FMIN "vsB")
1992+
(UNSPEC_COND_FMAXNM "vsB")
1993+
(UNSPEC_COND_FMINNM "vsB")])

‎gcc/config/aarch64/predicates.md

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -642,6 +642,11 @@
642642
(and (match_code "const,const_vector")
643643
(match_test "aarch64_sve_float_mul_immediate_p (op)")))
644644

645+
(define_predicate "aarch64_sve_float_maxmin_immediate"
646+
(and (match_code "const_vector")
647+
(ior (match_test "op == CONST0_RTX (GET_MODE (op))")
648+
(match_test "op == CONST1_RTX (GET_MODE (op))"))))
649+
645650
(define_predicate "aarch64_sve_arith_operand"
646651
(ior (match_operand 0 "register_operand")
647652
(match_operand 0 "aarch64_sve_arith_immediate")))
@@ -696,6 +701,10 @@
696701
(ior (match_operand 0 "register_operand")
697702
(match_operand 0 "aarch64_sve_float_mul_immediate")))
698703

704+
(define_predicate "aarch64_sve_float_maxmin_operand"
705+
(ior (match_operand 0 "register_operand")
706+
(match_operand 0 "aarch64_sve_float_maxmin_immediate")))
707+
699708
(define_predicate "aarch64_sve_vec_perm_operand"
700709
(ior (match_operand 0 "register_operand")
701710
(match_operand 0 "aarch64_constant_vector_operand")))

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