add sfence_vma key

Author: qbojj

coreblocks/func_blocks/fu/priv.py

@@ -4,7 +4,7 @@
 
 from enum import IntFlag, auto, unique
 from typing import Sequence
-from coreblocks.arch.isa_consts import Funct12, Funct3, Funct7, Opcode, PrivilegeLevel, SatpMode
+from coreblocks.arch.isa_consts import Funct12, Funct3, Funct7, Opcode, PrivilegeLevel
 
 
 from transactron import *
@@ -27,6 +27,7 @@
     UnsafeInstructionResolvedKey,
     FlushICacheKey,
     WaitForInterruptResumeKey,
+    SFenceVMAKey,
 )
 from coreblocks.func_blocks.interface.func_protocols import FuncUnit
 
@@ -89,6 +90,8 @@ def elaborate(self, platform):
         instr_imm = Signal(self.gen_params.isa.xlen)
         instr_s1_val = Signal(self.gen_params.isa.xlen)
         instr_s2_val = Signal(self.gen_params.isa.xlen)
+        instr_s1_x0 = Signal()
+        instr_s2_x0 = Signal()
 
         mret = self.dm.get_dependency(MretKey())
         sret = self.dm.get_optional_dependency(SretKey())
@@ -97,6 +100,7 @@ def elaborate(self, platform):
         csr = self.dm.get_dependency(CSRInstancesKey())
         priv_mode = csr.m_mode.priv_mode
         flush_icache = self.dm.get_dependency(FlushICacheKey())
+        sfence_vma = self.dm.get_optional_dependency(SFenceVMAKey())
         resume_core = self.dm.get_dependency(UnsafeInstructionResolvedKey())
 
         @def_method(m, self.issue_decoded, ready=~instr_valid)
@@ -108,6 +112,8 @@ def _(arg):
                 instr_fn.eq(arg.decode_fn),
                 instr_s1_val.eq(arg.s1_val),
                 instr_s2_val.eq(arg.s2_val),
+                instr_s1_x0.eq(arg.rp_s1_reg == 0),
+                instr_s2_x0.eq(arg.rp_s2_reg == 0),
                 instr_imm.eq(arg.imm),
             ]
 
@@ -150,8 +156,10 @@ def _(arg):
                     with branch(info.side_fx & (instr_fn == PrivilegedFn.Fn.SRET) & ~illegal_sret):
                         sret(m)
 
-                    # TODO: implement proper SFENCE.VMA, for BARE only - NO-OP is ok
-                    assert self.gen_params.vmem_params.supported_schemes == {SatpMode.BARE}
+                    if self.gen_params.vmem_params.supported_schemes > {SatpMode.BARE}:
+                        assert sfence_vma is not None
+                        with branch(info.side_fx & (instr_fn == PrivilegedFn.Fn.SFENCEVMA) & ~illegal_sfencevma):
+                            sfence_vma[0](m, vaddr=instr_s1_val, asid=instr_s2_val, all_vaddrs=instr_s1_x0, all_asids=instr_s2_x0)
 
                 with branch(info.side_fx & (instr_fn == PrivilegedFn.Fn.FENCEI)):
                     flush_icache(m)

coreblocks/interface/keys.py

@@ -27,6 +27,7 @@
     "CoreStateKey",
     "CSRListKey",
     "FlushICacheKey",
+    "SFenceVMAKey",
     "RollbackKey",
     "InstructionTaggedCounterKey",
 ]
@@ -117,6 +118,16 @@ class FlushICacheKey(SimpleKey[Method]):
     pass
 
 
+@dataclass(frozen=True)
+class SFenceVMAKey(UnifierKey, unifier=MethodProduct.create):
+    """
+    Collects SFENCE.VMA handlers to invalidate translation caches.
+    Expected layout is `AddressTranslationLayouts.sfence_vma`.
+    """
+
+    pass
+
+
 @dataclass(frozen=True)
 class RollbackKey(UnifierKey, unifier=MethodProduct.create):
     """

coreblocks/interface/layouts.py

@@ -181,6 +181,13 @@ def __init__(self, gen_params: GenParams):
             ("access_fault", 1),
         )
 
+        self.sfence_vma = make_layout(
+            fields.vaddr,
+            ("asid", gen_params.vmem_params.asidlen),
+            ("all_vaddrs", 1),
+            ("all_asids", 1),
+        )
+
 
 class SchedulerLayouts:
     """Layouts used in the scheduler."""