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Make RS feed FUs with garbage if flushing
See #598
1 parent c3edca0 commit 0fb0c82

2 files changed

Lines changed: 16 additions & 5 deletions

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coreblocks/func_blocks/fu/common/rs.py

Lines changed: 12 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,9 @@
77
from coreblocks.params import GenParams
88
from coreblocks.arch import OpType
99
from coreblocks.interface.layouts import RSLayouts
10+
from coreblocks.interface.keys import InstructionPrecommitKey
1011
from transactron.lib.metrics import HwExpHistogram, TaggedLatencyMeasurer
11-
from transactron.utils import RecordDict
12+
from transactron.utils import DependencyContext, RecordDict
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from transactron.utils import assign
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from transactron.utils.assign import AssignType
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from transactron.utils.amaranth_ext.functions import popcount
@@ -44,6 +45,8 @@ def __init__(
4445
self.ready_for = [list(op_list) for op_list in ready_for]
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self.get_ready_list = [Method(o=self.layouts.get_ready_list_out, nonexclusive=True) for _ in self.ready_for]
4647

48+
self.dependency_manager = DependencyContext.get()
49+
4750
self.data = Array(Signal(self.internal_layout) for _ in range(self.rs_entries))
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self.data_ready = Signal(self.rs_entries)
4952

@@ -67,10 +70,14 @@ def elaborate(self, platform) -> TModule:
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def _elaborate(self, m: TModule, selected_id: Value, select_possible: Value, take_vector: Value):
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m.submodules += [self.perf_rs_wait_time, self.perf_num_full]
6972

70-
for i, record in enumerate(self.data):
71-
m.d.comb += self.data_ready[i].eq(
72-
~record.rs_data.rp_s1.bool() & ~record.rs_data.rp_s2.bool() & record.rec_full.bool()
73-
)
73+
with Transaction(name="readiness").body(m):
74+
precommit = self.dependency_manager.get_dependency(InstructionPrecommitKey())
75+
info = precommit(m)
76+
for i, record in enumerate(self.data):
77+
m.d.comb += self.data_ready[i].eq(
78+
(~record.rs_data.rp_s1.bool() & ~record.rs_data.rp_s2.bool() & record.rec_full.bool())
79+
| ~info.side_fx
80+
)
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7582
ready_lists: list[Value] = []
7683
for op_list in self.ready_for:

transactron/core/tmodule.py

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,10 @@ def __iadd__(self, assigns: StatementLike) -> Self:
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class _AvoidingModuleBuilderDomains:
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_m: "TModule"
28+
comb: _AvoidingModuleBuilderDomain
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av_comb: _AvoidingModuleBuilderDomain
30+
top_comb: _AvoidingModuleBuilderDomain
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sync: _AvoidingModuleBuilderDomain
2832

2933
def __init__(self, m: "TModule"):
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object.__setattr__(self, "_m", m)

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