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The current implementation in loads/stores in Coreblocks is very rudimentary. Contrary to the out-of-order nature of the rest of the core, load/store instructions are executed strictly in order. This causes inefficiencies: for example, a load whose address is known and in idempotent memory region must wait for all of the previous loads and stores, even though previous reads can't affect it, and previous stores most probably won't affect it. To implement this, one should first learn about implementation techniques from the literature. For example: * Modern Processor Design - Fundamentals of Superscalar Processors, chapter 5.3 - "Memory Data Flow Techniques" * Microprocessor Architecture - From Simple Pipelines to Chip Multiprocessors, chapter 5.2 - "Memory Accessing Instructions" There are two main tasks: * Modify the core microarchitecture so that instructions can return a speculative value, but stall the retirement until it's certain that the value is correct. This requires decoupling value broadcast with ROB done marking in announcement. * Modify the LSU so that accesses can be reordered. Currently, actual memory accesses are performed in a functional unit, and a special RS takes care of the ordering. It remains to be decided if such a split should be maintained, or a more integrated implementation is warranted.
No due date•0/1 issues closedSuperscalar execution is important for realizing the gains of out-of-order processing. This requires several improvements to the CPU: * Fetching and decoding multiple instructions at a time. (Done.) * Scheduling multiple instructions at a time. * Retiring multiple instructions at a time. * Handling multiple requests to common data structures at the same time. This milestone is factored out from a previous, much wider one, https://github.com/kuznia-rdzeni/coreblocks/milestone/5.
No due date•16/18 issues closedWe should implement F and D extensions (floating-point instructions), and possibly also Zfhmin and Zfh - half-precision floating-point. These extensions require additional registers and the use of CSRs, which might be the most complex part of the implementation. As a stepping stone towards F and D, there are extensions Zfinx, Zdinx, Zhinx, Zhinxmin for floating-point operations in integer registers.
No due date•12/16 issues closedSupporting the machine mode ISA is a prerequisite for supporting OpenSBI, and later - Mimiker or Linux. 1. CSRs. 2. Interrupts. 3. Traps. 4. Performance counters. 5. Other machine-mode CSRs. 6. Physical memory attributes, for proper MMIO support.
No due date•26/28 issues closed