diff --git a/coreblocks/frontend/decode.py b/coreblocks/frontend/decode.py index e6c84b6ae..39a4b5f49 100644 --- a/coreblocks/frontend/decode.py +++ b/coreblocks/frontend/decode.py @@ -53,8 +53,11 @@ def elaborate(self, platform): "regs_l": { # read/writes to phys reg 0 make no effect "rl_dst": Mux(instr_decoder.rd_v, instr_decoder.rd, 0), + "rl_dst_rf": Mux(instr_decoder.rd_v, instr_decoder.rd_rf, 0), "rl_s1": Mux(instr_decoder.rs1_v, instr_decoder.rs1, 0), + "rl_s1_rf" : Mux(instr_decoder.rs1_v, instr_decoder.rs1_rf, 0), "rl_s2": Mux(instr_decoder.rs2_v, instr_decoder.rs2, 0), + "rl_s2_rf" : Mux(instr_decoder.rs2_v, instr_decoder.rs2_rf, 0), }, "imm": instr_decoder.imm, "csr": instr_decoder.csr, diff --git a/coreblocks/frontend/decoder.py b/coreblocks/frontend/decoder.py index 66579dbbd..6050db527 100644 --- a/coreblocks/frontend/decoder.py +++ b/coreblocks/frontend/decoder.py @@ -17,11 +17,11 @@ # Lists which fields are used by which Instruction's types -_rd_itypes = [InstrType.R, InstrType.I, InstrType.U, InstrType.J] +_rd_itypes = [InstrType.R, InstrType.I, InstrType.U, InstrType.J, InstrType.S1I, InstrType.S1IS2, InstrType.S1U] _rs1_itypes = [InstrType.R, InstrType.I, InstrType.S, InstrType.B] -_rs2_itypes = [InstrType.R, InstrType.S, InstrType.B] +_rs2_itypes = [InstrType.R, InstrType.S, InstrType.B, InstrType.S1IS2] @dataclass(frozen=True) @@ -48,6 +48,9 @@ class Encoding: rs1_zero: bool `rs1` field is specifed as constant zero in instruction encoding. Other fields are decoded accordingly to `InstrType`. Default is False. + rs2_zero: bool + `rs2` field is specifed as constant zero in instruction encoding. Other fields are decoded + accordingly to `InstrType`. Default is False. """ opcode: Opcode @@ -55,9 +58,11 @@ class Encoding: funct7: Optional[Funct7] = None funct12: Optional[Funct12] = None _ = KW_ONLY + funct6: Optional[Funct6] = None instr_type_override: Optional[InstrType] = None rd_zero: bool = False rs1_zero: bool = False + rs2_zero: bool = False # @@ -146,9 +151,9 @@ class Encoding: Encoding(Opcode.SYSTEM, Funct3.CSRRC), # csrrc ], OpType.CSR_IMM: [ - Encoding(Opcode.SYSTEM, Funct3.CSRRWI), # csrrwi - Encoding(Opcode.SYSTEM, Funct3.CSRRSI), # csrrsi - Encoding(Opcode.SYSTEM, Funct3.CSRRCI), # csrrci + Encoding(Opcode.SYSTEM, Funct3.CSRRWI, instr_type_override=InstrType.S1U), # csrrwi + Encoding(Opcode.SYSTEM, Funct3.CSRRSI, instr_type_override=InstrType.S1U), # csrrsi + Encoding(Opcode.SYSTEM, Funct3.CSRRCI, instr_type_override=InstrType.S1U), # csrrci ], OpType.MUL: [ Encoding(Opcode.OP, Funct3.MUL, Funct7.MULDIV), # mul @@ -221,6 +226,130 @@ class Encoding: Opcode.SYSTEM, Funct3.PRIV, Funct7.SFENCEVMA, rd_zero=True, instr_type_override=InstrType.R ), # sfence.vma ], + OpType.V_ARITHMETIC : [ + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VADD), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VSUB), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VAND), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VOR), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VXOR), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VSLL), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VSRL), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VSRA), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VMSEQ), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VMSNE), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VMSLTU), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VMSLT), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VMSLEU), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VMSLE), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VMINU), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VMIN), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VMAXU), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VMAX), + Encoding(Opcode.OP_V, Funct3.OPIVV, Funct7(int(Funct6.VADC)*2)), # Funct6.VADC * 2 + 1 is reserved by standard + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VMADC), + Encoding(Opcode.OP_V, Funct3.OPIVV, Funct7(int(Funct6.VSBC)*2)), # Funct6.VSBC * 2 + 1 is reserved by standard + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VMSBC), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VSADDU), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VSADD), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VSSUBU), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VSSUB), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VSMUL), + ], + OpType.V_ARITHMETIC_IMM : [ + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VADD, instr_type_override = InstrType.S1IS2), + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VRSUB, instr_type_override = InstrType.S1IS2), + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VAND, instr_type_override = InstrType.S1IS2), + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VOR, instr_type_override = InstrType.S1IS2), + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VXOR, instr_type_override = InstrType.S1IS2), + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VSLL, instr_type_override = InstrType.S1IS2), + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VSRL, instr_type_override = InstrType.S1IS2), + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VSRA, instr_type_override = InstrType.S1IS2), + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VMSEQ, instr_type_override = InstrType.S1IS2), + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VMSNE, instr_type_override = InstrType.S1IS2), + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VMSLEU, instr_type_override = InstrType.S1IS2), + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VMSLE, instr_type_override = InstrType.S1IS2), + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VMSGTU, instr_type_override = InstrType.S1IS2), + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VMSGT, instr_type_override = InstrType.S1IS2), + Encoding(Opcode.OP_V, Funct3.OPIVI, Funct7(int(Funct6.VADC)*2), instr_type_override = InstrType.S1IS2), + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VMADC, instr_type_override = InstrType.S1IS2), + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VSADDU, instr_type_override = InstrType.S1IS2), + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VSADD, instr_type_override = InstrType.S1IS2), + ], + OpType.V_ARITHMETIC_SCALAR : [ + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VADD), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VSUB), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VRSUB), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VAND), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VOR), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VXOR), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VSLL), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VSRL), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VSRA), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VMSEQ), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VMSNE), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VMSLTU), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VMSLT), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VMSLEU), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VMSLE), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VMSGTU), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VMSGT), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VMINU), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VMIN), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VMAXU), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VMAX), + Encoding(Opcode.OP_V, Funct3.OPIVX, Funct7(int(Funct6.VADC)*2)), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VMADC), + Encoding(Opcode.OP_V, Funct3.OPIVX, Funct7(int(Funct6.VSBC)*2)), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VMSBC), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VSADDU), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VSADD), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VSSUBU), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VSSUB), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VSMUL), + ], + OpType.V_ARITHMETIC_NARROWING :[ + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VNSRL), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VNSRA), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VNCLIP), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VNCLIPU), + ], + OpType.V_ARITHMETIC_NARROWING_IMM :[ + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VNSRL, instr_type_override = InstrType.S1IS2), + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VNSRA, instr_type_override = InstrType.S1IS2), + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VNCLIP, instr_type_override = InstrType.S1IS2), + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VNCLIPU, instr_type_override = InstrType.S1IS2), + ], + OpType.V_ARITHMETIC_NARROWING_SCALAR :[ + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VNSRL), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VNSRA), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VNCLIP), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VNCLIPU), + ], + OpType.V_PERMUTATION : [ + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VMV), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VRGATHER), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VRGATHEREI16), + ], + OpType.V_PERMUTATION_IMM : [ + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VMV, instr_type_override = InstrType.S1IS2), + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VMV1R, instr_type_override = InstrType.S1IS2), + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VRGATHER, instr_type_override = InstrType.S1IS2), + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VSLIDEUP, instr_type_override = InstrType.S1IS2), + Encoding(Opcode.OP_V, Funct3.OPIVI, funct6=Funct6.VSLIDEDOWN, instr_type_override = InstrType.S1IS2), + ], + OpType.V_PERMUTATION_SCALAR : [ + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VMV), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VRGATHER), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VSLIDEUP), + Encoding(Opcode.OP_V, Funct3.OPIVX, funct6=Funct6.VSLIDEDOWN), + ], + OpType.V_REDUCTION : [ + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VWREDSUMU), + Encoding(Opcode.OP_V, Funct3.OPIVV, funct6=Funct6.VWREDSUM), + ], + OpType.V_CONTROL : [ + Encoding(Opcode.OP_V, Funct3.OPCFG), + ], } @@ -301,6 +430,7 @@ def __init__(self, gen: GenParams): self.opcode = Signal(Opcode) self.funct3 = Signal(Funct3) self.funct3_v = Signal() + self.funct6 = Signal(Funct6) self.funct7 = Signal(Funct7) self.funct7_v = Signal() self.funct12 = Signal(Funct12) @@ -308,14 +438,17 @@ def __init__(self, gen: GenParams): # Destination register self.rd = Signal(gen.isa.reg_cnt_log) + self.rd_rf = Signal(RegisterType,reset = RegisterType.X) self.rd_v = Signal() # First source register self.rs1 = Signal(gen.isa.reg_cnt_log) + self.rs1_rf = Signal(RegisterType, reset = RegisterType.X) self.rs1_v = Signal() # Second source register self.rs2 = Signal(gen.isa.reg_cnt_log) + self.rs2_rf = Signal(RegisterType, reset = RegisterType.X) self.rs2_v = Signal() # Immediate @@ -380,7 +513,7 @@ def elaborate(self, platform): m.d.comb += instruction_type.eq(InstrType.I) with m.Case(Opcode.LUI, Opcode.AUIPC): m.d.comb += instruction_type.eq(InstrType.U) - with m.Case(Opcode.OP): + with m.Case(Opcode.OP, Opcode.OP_V): m.d.comb += instruction_type.eq(InstrType.R) with m.Case(Opcode.JAL): m.d.comb += instruction_type.eq(InstrType.J) @@ -394,6 +527,7 @@ def elaborate(self, platform): m.d.comb += [ self._extract(12, self.funct3), self._extract(25, self.funct7), + self._extract(26, self.funct6), self._extract(20, self.funct12), ] @@ -413,9 +547,11 @@ def elaborate(self, platform): (opcode == enc.opcode if enc.opcode is not None else 1) & (self.funct3 == enc.funct3 if enc.funct3 is not None else 1) & (self.funct7 == enc.funct7 if enc.funct7 is not None else 1) + & (self.funct6 == enc.funct6 if enc.funct6 is not None else 1) & (self.funct12 == enc.funct12 if enc.funct12 is not None else 1) & (self.rd == 0 if enc.rd_zero else 1) & (self.rs1 == 0 if enc.rs1_zero else 1) + & (self.rs2 == 0 if enc.rs2_zero else 1) ): m.d.comb += self.optype.eq(encoding_to_optype[enc]) @@ -426,7 +562,7 @@ def elaborate(self, platform): m.d.comb += rs1_invalid.eq(enc.rs1_zero) m.d.comb += self.funct3_v.eq(enc.funct3 is not None) - m.d.comb += self.funct7_v.eq(enc.funct7 is not None) + m.d.comb += self.funct7_v.eq((enc.funct7 is not None) | (enc.funct6 is not None)) m.d.comb += self.funct12_v.eq(enc.funct12 is not None) # Destination and source registers validity @@ -437,6 +573,20 @@ def elaborate(self, platform): self.rs2_v.eq(reduce(or_, (instruction_type == t for t in _rs2_itypes)) & ~self.funct12_v), ] + # Vector control instruction corrections + + high_bits = Signal(2) + m.d.comb += self._extract(30, high_bits) + with m.If(self.optype == OpType.V_CONTROL): + with m.Switch(high_bits): + with m.Case(0x0, 0x1): + m.d.comb += instruction_type.eq(InstrType.I) + with m.Case(0x2): + m.d.comb += instruction_type.eq(InstrType.R) + with m.Case(0x3): + m.d.comb += instruction_type.eq(InstrType.S1I) + + # Immediate iimm12 = Signal(signed(12)) @@ -445,6 +595,7 @@ def elaborate(self, platform): uimm20 = Signal(unsigned(20)) jimm20 = Signal(signed(21)) uimm5 = Signal(unsigned(5)) + imm5 = Signal(signed(5)) instr = self.instr @@ -455,6 +606,7 @@ def elaborate(self, platform): self._extract(12, uimm20), jimm20.eq(Cat(0, instr[21:31], instr[20], instr[12:20], instr[31])), self._extract(15, uimm5), + self._extract(15, imm5), ] with m.If((opcode == Opcode.OP_IMM) & ((self.funct3 == Funct3.SLL) | (self.funct3 == Funct3.SR))): @@ -471,6 +623,17 @@ def elaborate(self, platform): m.d.comb += self.imm.eq(uimm20 << (self.gen.isa.xlen - 20)) with m.Case(InstrType.J): m.d.comb += self.imm.eq(jimm20) + with m.Case(InstrType.S1U): + m.d.comb += [ + self.imm.eq(uimm5), + self.rs1_v.eq(0), + ] + with m.Case(InstrType.S1I, InstrType.S1IS2): + m.d.comb += [ + self.imm.eq(imm5), + self.rs1_v.eq(0), + ] + # Fence parameters @@ -480,17 +643,25 @@ def elaborate(self, platform): self._extract(28, self.fm), ] - # CSR address + # CSR address and constant for vector control instructions m.d.comb += self._extract(20, self.csr) - # CSR with immediate correction - - with m.If(self.optype == OpType.CSR_IMM): + # Register types + with m.If((self.opcode == Opcode.OP_V)): m.d.comb += [ - self.imm.eq(uimm5), - self.rs1_v.eq(0), - ] + self.rs1_rf.eq(RegisterType.V), + self.rs2_rf.eq(RegisterType.V), + self.rd_rf.eq(RegisterType.V), + ] + with m.If((self.opcode == Opcode.OP_V) & ((self.optype == OpType.V_ARITHMETIC_SCALAR) | (self.optype == OpType.V_PERMUTATION_SCALAR) | (self.optype == OpType.V_ARITHMETIC_NARROWING_SCALAR))): + m.d.comb += self.rs1_rf.eq(RegisterType.X) + with m.If((self.opcode == Opcode.OP_V) & (self.funct3 == Funct3.OPCFG) ): + m.d.comb += [ + self.rs1_rf.eq(RegisterType.X), + self.rs2_rf.eq(RegisterType.X), + self.rd_rf.eq(RegisterType.X), + ] # Instruction simplification diff --git a/coreblocks/params/configurations.py b/coreblocks/params/configurations.py index 84ece0631..ff75fbf24 100644 --- a/coreblocks/params/configurations.py +++ b/coreblocks/params/configurations.py @@ -112,3 +112,6 @@ def replace(self, **kwargs): phys_regs_bits=7, _implied_extensions=Extension.I, ) + +# Core configuration with vector extension +vector_core_config = CoreConfiguration(_implied_extensions = Extension.V) diff --git a/coreblocks/params/isa.py b/coreblocks/params/isa.py index 1bf3fbdfd..916bdf1b4 100644 --- a/coreblocks/params/isa.py +++ b/coreblocks/params/isa.py @@ -6,12 +6,14 @@ "InstrType", "Opcode", "Funct3", + "Funct6", "Funct7", "Funct12", "Extension", "FenceTarget", "FenceFm", "ISA", + "RegisterType", ] @@ -23,34 +25,81 @@ class InstrType(Enum): B = 3 U = 4 J = 5 + S1U = 6 # Unsigned imm in RS1 + S1I = 7 # Imm in RS1 + S1IS2 = 8 # Imm in RS1, valid RS2 @unique class Opcode(IntEnum, shape=5): + LOAD = 0b00000 + MISC_MEM = 0b00011 OP_IMM = 0b00100 - LUI = 0b01101 AUIPC = 0b00101 + STORE = 0b01000 OP = 0b01100 + LUI = 0b01101 OP32 = 0b01110 - JAL = 0b11011 - JALR = 0b11001 + OP_V = 0b10101 BRANCH = 0b11000 - LOAD = 0b00000 - STORE = 0b01000 - MISC_MEM = 0b00011 + JALR = 0b11001 + JAL = 0b11011 SYSTEM = 0b11100 class Funct3(IntEnum, shape=3): - JALR = BEQ = B = ADD = SUB = FENCE = PRIV = MUL = MULW = 0b000 - BNE = H = SLL = FENCEI = CSRRW = MULH = BCLR = BINV = BSET = CLZ = CPOP = CTZ = ROL = SEXTB = SEXTH = CLMUL = 0b001 - W = SLT = CSRRS = MULHSU = SH1ADD = CLMULR = 0b010 - SLTU = CSRRC = MULHU = CLMULH = 0b011 - BLT = BU = XOR = DIV = DIVW = SH2ADD = MIN = XNOR = ZEXTH = 0b100 - BGE = HU = SR = CSRRWI = DIVU = DIVUW = BEXT = ORCB = REV8 = ROR = MINU = 0b101 - BLTU = OR = CSRRSI = REM = REMW = SH3ADD = MAX = ORN = 0b110 - BGEU = AND = CSRRCI = REMU = REMUW = ANDN = MAXU = 0b111 - + JALR = BEQ = B = ADD = SUB = FENCE = PRIV = MUL = MULW = OPIVV = 0b000 + BNE = H = SLL = FENCEI = CSRRW = MULH = BCLR = BINV = BSET = CLZ = CPOP = CTZ = ROL = SEXTB = SEXTH = CLMUL = OPFVV = 0b001 + W = SLT = CSRRS = MULHSU = SH1ADD = CLMULR = OPMVV = 0b010 + SLTU = CSRRC = MULHU = CLMULH = OPIVI = 0b011 + BLT = BU = XOR = DIV = DIVW = SH2ADD = MIN = XNOR = ZEXTH = OPIVX = 0b100 + BGE = HU = SR = CSRRWI = DIVU = DIVUW = BEXT = ORCB = REV8 = ROR = MINU = OPFVF = 0b101 + BLTU = OR = CSRRSI = REM = REMW = SH3ADD = MAX = ORN = OPMVX = 0b110 + BGEU = AND = CSRRCI = REMU = REMUW = ANDN = MAXU = OPCFG = 0b111 + +class Funct6(IntEnum, shape=6): + VADD = 0b000000 + VSUB = 0b000010 + VRSUB = 0b000011 + VMINU = 0b000100 + VMIN = 0b000101 + VMAXU = 0b000110 + VMAX = 0b000111 + VAND = 0b001001 + VOR = 0b001010 + VXOR = 0b001011 + VRGATHER = 0b001100 + VSLIDEUP = VRGATHEREI16 = 0b001110 + VSLIDEDOWN=0b001111 + VADC = 0b010000 + VMADC = 0b010001 + VSBC = 0b010010 + VMSBC = 0b010011 + VMERGE = VMV = 0b010111 + VMSEQ = 0b011000 + VMSNE = 0b011001 + VMSLTU = 0b011010 + VMSLT = 0b011011 + VMSLEU = 0b011100 + VMSLE = 0b011101 + VMSGTU = 0b011110 + VMSGT = 0b011111 + VSADDU = 0b100000 + VSADD = 0b100001 + VSSUBU = 0b100010 + VSSUB = 0b100011 + VSLL = 0b100101 + VSMUL = VMV1R = VMV2R = VMV4R = VMV8R = 0b100111 + VSRL = 0b101000 + VSRA = 0b101001 + VSSRL = 0b101010 + VSSRA = 0b101011 + VNSRL = 0b101100 + VNSRA = 0b101101 + VNCLIPU = 0b101110 + VNCLIP = 0b101111 + VWREDSUMU= 0b110000 + VWREDSUM = 0b110001 class Funct7(IntEnum, shape=7): SL = SLT = ADD = XOR = OR = AND = 0b0000000 @@ -96,6 +145,11 @@ class FenceFm(IntEnum, shape=4): NONE = 0b0000 TSO = 0b1000 +@unique +class RegisterType(IntEnum, shape=1): + X = 0b0 + V = 0b1 + @unique class Extension(enum.IntFlag): diff --git a/coreblocks/params/layouts.py b/coreblocks/params/layouts.py index 6212d28fb..69c0e3be8 100644 --- a/coreblocks/params/layouts.py +++ b/coreblocks/params/layouts.py @@ -1,4 +1,4 @@ -from coreblocks.params import GenParams, OpType, Funct7, Funct3, Opcode +from coreblocks.params import GenParams, OpType, Funct7, Funct3, Opcode, RegisterType from coreblocks.utils.utils import layout_subset __all__ = [ @@ -29,8 +29,11 @@ def __init__(self, gen_params: GenParams): self.regs_l = [ ("rl_s1", gen_params.isa.reg_cnt_log), + ("rl_s1_rf", RegisterType), ("rl_s2", gen_params.isa.reg_cnt_log), + ("rl_s2_rf", RegisterType), ("rl_dst", gen_params.isa.reg_cnt_log), + ("rl_dst_rf", RegisterType), ] self.regs_p = [ diff --git a/coreblocks/params/optypes.py b/coreblocks/params/optypes.py index 9d74049b7..aa3fd1ba3 100644 --- a/coreblocks/params/optypes.py +++ b/coreblocks/params/optypes.py @@ -42,6 +42,19 @@ class OpType(IntEnum): CLMUL = auto() SRET = auto() SFENCEVMA = auto() + V_ARITHMETIC = auto() + V_ARITHMETIC_IMM = auto() + V_ARITHMETIC_SCALAR = auto() + # TODO after V implementation check if there is a need for separate optype for narrowing + V_ARITHMETIC_NARROWING = auto() + V_ARITHMETIC_NARROWING_IMM = auto() + V_ARITHMETIC_NARROWING_SCALAR = auto() + V_PERMUTATION = auto() + V_PERMUTATION_IMM = auto() + V_PERMUTATION_SCALAR = auto() + V_CONTROL = auto() + V_REDUCTION = auto() + # @@ -103,6 +116,19 @@ class OpType(IntEnum): OpType.SRET, OpType.SFENCEVMA, ], + Extension.V: [ + OpType.V_ARITHMETIC, + OpType.V_ARITHMETIC_IMM, + OpType.V_ARITHMETIC_SCALAR, + OpType.V_ARITHMETIC_NARROWING, + OpType.V_ARITHMETIC_NARROWING_IMM, + OpType.V_ARITHMETIC_NARROWING_SCALAR, + OpType.V_PERMUTATION, + OpType.V_PERMUTATION_IMM, + OpType.V_PERMUTATION_SCALAR, + OpType.V_CONTROL, + OpType.V_REDUCTION, + ], } diff --git a/scripts/synthesize.py b/scripts/synthesize.py index fb3cdf4c3..79b5834fe 100755 --- a/scripts/synthesize.py +++ b/scripts/synthesize.py @@ -17,7 +17,7 @@ from coreblocks.core import Core from coreblocks.transactions import TransactionModule from coreblocks.peripherals.wishbone import WishboneArbiter, WishboneBus -from coreblocks.params.configurations import basic_core_config +from coreblocks.params.configurations import basic_core_config, vector_core_config from constants.ecp5_platforms import make_ecp5_platform @@ -51,7 +51,7 @@ def elaborate(self, platform: Platform): def synthesize(platform: str): - gen_params = GenParams(basic_core_config) + gen_params = GenParams(vector_core_config) if platform == "ecp5": make_ecp5_platform(gen_params.wb_params)().build(TestElaboratable(gen_params)) diff --git a/stubs/amaranth/lib/enum.pyi b/stubs/amaranth/lib/enum.pyi index 2cd19fdbd..4afb3fd75 100644 --- a/stubs/amaranth/lib/enum.pyi +++ b/stubs/amaranth/lib/enum.pyi @@ -3,6 +3,7 @@ This type stub file was generated by pyright. """ import enum as py_enum +from typing import overload, TypeVar from typing_extensions import Self from amaranth import * from ..hdl.ast import ShapeCastable @@ -12,7 +13,7 @@ __all__ = ['EnumMeta', 'Enum', 'IntEnum', 'Flag', 'IntFlag', 'auto', 'unique'] auto = py_enum.auto unique = py_enum.unique - +T = TypeVar('T') class EnumMeta(ShapeCastable, py_enum.EnumMeta): """Subclass of the standard :class:`enum.EnumMeta` that implements the :class:`ShapeCastable` @@ -47,8 +48,15 @@ class EnumMeta(ShapeCastable, py_enum.EnumMeta): If the enumeration has neither an explicitly provided shape nor any members. """ ... + + @overload + def __call__(cls, value : Value) -> Value: + ... + @overload + def __call__(cls : type[T], value : int) -> T: + ... - def __call__(cls, value) -> Value: + def __call__(cls, value) -> Value | Self: ... def const(cls, init) -> Const: diff --git a/test/asm/v_instr.asm b/test/asm/v_instr.asm new file mode 100644 index 000000000..a22c73068 --- /dev/null +++ b/test/asm/v_instr.asm @@ -0,0 +1,122 @@ +# INTEGER +# 0b00xxxx +vadd.vv v1, v2, v3 +vadd.vv v1, v2, v3, v0.t +vadd.vi v0, v4, 11 +vadd.vx v31, v8, x7 +vadd.vx v31, v8, x7, v0.t +vsub.vv v4, v8, v3 +vsub.vx v2, v3, x1 +vrsub.vx v1, v2, x3 +vrsub.vi v1, v2, 7 +vminu.vv v1, v2, v3 +vminu.vx v1, v2, x3 +vmin.vv v1, v2, v3 +vmin.vx v1, v2, x3 +vmaxu.vv v1, v2, v3 +vmaxu.vx v1, v2, x3 +vmax.vv v1, v2, v3 +vmax.vx v1, v2, x3 +vand.vv v1, v2, v3 +vand.vx v1, v2, x3 +vand.vi v1, v2, 15 +vor.vv v1, v2, v3 +vor.vx v1, v2, x3 +vor.vi v1, v2, -16 +vxor.vv v1, v2, v3 +vxor.vx v1, v2, x3 +vxor.vi v1, v2, 0 +vrgather.vv v1, v2, v3 +vrgather.vx v1, v2, x3 +vrgather.vi v1, v2, 4 +vslideup.vx v1, v2, x3 +vslideup.vi v1, v2, 2 +vrgatherei16.vv v1, v2, v3 +vslidedown.vx v1, v2, x3 +vslidedown.vi v1, v2, 2 + +# 0b01xxxx +vadc.vvm v1, v2, v3, v0 +vadc.vxm v1, v2, x3, v0 +vadc.vim v1, v2, 3, v0 +vmadc.vvm v1, v2, v3, v0 +vmadc.vxm v1, v2, x3, v0 +vmadc.vim v1, v2, 3, v0 +vsbc.vvm v1, v2, v3, v0 +vsbc.vxm v1, v2, x3, v0 +vmsbc.vvm v1, v2, v3, v0 +vmsbc.vxm v1, v2, x3, v0 +vmerge.vvm v1, v2, v3, v0 +vmerge.vxm v1, v2, x3, v0 +vmerge.vim v1, v2, 3, v0 +vmv.v.v v1, v3 +vmv.v.x v1, x3 +vmv.v.i v1, 3 +vmseq.vv v1, v2, v3 +vmseq.vx v1, v2, x3 +vmseq.vi v1, v2, 3 +vmsne.vv v1, v2, v3 +vmsne.vx v1, v2, x3 +vmsne.vi v1, v2, 3 +vmsltu.vv v1, v2, v3 +vmsltu.vx v1, v2, x3 +vmslt.vv v1, v2, v3 +vmslt.vx v1, v2, x3 +vmsleu.vv v1, v2, v3 +vmsleu.vx v1, v2, x3 +vmsleu.vi v1, v2, 3 +vmsle.vv v1, v2, v3 +vmsle.vx v1, v2, x3 +vmsle.vi v1, v2, 3 +vmsgtu.vx v1, v2, x3 +vmsgtu.vi v1, v2, 3 +vmsgt.vx v1, v2, x3 +vmsgt.vi v1, v2, 3 + +# 0b10xxxx +vsaddu.vv v1, v2, v3 +vsaddu.vx v1, v2, x3 +vsaddu.vi v1, v2, 3 +vsadd.vv v1, v2, v3 +vsadd.vx v1, v2, x3 +vsadd.vi v1, v2, 3 +vssubu.vv v1, v2, v3 +vssubu.vx v1, v2, x3 +vssub.vv v1, v2, v3 +vssub.vx v1, v2, x3 +vsll.vv v1, v2, v3 +vsll.vx v1, v2, x3 +vsll.vi v1, v2, 3 +vsmul.vv v1, v2, v3 +vsmul.vx v1, v2, x3 +vmv1r.v v0, v8 +vmv2r.v v0, v8 +vmv4r.v v0, v8 +vmv8r.v v0, v8 +vsrl.vv v1, v2, v3 +vsrl.vx v1, v2, x3 +vsrl.vi v1, v2, 3 +vsra.vv v1, v2, v3 +vsra.vx v1, v2, x3 +vsra.vi v1, v2, 3 +vnsrl.wv v1, v2, v3 +vnsrl.wx v1, v2, x3 +vnsrl.wi v1, v2, 3 +vnsra.wv v1, v2, v3 +vnsra.wx v1, v2, x3 +vnsra.wi v1, v2, 3 +vnclipu.wv v1, v2, v3 +vnclipu.wx v1, v2, x3 +vnclipu.wi v1, v2, 3 +vnclip.wv v1, v2, v3 +vnclip.wx v1, v2, x3 +vnclip.wi v1, v2, 3 + +#0b11xxxx +vwredsumu.vs v1, v2, v3 +vwredsum.vs v1, v2, v3 + +# CONTROL +vsetvl x0, x1, x2 +vsetvli x0, x0, e32,m8,ta,ma +vsetivli x1, 8, e32,m8,ta,ma diff --git a/test/frontend/test_decoder.py b/test/frontend/test_decoder.py index 1456ab3d1..c29982eb1 100644 --- a/test/frontend/test_decoder.py +++ b/test/frontend/test_decoder.py @@ -17,8 +17,11 @@ def __init__( funct7=None, funct12=None, rd=None, + rd_rf = RegisterType.X, rs1=None, + rs1_rf = RegisterType.X, rs2=None, + rs2_rf = RegisterType.X, imm=None, succ=None, pred=None, @@ -33,8 +36,11 @@ def __init__( self.funct7 = funct7 self.funct12 = funct12 self.rd = rd + self.rd_rf = rd_rf self.rs1 = rs1 + self.rs1_rf = rs1_rf self.rs2 = rs2 + self.rs2_rf = rs2_rf self.imm = imm self.succ = succ self.pred = pred @@ -167,11 +173,128 @@ def __init__( op=OpType.UNARY_BIT_MANIPULATION_1, ), ] + DECODER_TESTS_V_INTEGERS = [ + InstrTest(0x022180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VADD * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vadd.vv v1, v2, v3 + InstrTest(0x002180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VADD * 2, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vadd.vv v1, v2, v3, v0.t + InstrTest(0x0245b057, Opcode.OP_V, Funct3.OPIVI, Funct6.VADD * 2 + 1, rd_rf=RegisterType.V, rd= 0, rs2_rf=RegisterType.V, rs2= 4, imm=11, op=OpType.V_ARITHMETIC_IMM), #vadd.vi v0, v4, 11 + InstrTest(0x0283cfd7, Opcode.OP_V, Funct3.OPIVX, Funct6.VADD * 2 + 1, rd_rf=RegisterType.V, rd= 31, rs2_rf=RegisterType.V, rs2= 8, rs1_rf=RegisterType.X, rs1=7, op=OpType.V_ARITHMETIC_SCALAR), #vadd.vx v31, v8, x7 + InstrTest(0x0083cfd7, Opcode.OP_V, Funct3.OPIVX, Funct6.VADD * 2, rd_rf=RegisterType.V, rd= 31, rs2_rf=RegisterType.V, rs2= 8, rs1_rf=RegisterType.X, rs1=7, op=OpType.V_ARITHMETIC_SCALAR), #vadd.vx v31, v8, x7, v0.t + InstrTest(0x0a818257, Opcode.OP_V, Funct3.OPIVV, Funct6.VSUB * 2 + 1, rd_rf=RegisterType.V, rd= 4, rs2_rf=RegisterType.V, rs2= 8, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vsub.vv v4, v8, v3 + InstrTest(0x0a30c157, Opcode.OP_V, Funct3.OPIVX, Funct6.VSUB * 2 + 1, rd_rf=RegisterType.V, rd= 2, rs2_rf=RegisterType.V, rs2= 3, rs1_rf=RegisterType.X, rs1=1, op=OpType.V_ARITHMETIC_SCALAR), #vsub.vx v2, v3, x1 + InstrTest(0x0e21c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VRSUB * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_ARITHMETIC_SCALAR), #vrsub.vx v1, v2, x3 + InstrTest(0x0e23b0d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VRSUB * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, imm=7, op=OpType.V_ARITHMETIC_IMM), #vrsub.vi v1, v2, 7 + InstrTest(0x122180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VMINU * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vminu.vv v1, v2, v3 + InstrTest(0x1221c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VMINU * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_ARITHMETIC_SCALAR), #vminu.vx v1, v2, x3 + InstrTest(0x162180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VMIN * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vmin.vv v1, v2, v3 + InstrTest(0x1621c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VMIN * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_ARITHMETIC_SCALAR), #vmin.vx v1, v2, x3 + InstrTest(0x1a2180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VMAXU * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vmaxu.vv v1, v2, v3 + InstrTest(0x1a21c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VMAXU * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_ARITHMETIC_SCALAR), #vmaxu.vx v1, v2, x3 + InstrTest(0x1e2180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VMAX * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vmax.vv v1, v2, v3 + InstrTest(0x1e21c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VMAX * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_ARITHMETIC_SCALAR), #vmax.vx v1, v2, x3 + InstrTest(0x262180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VAND * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vand.vv v1, v2, v3 + InstrTest(0x2621c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VAND * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_ARITHMETIC_SCALAR), #vand.vx v1, v2, x3 + InstrTest(0x2627b0d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VAND * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, imm=15, op=OpType.V_ARITHMETIC_IMM), #vand.vi v1, v2, 15 + InstrTest(0x2a2180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VOR * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vor.vv v1, v2, v3 + InstrTest(0x2a21c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VOR * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_ARITHMETIC_SCALAR), #vor.vx v1, v2, x3 + InstrTest(0x2a2830d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VOR * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, imm=-16, op=OpType.V_ARITHMETIC_IMM), #vor.vi v1, v2, -16 + InstrTest(0x2e2180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VXOR * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vxor.vv v1, v2, v3 + InstrTest(0x2e21c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VXOR * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_ARITHMETIC_SCALAR), #vxor.vx v1, v2, x3 + InstrTest(0x2e2030d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VXOR * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, imm=0, op=OpType.V_ARITHMETIC_IMM), #vxor.vi v1, v2, 0 + InstrTest(0x322180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VRGATHER * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_PERMUTATION), #vrgather.vv v1, v2, v3 + InstrTest(0x3221c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VRGATHER * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_PERMUTATION_SCALAR), #vrgather.vx v1, v2, x3 + InstrTest(0x322230d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VRGATHER * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, imm=4, op=OpType.V_PERMUTATION_IMM), #vrgather.vi v1, v2, 4 + InstrTest(0x3a21c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VSLIDEUP * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_PERMUTATION_SCALAR), #vslideup.vx v1, v2, x3 + InstrTest(0x3a2130d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VSLIDEUP * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, imm=2, op=OpType.V_PERMUTATION_IMM), #vslideup.vi v1, v2, 2 + InstrTest(0x3a2180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VRGATHEREI16 * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_PERMUTATION), #vrgatherei16.vv v1, v2, v3 + InstrTest(0x3e21c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VSLIDEDOWN * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_PERMUTATION_SCALAR), #vslidedown.vx v1, v2, x3 + InstrTest(0x3e2130d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VSLIDEDOWN * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, imm=2, op=OpType.V_PERMUTATION_IMM), #vslidedown.vi v1, v2, 2 + InstrTest(0x402180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VADC * 2, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vadc.vvm v1, v2, v3, v0 + InstrTest(0x4021c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VADC * 2, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_ARITHMETIC_SCALAR), #vadc.vxm v1, v2, x3, v0 + InstrTest(0x4021b0d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VADC * 2, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, imm=3, op=OpType.V_ARITHMETIC_IMM), #vadc.vim v1, v2, 3, v0 + InstrTest(0x442180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VMADC * 2, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vmadc.vvm v1, v2, v3, v0 + InstrTest(0x4421c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VMADC * 2, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_ARITHMETIC_SCALAR), #vmadc.vxm v1, v2, x3, v0 + InstrTest(0x4421b0d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VMADC * 2, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, imm=3, op=OpType.V_ARITHMETIC_IMM), #vmadc.vim v1, v2, 3, v0 + InstrTest(0x482180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VSBC * 2, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vsbc.vvm v1, v2, v3, v0 + InstrTest(0x4821c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VSBC * 2, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_ARITHMETIC_SCALAR), #vsbc.vxm v1, v2, x3, v0 + InstrTest(0x4c2180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VMSBC * 2, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vmsbc.vvm v1, v2, v3, v0 + InstrTest(0x4c21c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VMSBC * 2, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_ARITHMETIC_SCALAR), #vmsbc.vxm v1, v2, x3, v0 + InstrTest(0x5c2180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VMERGE * 2, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_PERMUTATION), #vmerge.vvm v1, v2, v3, v0 + InstrTest(0x5c21c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VMERGE * 2, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_PERMUTATION_SCALAR), #vmerge.vxm v1, v2, x3, v0 + InstrTest(0x5c21b0d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VMERGE * 2, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, imm=3, op=OpType.V_PERMUTATION_IMM), #vmerge.vim v1, v2, 3, v0 + InstrTest(0x5e0180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VMV * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2=0, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_PERMUTATION), #vmv.v.v v1, v3 + InstrTest(0x5e01c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VMV * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2=0, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_PERMUTATION_SCALAR), #vmv.v.x v1, x3 + InstrTest(0x5e01b0d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VMV * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2=0, imm=3, op=OpType.V_PERMUTATION_IMM), #vmv.v.i v1, 3 + InstrTest(0x622180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VMSEQ * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vmseq.vv v1, v2, v3 + InstrTest(0x6221c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VMSEQ * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_ARITHMETIC_SCALAR), #vmseq.vx v1, v2, x3 + InstrTest(0x6221b0d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VMSEQ * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, imm=3, op=OpType.V_ARITHMETIC_IMM), #vmseq.vi v1, v2, 3 + InstrTest(0x662180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VMSNE * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vmsne.vv v1, v2, v3 + InstrTest(0x6621c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VMSNE * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_ARITHMETIC_SCALAR), #vmsne.vx v1, v2, x3 + InstrTest(0x6621b0d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VMSNE * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, imm=3, op=OpType.V_ARITHMETIC_IMM), #vmsne.vi v1, v2, 3 + InstrTest(0x6a2180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VMSLTU * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vmsltu.vv v1, v2, v3 + InstrTest(0x6a21c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VMSLTU * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_ARITHMETIC_SCALAR), #vmsltu.vx v1, v2, x3 + InstrTest(0x6e2180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VMSLT * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vmslt.vv v1, v2, v3 + InstrTest(0x6e21c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VMSLT * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_ARITHMETIC_SCALAR), #vmslt.vx v1, v2, x3 + InstrTest(0x722180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VMSLEU * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vmsleu.vv v1, v2, v3 + InstrTest(0x7221c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VMSLEU * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_ARITHMETIC_SCALAR), #vmsleu.vx v1, v2, x3 + InstrTest(0x7221b0d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VMSLEU * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, imm=3, op=OpType.V_ARITHMETIC_IMM), #vmsleu.vi v1, v2, 3 + InstrTest(0x762180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VMSLE * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vmsle.vv v1, v2, v3 + InstrTest(0x7621c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VMSLE * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_ARITHMETIC_SCALAR), #vmsle.vx v1, v2, x3 + InstrTest(0x7621b0d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VMSLE * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, imm= 3, op=OpType.V_ARITHMETIC_IMM), #vmsle.vi v1, v2, 3 + InstrTest(0x7a21c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VMSGTU * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_ARITHMETIC_SCALAR), #vmsgtu.vx v1, v2, x3 + InstrTest(0x7a21b0d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VMSGTU * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, imm= 3, op=OpType.V_ARITHMETIC_IMM), #vmsgtu.vi v1, v2, 3 + InstrTest(0x7e21c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VMSGT * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_ARITHMETIC_SCALAR), #vmsgt.vx v1, v2, x3 + InstrTest(0x7e21b0d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VMSGT * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, imm= 3, op=OpType.V_ARITHMETIC_IMM), #vmsgt.vi v1, v2, 3 + InstrTest(0x822180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VSADDU * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vsaddu.vv v1, v2, v3 + InstrTest(0x8221c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VSADDU * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_ARITHMETIC_SCALAR), #vsaddu.vx v1, v2, x3 + InstrTest(0x8221b0d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VSADDU * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, imm= 3, op=OpType.V_ARITHMETIC_IMM), #vsaddu.vi v1, v2, 3 + InstrTest(0x862180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VSADD * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vsadd.vv v1, v2, v3 + InstrTest(0x8621c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VSADD * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_ARITHMETIC_SCALAR), #vsadd.vx v1, v2, x3 + InstrTest(0x8621b0d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VSADD * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, imm= 3, op=OpType.V_ARITHMETIC_IMM), #vsadd.vi v1, v2, 3 + InstrTest(0x8a2180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VSSUBU * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vssubu.vv v1, v2, v3 + InstrTest(0x8a21c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VSSUBU * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1= 3, op=OpType.V_ARITHMETIC_SCALAR), #vssubu.vx v1, v2, x3 + InstrTest(0x8e2180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VSSUB * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vssub.vv v1, v2, v3 + InstrTest(0x8e21c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VSSUB * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1=3, op=OpType.V_ARITHMETIC_SCALAR), #vssub.vx v1, v2, x3 + InstrTest(0x962180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VSLL * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vsll.vv v1, v2, v3 + InstrTest(0x9621c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VSLL * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1= 3, op=OpType.V_ARITHMETIC_SCALAR), #vsll.vx v1, v2, x3 + InstrTest(0x9621b0d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VSLL * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, imm= 3, op=OpType.V_ARITHMETIC_IMM), #vsll.vi v1, v2, 3 + InstrTest(0x9e2180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VSMUL * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC), #vsmul.vv v1, v2, v3 + InstrTest(0x9e21c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VSMUL * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1= 3, op=OpType.V_ARITHMETIC_SCALAR), #vsmul.vx v1, v2, x3 + InstrTest(0x9e803057, Opcode.OP_V, Funct3.OPIVI, Funct6.VMV1R * 2 + 1, rd_rf=RegisterType.V, rd= 0, rs2_rf=RegisterType.V, rs2=8, imm=0, op=OpType.V_PERMUTATION_IMM), #vmv1r.v v0, v8 + InstrTest(0x9e80b057, Opcode.OP_V, Funct3.OPIVI, Funct6.VMV2R * 2 + 1, rd_rf=RegisterType.V, rd= 0, rs2_rf=RegisterType.V, rs2=8, imm=1, op=OpType.V_PERMUTATION_IMM), #vmv2r.v v0, v8 + InstrTest(0x9e81b057, Opcode.OP_V, Funct3.OPIVI, Funct6.VMV4R * 2 + 1, rd_rf=RegisterType.V, rd= 0, rs2_rf=RegisterType.V, rs2=8, imm=3, op=OpType.V_PERMUTATION_IMM), #vmv4r.v v0, v8 + InstrTest(0x9e83b057, Opcode.OP_V, Funct3.OPIVI, Funct6.VMV8R * 2 + 1, rd_rf=RegisterType.V, rd= 0, rs2_rf=RegisterType.V, rs2=8, imm=7, op=OpType.V_PERMUTATION_IMM), #vmv8r.v v0, v8 + InstrTest(0xa22180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VSRL * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1= 3, op=OpType.V_ARITHMETIC), #vsrl.vv v1, v2, v3 + InstrTest(0xa221c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VSRL * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1= 3, op=OpType.V_ARITHMETIC_SCALAR), #vsrl.vx v1, v2, x3 + InstrTest(0xa221b0d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VSRL * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, imm= 3, op=OpType.V_ARITHMETIC_IMM), #vsrl.vi v1, v2, 3 + InstrTest(0xa62180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VSRA * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1= 3, op=OpType.V_ARITHMETIC), #vsra.vv v1, v2, v3 + InstrTest(0xa621c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VSRA * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1= 3, op=OpType.V_ARITHMETIC_SCALAR), #vsra.vx v1, v2, x3 + InstrTest(0xa621b0d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VSRA * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, imm= 3, op=OpType.V_ARITHMETIC_IMM), #vsra.vi v1, v2, 3 + InstrTest(0xb22180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VNSRL * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_ARITHMETIC_NARROWING), #vnsrl.wv v1, v2, v3 + InstrTest(0xb221c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VNSRL * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1= 3, op=OpType.V_ARITHMETIC_NARROWING_SCALAR), #vnsrl.wx v1, v2, x3 + InstrTest(0xb221b0d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VNSRL * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, imm= 3, op=OpType.V_ARITHMETIC_NARROWING_IMM), #vnsrl.wi v1, v2, 3 + InstrTest(0xb62180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VNSRA * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1= 3, op=OpType.V_ARITHMETIC_NARROWING), #vnsra.wv v1, v2, v3 + InstrTest(0xb621c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VNSRA * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1= 3, op=OpType.V_ARITHMETIC_NARROWING_SCALAR), #vnsra.wx v1, v2, x3 + InstrTest(0xb621b0d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VNSRA * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, imm= 3, op=OpType.V_ARITHMETIC_NARROWING_IMM), #vnsra.wi v1, v2, 3 + InstrTest(0xba2180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VNCLIPU * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1= 3, op=OpType.V_ARITHMETIC_NARROWING), #vnclipu.wv v1, v2, v3 + InstrTest(0xba21c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VNCLIPU * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1= 3, op=OpType.V_ARITHMETIC_NARROWING_SCALAR), #vnclipu.wx v1, v2, x3 + InstrTest(0xba21b0d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VNCLIPU * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, imm= 3, op=OpType.V_ARITHMETIC_NARROWING_IMM), #vnclipu.wi v1, v2, 3 + InstrTest(0xbe2180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VNCLIP * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1= 3, op=OpType.V_ARITHMETIC_NARROWING), #vnclip.wv v1, v2, v3 + InstrTest(0xbe21c0d7, Opcode.OP_V, Funct3.OPIVX, Funct6.VNCLIP * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.X, rs1= 3, op=OpType.V_ARITHMETIC_NARROWING_SCALAR), #vnclip.wx v1, v2, x3 + InstrTest(0xbe21b0d7, Opcode.OP_V, Funct3.OPIVI, Funct6.VNCLIP * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, imm= 3, op=OpType.V_ARITHMETIC_NARROWING_IMM), #vnclip.wi v1, v2, 3 + InstrTest(0xc22180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VWREDSUMU * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1=3, op=OpType.V_REDUCTION), #vwredsumu.vs v1, v2, v3 + InstrTest(0xc62180d7, Opcode.OP_V, Funct3.OPIVV, Funct6.VWREDSUM * 2 + 1, rd_rf=RegisterType.V, rd= 1, rs2_rf=RegisterType.V, rs2= 2, rs1_rf=RegisterType.V, rs1= 3, op=OpType.V_REDUCTION),#vwredsum.vs v1, v2, v3 + ] + DECODER_TESTS_V_CONTROL = [ + InstrTest(0x8020f057, Opcode.OP_V, Funct3.OPCFG, rd=0, rs1=1, rs2=2, op=OpType.V_CONTROL), #vsetvl x0, x1, x2 + InstrTest(0x0d307057, Opcode.OP_V, Funct3.OPCFG, rd=0, rs1=0, csr=0b11010011, op=OpType.V_CONTROL), #vsetvli x0, x0, e32,m8,ta,ma + InstrTest(0xcd3470d7, Opcode.OP_V, Funct3.OPCFG, rd=1, imm=8, csr=0b110011010011,op=OpType.V_CONTROL), #vsetivli x1, 8, e32,m8,ta,ma + ] + def setUp(self): gen = GenParams( test_core_config.replace( - _implied_extensions=Extension.G | Extension.XINTMACHINEMODE | Extension.XINTSUPERVISOR | Extension.ZBB + _implied_extensions=Extension.G | Extension.XINTMACHINEMODE | Extension.XINTSUPERVISOR | Extension.ZBB | Extension.V ) ) self.decoder = InstrDecoder(gen) @@ -181,6 +304,8 @@ def do_test(self, test): def process(): yield self.decoder.instr.eq(test.encoding) yield Settle() + # For pprint in gtkwave + yield Delay(1e-7) self.assertEqual((yield self.decoder.illegal), test.illegal) if test.illegal: @@ -202,14 +327,17 @@ def process(): if test.rd is not None: self.assertEqual((yield self.decoder.rd), test.rd) + self.assertEqual((yield self.decoder.rd_rf), test.rd_rf) self.assertEqual((yield self.decoder.rd_v), test.rd is not None) if test.rs1 is not None: self.assertEqual((yield self.decoder.rs1), test.rs1) + self.assertEqual((yield self.decoder.rs1_rf), test.rs1_rf) self.assertEqual((yield self.decoder.rs1_v), test.rs1 is not None) if test.rs2 is not None: self.assertEqual((yield self.decoder.rs2), test.rs2) + self.assertEqual((yield self.decoder.rs2_rf), test.rs2_rf) self.assertEqual((yield self.decoder.rs2_v), test.rs2 is not None) if test.imm is not None: @@ -263,3 +391,11 @@ def test_xintsupervisor(self): def test_zbb(self): for test in self.DECODER_TESTS_ZBB: self.do_test(test) + + def test_v_integer(self): + for test in self.DECODER_TESTS_V_INTEGERS: + self.do_test(test) + + def test_v_control(self): + for test in self.DECODER_TESTS_V_CONTROL: + self.do_test(test)