@@ -411,7 +411,7 @@ static Operand::Register RegOp(xed_reg_enum_t reg) {
411411static Operand::Register SegBaseRegOp (xed_reg_enum_t reg, unsigned addr_size) {
412412 auto op = RegOp (reg);
413413 if (XED_REG_INVALID != reg) {
414- op.name += " _BASE " ;
414+ op.name += " BASE " ;
415415 op.size = addr_size;
416416 }
417417 return op;
@@ -1362,17 +1362,19 @@ void X86Arch::PopulateBasicBlockFunction(llvm::Module *module,
13621362 REG (DS, seg.ds .flat , u16 );
13631363 REG (CS, seg.cs .flat , u16 );
13641364
1365- ir.CreateStore (zero_addr_val, ir.CreateAlloca (addr, nullptr , " SS_BASE" ));
1366- ir.CreateStore (zero_addr_val, ir.CreateAlloca (addr, nullptr , " ES_BASE" ));
1367- ir.CreateStore (zero_addr_val, ir.CreateAlloca (addr, nullptr , " DS_BASE" ));
1368- ir.CreateStore (zero_addr_val, ir.CreateAlloca (addr, nullptr , " CS_BASE" ));
1365+ ir.CreateStore (zero_addr_val, ir.CreateAlloca (addr, nullptr , " ESBASE" ));
1366+ ir.CreateStore (zero_addr_val, ir.CreateAlloca (addr, nullptr , " DSBASE" ));
1367+ ir.CreateStore (zero_addr_val, ir.CreateAlloca (addr, nullptr , " CSBASE" ));
13691368
13701369 if (64 == address_size) {
1371- REG (GS_BASE, addr.gs_base .qword , addr);
1372- REG (FS_BASE, addr.fs_base .qword , addr);
1370+ ir.CreateStore (zero_addr_val, ir.CreateAlloca (addr, nullptr , " SSBASE" ));
1371+ REG (GSBASE, addr.gs_base .qword , addr);
1372+ REG (FSBASE, addr.fs_base .qword , addr);
1373+
13731374 } else {
1374- REG (GS_BASE, addr.gs_base .dword , addr);
1375- REG (FS_BASE, addr.fs_base .dword , addr);
1375+ REG (SSBASE, addr.ss_base .dword , addr);
1376+ REG (GSBASE, addr.gs_base .dword , addr);
1377+ REG (FSBASE, addr.fs_base .dword , addr);
13761378 }
13771379
13781380 if (has_avx) {
0 commit comments