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AArch64.cpp
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//===--- AArch64.cpp - Implement AArch64 target feature support -----------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file implements AArch64 TargetInfo objects.
//
//===----------------------------------------------------------------------===//
#include "AArch64.h"
#include "clang/Basic/LangOptions.h"
#include "clang/Basic/TargetBuiltins.h"
#include "clang/Basic/TargetInfo.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/TargetParser/AArch64TargetParser.h"
#include "llvm/TargetParser/ARMTargetParserCommon.h"
#include <optional>
using namespace clang;
using namespace clang::targets;
static constexpr Builtin::Info BuiltinInfo[] = {
#define BUILTIN(ID, TYPE, ATTRS) \
{#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
{#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
#include "clang/Basic/BuiltinsNEON.def"
#define BUILTIN(ID, TYPE, ATTRS) \
{#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
{#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
#include "clang/Basic/BuiltinsSVE.def"
#define BUILTIN(ID, TYPE, ATTRS) \
{#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
{#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
#include "clang/Basic/BuiltinsSME.def"
#define BUILTIN(ID, TYPE, ATTRS) \
{#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
#define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \
{#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, LANG},
#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
{#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
{#ID, TYPE, ATTRS, FEATURE, HeaderDesc::HEADER, LANGS},
#include "clang/Basic/BuiltinsAArch64.def"
};
void AArch64TargetInfo::setArchFeatures() {
if (*ArchInfo == llvm::AArch64::ARMV8R) {
HasDotProd = true;
HasDIT = true;
HasFlagM = true;
HasRCPC = true;
FPU |= NeonMode;
HasCCPP = true;
HasCRC = true;
HasLSE = true;
HasRDM = true;
} else if (ArchInfo->Version.getMajor() == 8) {
if (ArchInfo->Version.getMinor() >= 7u) {
HasWFxT = true;
}
if (ArchInfo->Version.getMinor() >= 6u) {
HasBFloat16 = true;
HasMatMul = true;
}
if (ArchInfo->Version.getMinor() >= 5u) {
HasAlternativeNZCV = true;
HasFRInt3264 = true;
HasSSBS = true;
HasSB = true;
HasPredRes = true;
HasBTI = true;
}
if (ArchInfo->Version.getMinor() >= 4u) {
HasDotProd = true;
HasDIT = true;
HasFlagM = true;
}
if (ArchInfo->Version.getMinor() >= 3u) {
HasRCPC = true;
FPU |= NeonMode;
}
if (ArchInfo->Version.getMinor() >= 2u) {
HasCCPP = true;
}
if (ArchInfo->Version.getMinor() >= 1u) {
HasCRC = true;
HasLSE = true;
HasRDM = true;
}
} else if (ArchInfo->Version.getMajor() == 9) {
if (ArchInfo->Version.getMinor() >= 2u) {
HasWFxT = true;
}
if (ArchInfo->Version.getMinor() >= 1u) {
HasBFloat16 = true;
HasMatMul = true;
}
FPU |= SveMode;
HasSVE2 = true;
HasFullFP16 = true;
HasAlternativeNZCV = true;
HasFRInt3264 = true;
HasSSBS = true;
HasSB = true;
HasPredRes = true;
HasBTI = true;
HasDotProd = true;
HasDIT = true;
HasFlagM = true;
HasRCPC = true;
FPU |= NeonMode;
HasCCPP = true;
HasCRC = true;
HasLSE = true;
HasRDM = true;
}
}
AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple,
const TargetOptions &Opts)
: TargetInfo(Triple), ABI("aapcs") {
if (getTriple().isOSOpenBSD()) {
Int64Type = SignedLongLong;
IntMaxType = SignedLongLong;
} else {
if (!getTriple().isOSDarwin() && !getTriple().isOSNetBSD())
WCharType = UnsignedInt;
Int64Type = SignedLong;
IntMaxType = SignedLong;
}
// All AArch64 implementations support ARMv8 FP, which makes half a legal type.
HasLegalHalfType = true;
HalfArgsAndReturns = true;
HasFloat16 = true;
HasStrictFP = true;
if (Triple.isArch64Bit())
LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
else
LongWidth = LongAlign = PointerWidth = PointerAlign = 32;
MaxVectorAlign = 128;
MaxAtomicInlineWidth = 128;
MaxAtomicPromoteWidth = 128;
LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
LongDoubleFormat = &llvm::APFloat::IEEEquad();
BFloat16Width = BFloat16Align = 16;
BFloat16Format = &llvm::APFloat::BFloat();
// Make __builtin_ms_va_list available.
HasBuiltinMSVaList = true;
// Make the SVE types available. Note that this deliberately doesn't
// depend on SveMode, since in principle it should be possible to turn
// SVE on and off within a translation unit. It should also be possible
// to compile the global declaration:
//
// __SVInt8_t *ptr;
//
// even without SVE.
HasAArch64SVETypes = true;
// {} in inline assembly are neon specifiers, not assembly variant
// specifiers.
NoAsmVariants = true;
// AAPCS gives rules for bitfields. 7.1.7 says: "The container type
// contributes to the alignment of the containing aggregate in the same way
// a plain (non bit-field) member of that type would, without exception for
// zero-sized or anonymous bit-fields."
assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
UseZeroLengthBitfieldAlignment = true;
// AArch64 targets default to using the ARM C++ ABI.
TheCXXABI.set(TargetCXXABI::GenericAArch64);
if (Triple.getOS() == llvm::Triple::Linux)
this->MCountName = "\01_mcount";
else if (Triple.getOS() == llvm::Triple::UnknownOS)
this->MCountName =
Opts.EABIVersion == llvm::EABI::GNU ? "\01_mcount" : "mcount";
}
StringRef AArch64TargetInfo::getABI() const { return ABI; }
bool AArch64TargetInfo::setABI(const std::string &Name) {
if (Name != "aapcs" && Name != "darwinpcs")
return false;
ABI = Name;
return true;
}
bool AArch64TargetInfo::validateBranchProtection(StringRef Spec, StringRef,
BranchProtectionInfo &BPI,
StringRef &Err) const {
llvm::ARM::ParsedBranchProtection PBP;
if (!llvm::ARM::parseBranchProtection(Spec, PBP, Err))
return false;
BPI.SignReturnAddr =
llvm::StringSwitch<LangOptions::SignReturnAddressScopeKind>(PBP.Scope)
.Case("non-leaf", LangOptions::SignReturnAddressScopeKind::NonLeaf)
.Case("all", LangOptions::SignReturnAddressScopeKind::All)
.Default(LangOptions::SignReturnAddressScopeKind::None);
if (PBP.Key == "a_key")
BPI.SignKey = LangOptions::SignReturnAddressKeyKind::AKey;
else
BPI.SignKey = LangOptions::SignReturnAddressKeyKind::BKey;
BPI.BranchTargetEnforcement = PBP.BranchTargetEnforcement;
BPI.BranchProtectionPAuthLR = PBP.BranchProtectionPAuthLR;
BPI.GuardedControlStack = PBP.GuardedControlStack;
return true;
}
bool AArch64TargetInfo::isValidCPUName(StringRef Name) const {
return Name == "generic" || llvm::AArch64::parseCpu(Name);
}
bool AArch64TargetInfo::setCPU(const std::string &Name) {
return isValidCPUName(Name);
}
void AArch64TargetInfo::fillValidCPUList(
SmallVectorImpl<StringRef> &Values) const {
llvm::AArch64::fillValidCPUArchList(Values);
}
void AArch64TargetInfo::getTargetDefinesARMV81A(const LangOptions &Opts,
MacroBuilder &Builder) const {
Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
}
void AArch64TargetInfo::getTargetDefinesARMV82A(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Also include the ARMv8.1 defines
getTargetDefinesARMV81A(Opts, Builder);
}
void AArch64TargetInfo::getTargetDefinesARMV83A(const LangOptions &Opts,
MacroBuilder &Builder) const {
Builder.defineMacro("__ARM_FEATURE_COMPLEX", "1");
Builder.defineMacro("__ARM_FEATURE_JCVT", "1");
// Also include the Armv8.2 defines
getTargetDefinesARMV82A(Opts, Builder);
}
void AArch64TargetInfo::getTargetDefinesARMV84A(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Also include the Armv8.3 defines
getTargetDefinesARMV83A(Opts, Builder);
}
void AArch64TargetInfo::getTargetDefinesARMV85A(const LangOptions &Opts,
MacroBuilder &Builder) const {
Builder.defineMacro("__ARM_FEATURE_FRINT", "1");
Builder.defineMacro("__ARM_FEATURE_BTI", "1");
// Also include the Armv8.4 defines
getTargetDefinesARMV84A(Opts, Builder);
}
void AArch64TargetInfo::getTargetDefinesARMV86A(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Also include the Armv8.5 defines
// FIXME: Armv8.6 makes the following extensions mandatory:
// - __ARM_FEATURE_BF16
// - __ARM_FEATURE_MATMUL_INT8
// Handle them here.
getTargetDefinesARMV85A(Opts, Builder);
}
void AArch64TargetInfo::getTargetDefinesARMV87A(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Also include the Armv8.6 defines
getTargetDefinesARMV86A(Opts, Builder);
}
void AArch64TargetInfo::getTargetDefinesARMV88A(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Also include the Armv8.7 defines
getTargetDefinesARMV87A(Opts, Builder);
}
void AArch64TargetInfo::getTargetDefinesARMV89A(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Also include the Armv8.8 defines
getTargetDefinesARMV88A(Opts, Builder);
}
void AArch64TargetInfo::getTargetDefinesARMV9A(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Armv9-A maps to Armv8.5-A
getTargetDefinesARMV85A(Opts, Builder);
}
void AArch64TargetInfo::getTargetDefinesARMV91A(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Armv9.1-A maps to Armv8.6-A
getTargetDefinesARMV86A(Opts, Builder);
}
void AArch64TargetInfo::getTargetDefinesARMV92A(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Armv9.2-A maps to Armv8.7-A
getTargetDefinesARMV87A(Opts, Builder);
}
void AArch64TargetInfo::getTargetDefinesARMV93A(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Armv9.3-A maps to Armv8.8-A
getTargetDefinesARMV88A(Opts, Builder);
}
void AArch64TargetInfo::getTargetDefinesARMV94A(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Armv9.4-A maps to Armv8.9-A
getTargetDefinesARMV89A(Opts, Builder);
}
void AArch64TargetInfo::getTargetDefinesARMV95A(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Armv9.5-A does not have a v8.* equivalent, but is a superset of v9.4-A.
getTargetDefinesARMV94A(Opts, Builder);
}
void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Target identification.
if (getTriple().isWindowsArm64EC()) {
// Define the same set of macros as would be defined on x86_64 to ensure that
// ARM64EC datatype layouts match those of x86_64 compiled code
Builder.defineMacro("__amd64__");
Builder.defineMacro("__amd64");
Builder.defineMacro("__x86_64");
Builder.defineMacro("__x86_64__");
Builder.defineMacro("__arm64ec__");
} else {
Builder.defineMacro("__aarch64__");
}
// Inline assembly supports AArch64 flag outputs.
Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
std::string CodeModel = getTargetOpts().CodeModel;
if (CodeModel == "default")
CodeModel = "small";
for (char &c : CodeModel)
c = toupper(c);
Builder.defineMacro("__AARCH64_CMODEL_" + CodeModel + "__");
// ACLE predefines. Many can only have one possible value on v8 AArch64.
Builder.defineMacro("__ARM_ACLE", "200");
Builder.defineMacro("__ARM_ARCH",
std::to_string(ArchInfo->Version.getMajor()));
Builder.defineMacro("__ARM_ARCH_PROFILE",
std::string("'") + (char)ArchInfo->Profile + "'");
Builder.defineMacro("__ARM_64BIT_STATE", "1");
Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
Builder.defineMacro("__ARM_FEATURE_FMA", "1");
Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE
Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
// These macros are set when Clang can parse declarations with these
// attributes.
Builder.defineMacro("__ARM_STATE_ZA", "1");
Builder.defineMacro("__ARM_STATE_ZT0", "1");
// 0xe implies support for half, single and double precision operations.
if (FPU & FPUMode)
Builder.defineMacro("__ARM_FP", "0xE");
// PCS specifies this for SysV variants, which is all we support. Other ABIs
// may choose __ARM_FP16_FORMAT_ALTERNATIVE.
Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
Builder.defineMacro("__ARM_FP16_ARGS", "1");
if (Opts.UnsafeFPMath)
Builder.defineMacro("__ARM_FP_FAST", "1");
Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
Twine(Opts.WCharSize ? Opts.WCharSize : 4));
Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? "1" : "4");
if (FPU & NeonMode) {
Builder.defineMacro("__ARM_NEON", "1");
// 64-bit NEON supports half, single and double precision operations.
Builder.defineMacro("__ARM_NEON_FP", "0xE");
}
if (FPU & SveMode)
Builder.defineMacro("__ARM_FEATURE_SVE", "1");
if ((FPU & NeonMode) && (FPU & SveMode))
Builder.defineMacro("__ARM_NEON_SVE_BRIDGE", "1");
if (HasSVE2)
Builder.defineMacro("__ARM_FEATURE_SVE2", "1");
if (HasSVE2 && HasSVE2AES)
Builder.defineMacro("__ARM_FEATURE_SVE2_AES", "1");
if (HasSVE2 && HasSVE2BitPerm)
Builder.defineMacro("__ARM_FEATURE_SVE2_BITPERM", "1");
if (HasSVE2 && HasSVE2SHA3)
Builder.defineMacro("__ARM_FEATURE_SVE2_SHA3", "1");
if (HasSVE2 && HasSVE2SM4)
Builder.defineMacro("__ARM_FEATURE_SVE2_SM4", "1");
if (HasSME) {
Builder.defineMacro("__ARM_FEATURE_SME");
Builder.defineMacro("__ARM_FEATURE_LOCALLY_STREAMING", "1");
}
if (HasSME2) {
Builder.defineMacro("__ARM_FEATURE_SME");
Builder.defineMacro("__ARM_FEATURE_SME2");
Builder.defineMacro("__ARM_FEATURE_LOCALLY_STREAMING", "1");
}
if (HasCRC)
Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
if (HasRCPC3)
Builder.defineMacro("__ARM_FEATURE_RCPC", "3");
else if (HasRCPC)
Builder.defineMacro("__ARM_FEATURE_RCPC", "1");
if (HasFMV)
Builder.defineMacro("__HAVE_FUNCTION_MULTI_VERSIONING", "1");
// The __ARM_FEATURE_CRYPTO is deprecated in favor of finer grained feature
// macros for AES, SHA2, SHA3 and SM4
if (HasAES && HasSHA2)
Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
if (HasAES)
Builder.defineMacro("__ARM_FEATURE_AES", "1");
if (HasSHA2)
Builder.defineMacro("__ARM_FEATURE_SHA2", "1");
if (HasSHA3) {
Builder.defineMacro("__ARM_FEATURE_SHA3", "1");
Builder.defineMacro("__ARM_FEATURE_SHA512", "1");
}
if (HasSM4) {
Builder.defineMacro("__ARM_FEATURE_SM3", "1");
Builder.defineMacro("__ARM_FEATURE_SM4", "1");
}
if (HasPAuth)
Builder.defineMacro("__ARM_FEATURE_PAUTH", "1");
if (HasUnaligned)
Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
if ((FPU & NeonMode) && HasFullFP16)
Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1");
if (HasFullFP16)
Builder.defineMacro("__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", "1");
if (HasDotProd)
Builder.defineMacro("__ARM_FEATURE_DOTPROD", "1");
if (HasMTE)
Builder.defineMacro("__ARM_FEATURE_MEMORY_TAGGING", "1");
if (HasTME)
Builder.defineMacro("__ARM_FEATURE_TME", "1");
if (HasMatMul)
Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1");
if (HasLSE)
Builder.defineMacro("__ARM_FEATURE_ATOMICS", "1");
if (HasBFloat16) {
Builder.defineMacro("__ARM_FEATURE_BF16", "1");
Builder.defineMacro("__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", "1");
Builder.defineMacro("__ARM_BF16_FORMAT_ALTERNATIVE", "1");
Builder.defineMacro("__ARM_FEATURE_BF16_SCALAR_ARITHMETIC", "1");
}
if ((FPU & SveMode) && HasBFloat16) {
Builder.defineMacro("__ARM_FEATURE_SVE_BF16", "1");
}
if ((FPU & SveMode) && HasMatmulFP64)
Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_FP64", "1");
if ((FPU & SveMode) && HasMatmulFP32)
Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_FP32", "1");
if ((FPU & SveMode) && HasMatMul)
Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_INT8", "1");
if ((FPU & NeonMode) && HasFP16FML)
Builder.defineMacro("__ARM_FEATURE_FP16_FML", "1");
if (Opts.hasSignReturnAddress()) {
// Bitmask:
// 0: Protection using the A key
// 1: Protection using the B key
// 2: Protection including leaf functions
unsigned Value = 0;
if (Opts.isSignReturnAddressWithAKey())
Value |= (1 << 0);
else
Value |= (1 << 1);
if (Opts.isSignReturnAddressScopeAll())
Value |= (1 << 2);
Builder.defineMacro("__ARM_FEATURE_PAC_DEFAULT", std::to_string(Value));
}
if (Opts.BranchTargetEnforcement)
Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1");
if (Opts.GuardedControlStack)
Builder.defineMacro("__ARM_FEATURE_GCS_DEFAULT", "1");
if (HasLS64)
Builder.defineMacro("__ARM_FEATURE_LS64", "1");
if (HasRandGen)
Builder.defineMacro("__ARM_FEATURE_RNG", "1");
if (HasMOPS)
Builder.defineMacro("__ARM_FEATURE_MOPS", "1");
if (HasD128)
Builder.defineMacro("__ARM_FEATURE_SYSREG128", "1");
if (HasGCS)
Builder.defineMacro("__ARM_FEATURE_GCS", "1");
if (*ArchInfo == llvm::AArch64::ARMV8_1A)
getTargetDefinesARMV81A(Opts, Builder);
else if (*ArchInfo == llvm::AArch64::ARMV8_2A)
getTargetDefinesARMV82A(Opts, Builder);
else if (*ArchInfo == llvm::AArch64::ARMV8_3A)
getTargetDefinesARMV83A(Opts, Builder);
else if (*ArchInfo == llvm::AArch64::ARMV8_4A)
getTargetDefinesARMV84A(Opts, Builder);
else if (*ArchInfo == llvm::AArch64::ARMV8_5A)
getTargetDefinesARMV85A(Opts, Builder);
else if (*ArchInfo == llvm::AArch64::ARMV8_6A)
getTargetDefinesARMV86A(Opts, Builder);
else if (*ArchInfo == llvm::AArch64::ARMV8_7A)
getTargetDefinesARMV87A(Opts, Builder);
else if (*ArchInfo == llvm::AArch64::ARMV8_8A)
getTargetDefinesARMV88A(Opts, Builder);
else if (*ArchInfo == llvm::AArch64::ARMV8_9A)
getTargetDefinesARMV89A(Opts, Builder);
else if (*ArchInfo == llvm::AArch64::ARMV9A)
getTargetDefinesARMV9A(Opts, Builder);
else if (*ArchInfo == llvm::AArch64::ARMV9_1A)
getTargetDefinesARMV91A(Opts, Builder);
else if (*ArchInfo == llvm::AArch64::ARMV9_2A)
getTargetDefinesARMV92A(Opts, Builder);
else if (*ArchInfo == llvm::AArch64::ARMV9_3A)
getTargetDefinesARMV93A(Opts, Builder);
else if (*ArchInfo == llvm::AArch64::ARMV9_4A)
getTargetDefinesARMV94A(Opts, Builder);
else if (*ArchInfo == llvm::AArch64::ARMV9_5A)
getTargetDefinesARMV95A(Opts, Builder);
// All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8|16) builtins work.
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
// Allow detection of fast FMA support.
Builder.defineMacro("__FP_FAST_FMA", "1");
Builder.defineMacro("__FP_FAST_FMAF", "1");
// C/C++ operators work on both VLS and VLA SVE types
if (FPU & SveMode)
Builder.defineMacro("__ARM_FEATURE_SVE_VECTOR_OPERATORS", "2");
if (Opts.VScaleMin && Opts.VScaleMin == Opts.VScaleMax) {
Builder.defineMacro("__ARM_FEATURE_SVE_BITS", Twine(Opts.VScaleMin * 128));
}
}
ArrayRef<Builtin::Info> AArch64TargetInfo::getTargetBuiltins() const {
return llvm::ArrayRef(BuiltinInfo, clang::AArch64::LastTSBuiltin -
Builtin::FirstTSBuiltin);
}
std::optional<std::pair<unsigned, unsigned>>
AArch64TargetInfo::getVScaleRange(const LangOptions &LangOpts) const {
if (LangOpts.VScaleMin || LangOpts.VScaleMax)
return std::pair<unsigned, unsigned>(
LangOpts.VScaleMin ? LangOpts.VScaleMin : 1, LangOpts.VScaleMax);
if (hasFeature("sve"))
return std::pair<unsigned, unsigned>(1, 16);
return std::nullopt;
}
unsigned AArch64TargetInfo::multiVersionSortPriority(StringRef Name) const {
if (Name == "default")
return 0;
if (auto Ext = llvm::AArch64::parseArchExtension(Name))
return Ext->FmvPriority;
return 0;
}
unsigned AArch64TargetInfo::multiVersionFeatureCost() const {
// Take the maximum priority as per feature cost, so more features win.
return llvm::AArch64::ExtensionInfo::MaxFMVPriority;
}
bool AArch64TargetInfo::doesFeatureAffectCodeGen(StringRef Name) const {
if (auto Ext = llvm::AArch64::parseArchExtension(Name))
return !Ext->DependentFeatures.empty();
return false;
}
StringRef AArch64TargetInfo::getFeatureDependencies(StringRef Name) const {
if (auto Ext = llvm::AArch64::parseArchExtension(Name))
return Ext->DependentFeatures;
return StringRef();
}
bool AArch64TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
return llvm::AArch64::parseArchExtension(FeatureStr).has_value();
}
bool AArch64TargetInfo::hasFeature(StringRef Feature) const {
return llvm::StringSwitch<bool>(Feature)
.Cases("aarch64", "arm64", "arm", true)
.Case("fmv", HasFMV)
.Cases("neon", "fp", "simd", FPU & NeonMode)
.Case("jscvt", HasJSCVT)
.Case("fcma", HasFCMA)
.Case("rng", HasRandGen)
.Case("flagm", HasFlagM)
.Case("flagm2", HasAlternativeNZCV)
.Case("fp16fml", HasFP16FML)
.Case("dotprod", HasDotProd)
.Case("sm4", HasSM4)
.Case("rdm", HasRDM)
.Case("lse", HasLSE)
.Case("crc", HasCRC)
.Case("sha2", HasSHA2)
.Case("sha3", HasSHA3)
.Cases("aes", "pmull", HasAES)
.Cases("fp16", "fullfp16", HasFullFP16)
.Case("dit", HasDIT)
.Case("dpb", HasCCPP)
.Case("dpb2", HasCCDP)
.Case("rcpc", HasRCPC)
.Case("frintts", HasFRInt3264)
.Case("i8mm", HasMatMul)
.Case("bf16", HasBFloat16)
.Case("sve", FPU & SveMode)
.Case("sve-bf16", FPU & SveMode && HasBFloat16)
.Case("sve-i8mm", FPU & SveMode && HasMatMul)
.Case("f32mm", FPU & SveMode && HasMatmulFP32)
.Case("f64mm", FPU & SveMode && HasMatmulFP64)
.Case("sve2", FPU & SveMode && HasSVE2)
.Case("sve2-pmull128", FPU & SveMode && HasSVE2AES)
.Case("sve2-bitperm", FPU & SveMode && HasSVE2BitPerm)
.Case("sve2-sha3", FPU & SveMode && HasSVE2SHA3)
.Case("sve2-sm4", FPU & SveMode && HasSVE2SM4)
.Case("sme", HasSME)
.Case("sme2", HasSME2)
.Case("sme-f64f64", HasSMEF64F64)
.Case("sme-i16i64", HasSMEI16I64)
.Case("sme-fa64", HasSMEFA64)
.Cases("memtag", "memtag2", HasMTE)
.Case("sb", HasSB)
.Case("predres", HasPredRes)
.Cases("ssbs", "ssbs2", HasSSBS)
.Case("bti", HasBTI)
.Cases("ls64", "ls64_v", "ls64_accdata", HasLS64)
.Case("wfxt", HasWFxT)
.Case("rcpc3", HasRCPC3)
.Default(false);
}
void AArch64TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
StringRef Name, bool Enabled) const {
Features[Name] = Enabled;
// If the feature is an architecture feature (like v8.2a), add all previous
// architecture versions and any dependant target features.
const std::optional<llvm::AArch64::ArchInfo> ArchInfo =
llvm::AArch64::ArchInfo::findBySubArch(Name);
if (!ArchInfo)
return; // Not an architecture, nothing more to do.
// Disabling an architecture feature does not affect dependent features
if (!Enabled)
return;
for (const auto *OtherArch : llvm::AArch64::ArchInfos)
if (ArchInfo->implies(*OtherArch))
Features[OtherArch->getSubArch()] = true;
// Set any features implied by the architecture
std::vector<StringRef> CPUFeats;
if (llvm::AArch64::getExtensionFeatures(ArchInfo->DefaultExts, CPUFeats)) {
for (auto F : CPUFeats) {
assert(F[0] == '+' && "Expected + in target feature!");
Features[F.drop_front(1)] = true;
}
}
}
bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
DiagnosticsEngine &Diags) {
for (const auto &Feature : Features) {
if (Feature == "-fp-armv8")
HasNoFP = true;
if (Feature == "-neon")
HasNoNeon = true;
if (Feature == "-sve")
HasNoSVE = true;
if (Feature == "+neon" || Feature == "+fp-armv8")
FPU |= NeonMode;
if (Feature == "+jscvt") {
HasJSCVT = true;
FPU |= NeonMode;
}
if (Feature == "+fcma") {
HasFCMA = true;
FPU |= NeonMode;
}
if (Feature == "+sve") {
FPU |= NeonMode;
FPU |= SveMode;
HasFullFP16 = true;
}
if (Feature == "+sve2") {
FPU |= NeonMode;
FPU |= SveMode;
HasFullFP16 = true;
HasSVE2 = true;
}
if (Feature == "+sve2-aes") {
FPU |= NeonMode;
FPU |= SveMode;
HasFullFP16 = true;
HasSVE2 = true;
HasSVE2AES = true;
}
if (Feature == "+sve2-sha3") {
FPU |= NeonMode;
FPU |= SveMode;
HasFullFP16 = true;
HasSVE2 = true;
HasSVE2SHA3 = true;
}
if (Feature == "+sve2-sm4") {
FPU |= NeonMode;
FPU |= SveMode;
HasFullFP16 = true;
HasSVE2 = true;
HasSVE2SM4 = true;
}
if (Feature == "+sve2-bitperm") {
FPU |= NeonMode;
FPU |= SveMode;
HasFullFP16 = true;
HasSVE2 = true;
HasSVE2BitPerm = true;
}
if (Feature == "+f32mm") {
FPU |= NeonMode;
FPU |= SveMode;
HasFullFP16 = true;
HasMatmulFP32 = true;
}
if (Feature == "+f64mm") {
FPU |= NeonMode;
FPU |= SveMode;
HasFullFP16 = true;
HasMatmulFP64 = true;
}
if (Feature == "+sme") {
HasSME = true;
HasBFloat16 = true;
HasFullFP16 = true;
}
if (Feature == "+sme2") {
HasSME = true;
HasSME2 = true;
HasBFloat16 = true;
HasFullFP16 = true;
}
if (Feature == "+sme-f64f64") {
HasSME = true;
HasSMEF64F64 = true;
HasBFloat16 = true;
HasFullFP16 = true;
}
if (Feature == "+sme-i16i64") {
HasSME = true;
HasSMEI16I64 = true;
HasBFloat16 = true;
HasFullFP16 = true;
}
if (Feature == "+sme-fa64") {
FPU |= NeonMode;
FPU |= SveMode;
HasSME = true;
HasSVE2 = true;
HasSMEFA64 = true;
}
if (Feature == "+sb")
HasSB = true;
if (Feature == "+predres")
HasPredRes = true;
if (Feature == "+ssbs")
HasSSBS = true;
if (Feature == "+bti")
HasBTI = true;
if (Feature == "+wfxt")
HasWFxT = true;
if (Feature == "-fmv")
HasFMV = false;
if (Feature == "+crc")
HasCRC = true;
if (Feature == "+rcpc")
HasRCPC = true;
if (Feature == "+aes") {
FPU |= NeonMode;
HasAES = true;
}
if (Feature == "+sha2") {
FPU |= NeonMode;
HasSHA2 = true;
}
if (Feature == "+sha3") {
FPU |= NeonMode;
HasSHA2 = true;
HasSHA3 = true;
}
if (Feature == "+rdm") {
FPU |= NeonMode;
HasRDM = true;
}
if (Feature == "+dit")
HasDIT = true;
if (Feature == "+cccp")
HasCCPP = true;
if (Feature == "+ccdp") {
HasCCPP = true;
HasCCDP = true;
}
if (Feature == "+fptoint")
HasFRInt3264 = true;
if (Feature == "+sm4") {
FPU |= NeonMode;
HasSM4 = true;
}
if (Feature == "+strict-align")
HasUnaligned = false;
// All predecessor archs are added but select the latest one for ArchKind.
if (Feature == "+v8a" && ArchInfo->Version < llvm::AArch64::ARMV8A.Version)
ArchInfo = &llvm::AArch64::ARMV8A;
if (Feature == "+v8.1a" &&
ArchInfo->Version < llvm::AArch64::ARMV8_1A.Version)
ArchInfo = &llvm::AArch64::ARMV8_1A;
if (Feature == "+v8.2a" &&
ArchInfo->Version < llvm::AArch64::ARMV8_2A.Version)
ArchInfo = &llvm::AArch64::ARMV8_2A;
if (Feature == "+v8.3a" &&
ArchInfo->Version < llvm::AArch64::ARMV8_3A.Version)
ArchInfo = &llvm::AArch64::ARMV8_3A;
if (Feature == "+v8.4a" &&
ArchInfo->Version < llvm::AArch64::ARMV8_4A.Version)
ArchInfo = &llvm::AArch64::ARMV8_4A;
if (Feature == "+v8.5a" &&
ArchInfo->Version < llvm::AArch64::ARMV8_5A.Version)
ArchInfo = &llvm::AArch64::ARMV8_5A;
if (Feature == "+v8.6a" &&
ArchInfo->Version < llvm::AArch64::ARMV8_6A.Version)
ArchInfo = &llvm::AArch64::ARMV8_6A;
if (Feature == "+v8.7a" &&
ArchInfo->Version < llvm::AArch64::ARMV8_7A.Version)
ArchInfo = &llvm::AArch64::ARMV8_7A;
if (Feature == "+v8.8a" &&
ArchInfo->Version < llvm::AArch64::ARMV8_8A.Version)
ArchInfo = &llvm::AArch64::ARMV8_8A;
if (Feature == "+v8.9a" &&
ArchInfo->Version < llvm::AArch64::ARMV8_9A.Version)
ArchInfo = &llvm::AArch64::ARMV8_9A;
if (Feature == "+v9a" && ArchInfo->Version < llvm::AArch64::ARMV9A.Version)
ArchInfo = &llvm::AArch64::ARMV9A;
if (Feature == "+v9.1a" &&
ArchInfo->Version < llvm::AArch64::ARMV9_1A.Version)
ArchInfo = &llvm::AArch64::ARMV9_1A;
if (Feature == "+v9.2a" &&
ArchInfo->Version < llvm::AArch64::ARMV9_2A.Version)
ArchInfo = &llvm::AArch64::ARMV9_2A;
if (Feature == "+v9.3a" &&
ArchInfo->Version < llvm::AArch64::ARMV9_3A.Version)
ArchInfo = &llvm::AArch64::ARMV9_3A;
if (Feature == "+v9.4a" &&
ArchInfo->Version < llvm::AArch64::ARMV9_4A.Version)
ArchInfo = &llvm::AArch64::ARMV9_4A;
if (Feature == "+v9.5a" &&
ArchInfo->Version < llvm::AArch64::ARMV9_5A.Version)
ArchInfo = &llvm::AArch64::ARMV9_5A;
if (Feature == "+v8r")
ArchInfo = &llvm::AArch64::ARMV8R;
if (Feature == "+fullfp16") {
FPU |= NeonMode;
HasFullFP16 = true;
}
if (Feature == "+dotprod") {
FPU |= NeonMode;
HasDotProd = true;
}
if (Feature == "+fp16fml") {
FPU |= NeonMode;
HasFullFP16 = true;
HasFP16FML = true;
}
if (Feature == "+mte")
HasMTE = true;
if (Feature == "+tme")
HasTME = true;
if (Feature == "+pauth")
HasPAuth = true;
if (Feature == "+i8mm")
HasMatMul = true;
if (Feature == "+bf16")
HasBFloat16 = true;
if (Feature == "+lse")
HasLSE = true;
if (Feature == "+ls64")
HasLS64 = true;
if (Feature == "+rand")
HasRandGen = true;
if (Feature == "+flagm")
HasFlagM = true;
if (Feature == "+altnzcv") {
HasFlagM = true;
HasAlternativeNZCV = true;
}
if (Feature == "+mops")
HasMOPS = true;
if (Feature == "+d128")
HasD128 = true;
if (Feature == "+gcs")
HasGCS = true;
if (Feature == "+rcpc3")
HasRCPC3 = true;
}
// Check features that are manually disabled by command line options.
// This needs to be checked after architecture-related features are handled,
// making sure they are properly disabled when required.
for (const auto &Feature : Features) {
if (Feature == "-d128")
HasD128 = false;
}