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test/CodeGen/AMDGPU/GlobalISel
2 files changed +29
-3
lines changed Original file line number Diff line number Diff line change @@ -1116,9 +1116,9 @@ std::optional<APInt>
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llvm::getIConstantSplatVal (const Register Reg, const MachineRegisterInfo &MRI) {
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if (auto SplatValAndReg =
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getAnyConstantSplat (Reg, MRI, /* AllowUndef */ false )) {
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- std::optional<ValueAndVReg> ValAndVReg =
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- getIConstantVRegValWithLookThrough (SplatValAndReg->VReg , MRI);
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- return ValAndVReg->Value ;
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+ if ( std::optional<ValueAndVReg> ValAndVReg =
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+ getIConstantVRegValWithLookThrough (SplatValAndReg->VReg , MRI))
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+ return ValAndVReg->Value ;
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}
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return std::nullopt;
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+ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
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+ # RUN: llc -march=amdgcn -mcpu=gfx1030 -run-pass amdgpu-prelegalizer-combiner %s -o - | FileCheck -check-prefix=GCN %s
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+
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+ ---
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+ name : non_inlineable_imm_splat
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+ body : |
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+ bb.1:
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+ liveins: $vgpr0
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+
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+ ; GCN-LABEL: name: non_inlineable_imm_splat
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+ ; GCN: liveins: $vgpr0
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+ ; GCN-NEXT: {{ $}}
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+ ; GCN-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
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+ ; GCN-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4200
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+ ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
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+ ; GCN-NEXT: [[SUB:%[0-9]+]]:_(<2 x s16>) = G_SUB [[COPY]], [[BUILD_VECTOR]]
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+ ; GCN-NEXT: $vgpr0 = COPY [[SUB]](<2 x s16>)
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+ ; GCN-NEXT: SI_RETURN implicit $vgpr0
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+ %0:_(<2 x s16>) = COPY $vgpr0
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+ %2:_(s16) = G_FCONSTANT half 0xH4200
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+ %1:_(<2 x s16>) = G_BUILD_VECTOR %2(s16), %2(s16)
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+ %3:_(<2 x s16>) = G_SUB %0, %1
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+ $vgpr0 = COPY %3(<2 x s16>)
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+ SI_RETURN implicit $vgpr0
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+
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+ ...
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