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[RISCV] Rework .option arch target streamer interface
The current interface requires some rather ugly tracking of state due to splitting up the calls for each argument. Instead, pack them all into a single call by passing an ArrayRef. Also clean up the dodgy whitespace emitted for the directive whilst here; there was a stray space between the tab and .option, and there was a tab rather than a space after the first comma for some strange reason. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D152193
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+56
-72
lines changed

3 files changed

+56
-72
lines changed

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Lines changed: 18 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -2711,28 +2711,21 @@ bool RISCVAsmParser::parseDirectiveOption() {
27112711
}
27122712

27132713
if (Option == "arch") {
2714-
bool PrefixEmitted = false;
2715-
bool IsExtensionList = false;
2714+
SmallVector<RISCVOptionArchArg> Args;
27162715
do {
27172716
if (Parser.parseComma())
27182717
return true;
27192718

2720-
bool IsAdd, IsFull;
2721-
if (parseOptionalToken(AsmToken::Plus)) {
2722-
IsAdd = true;
2723-
IsFull = false;
2724-
IsExtensionList = true;
2725-
} else if (parseOptionalToken(AsmToken::Minus)) {
2726-
IsAdd = false;
2727-
IsFull = false;
2728-
IsExtensionList = true;
2729-
} else {
2730-
if (IsExtensionList)
2731-
return Error(Parser.getTok().getLoc(),
2732-
"unexpected token, expected + or -");
2733-
2734-
IsFull = true;
2735-
}
2719+
RISCVOptionArchArgType Type;
2720+
if (parseOptionalToken(AsmToken::Plus))
2721+
Type = RISCVOptionArchArgType::Plus;
2722+
else if (parseOptionalToken(AsmToken::Minus))
2723+
Type = RISCVOptionArchArgType::Minus;
2724+
else if (!Args.empty())
2725+
return Error(Parser.getTok().getLoc(),
2726+
"unexpected token, expected + or -");
2727+
else
2728+
Type = RISCVOptionArchArgType::Full;
27362729

27372730
if (Parser.getTok().isNot(AsmToken::Identifier))
27382731
return Error(Parser.getTok().getLoc(),
@@ -2742,14 +2735,12 @@ bool RISCVAsmParser::parseDirectiveOption() {
27422735
SMLoc Loc = Parser.getTok().getLoc();
27432736
Parser.Lex();
27442737

2745-
if (IsFull) {
2738+
if (Type == RISCVOptionArchArgType::Full) {
27462739
std::string Result;
27472740
if (resetToArch(Arch, Loc, Result, true))
27482741
return true;
27492742

2750-
getTargetStreamer().emitDirectiveOptionArchFullArch(Result,
2751-
PrefixEmitted);
2752-
2743+
Args.emplace_back(Type, Result);
27532744
break;
27542745
}
27552746

@@ -2764,8 +2755,9 @@ bool RISCVAsmParser::parseDirectiveOption() {
27642755
return Error(Loc, "unknown extension feature");
27652756
}
27662757

2767-
bool HasComma = getTok().is(AsmToken::Comma);
2768-
if (IsAdd) {
2758+
Args.emplace_back(Type, Ext->Key);
2759+
2760+
if (Type == RISCVOptionArchArgType::Plus) {
27692761
setFeatureBits(Ext->Value, Ext->Key);
27702762
auto ParseResult = RISCVFeatures::parseFeatureBits(isRV64(), STI->getFeatureBits());
27712763
if (!ParseResult) {
@@ -2777,9 +2769,8 @@ bool RISCVAsmParser::parseDirectiveOption() {
27772769

27782770
return Error(Loc, OutputErrMsg.str());
27792771
}
2780-
getTargetStreamer().emitDirectiveOptionArchPlusOrMinus(
2781-
Ext->Key, /*Enable*/ true, PrefixEmitted, HasComma);
27822772
} else {
2773+
assert(Type == RISCVOptionArchArgType::Minus);
27832774
// It is invalid to disable an extension that there are other enabled
27842775
// extensions depend on it.
27852776
// TODO: Make use of RISCVISAInfo to handle this
@@ -2793,14 +2784,13 @@ bool RISCVAsmParser::parseDirectiveOption() {
27932784
}
27942785

27952786
clearFeatureBits(Ext->Value, Ext->Key);
2796-
getTargetStreamer().emitDirectiveOptionArchPlusOrMinus(
2797-
Ext->Key, /*Enable*/ false, PrefixEmitted, HasComma);
27982787
}
27992788
} while (Parser.getTok().isNot(AsmToken::EndOfStatement));
28002789

28012790
if (Parser.parseEOL())
28022791
return true;
28032792

2793+
getTargetStreamer().emitDirectiveOptionArch(Args);
28042794
return false;
28052795
}
28062796

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

Lines changed: 22 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -33,12 +33,9 @@ void RISCVTargetStreamer::emitDirectiveOptionRVC() {}
3333
void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {}
3434
void RISCVTargetStreamer::emitDirectiveOptionRelax() {}
3535
void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {}
36+
void RISCVTargetStreamer::emitDirectiveOptionArch(
37+
ArrayRef<RISCVOptionArchArg> Args) {}
3638
void RISCVTargetStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) {}
37-
void RISCVTargetStreamer::emitDirectiveOptionArchFullArch(StringRef Value,
38-
bool &PrefixEmitted) {
39-
}
40-
void RISCVTargetStreamer::emitDirectiveOptionArchPlusOrMinus(
41-
StringRef Value, bool Enable, bool &PrefixEmitted, bool EmitComma) {}
4239
void RISCVTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {}
4340
void RISCVTargetStreamer::finishAttributeSection() {}
4441
void RISCVTargetStreamer::emitTextAttribute(unsigned Attribute,
@@ -106,6 +103,26 @@ void RISCVTargetAsmStreamer::emitDirectiveOptionNoRelax() {
106103
OS << "\t.option\tnorelax\n";
107104
}
108105

106+
void RISCVTargetAsmStreamer::emitDirectiveOptionArch(
107+
ArrayRef<RISCVOptionArchArg> Args) {
108+
OS << "\t.option\tarch";
109+
for (const auto &Arg : Args) {
110+
OS << ", ";
111+
switch (Arg.Type) {
112+
case RISCVOptionArchArgType::Full:
113+
break;
114+
case RISCVOptionArchArgType::Plus:
115+
OS << "+";
116+
break;
117+
case RISCVOptionArchArgType::Minus:
118+
OS << "-";
119+
break;
120+
}
121+
OS << Arg.Value;
122+
}
123+
OS << "\n";
124+
}
125+
109126
void RISCVTargetAsmStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) {
110127
OS << "\t.variant_cc\t" << Symbol.getName() << "\n";
111128
}
@@ -123,33 +140,4 @@ void RISCVTargetAsmStreamer::emitIntTextAttribute(unsigned Attribute,
123140
unsigned IntValue,
124141
StringRef StringValue) {}
125142

126-
static void emitDirectiveOptionArchPrefix(formatted_raw_ostream &OS,
127-
bool &PrefixEmitted) {
128-
if (!PrefixEmitted) {
129-
OS << "\t .option\tarch,\t";
130-
PrefixEmitted = true;
131-
}
132-
}
133-
134-
static void emitCommaOrNextLine(formatted_raw_ostream &OS, bool EmitComma) {
135-
if (EmitComma)
136-
OS << ", ";
137-
else
138-
OS << "\n";
139-
}
140-
141-
void RISCVTargetAsmStreamer::emitDirectiveOptionArchFullArch(
142-
StringRef Value, bool &PrefixEmitted) {
143-
emitDirectiveOptionArchPrefix(OS, PrefixEmitted);
144-
OS << Value;
145-
emitCommaOrNextLine(OS, false);
146-
}
147-
148-
void RISCVTargetAsmStreamer::emitDirectiveOptionArchPlusOrMinus(
149-
StringRef Value, bool Enable, bool &PrefixEmitted, bool EmitComma) {
150-
emitDirectiveOptionArchPrefix(OS, PrefixEmitted);
151-
OS << (Enable ? "+" : "-") << Value;
152-
emitCommaOrNextLine(OS, EmitComma);
153-
}
154-
155143
void RISCVTargetAsmStreamer::finishAttributeSection() {}

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h

Lines changed: 16 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,20 @@ namespace llvm {
1717

1818
class formatted_raw_ostream;
1919

20+
enum class RISCVOptionArchArgType {
21+
Full,
22+
Plus,
23+
Minus,
24+
};
25+
26+
struct RISCVOptionArchArg {
27+
RISCVOptionArchArgType Type;
28+
std::string Value;
29+
30+
RISCVOptionArchArg(RISCVOptionArchArgType Type, std::string Value)
31+
: Type(Type), Value(Value) {}
32+
};
33+
2034
class RISCVTargetStreamer : public MCTargetStreamer {
2135
RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
2236

@@ -33,12 +47,8 @@ class RISCVTargetStreamer : public MCTargetStreamer {
3347
virtual void emitDirectiveOptionNoRVC();
3448
virtual void emitDirectiveOptionRelax();
3549
virtual void emitDirectiveOptionNoRelax();
50+
virtual void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args);
3651
virtual void emitDirectiveVariantCC(MCSymbol &Symbol);
37-
virtual void emitDirectiveOptionArchFullArch(StringRef Value,
38-
bool &PrefixEmitted);
39-
virtual void emitDirectiveOptionArchPlusOrMinus(StringRef Value, bool Enable,
40-
bool &PrefixEmitted,
41-
bool EmitComma);
4252
virtual void emitAttribute(unsigned Attribute, unsigned Value);
4353
virtual void finishAttributeSection();
4454
virtual void emitTextAttribute(unsigned Attribute, StringRef String);
@@ -71,12 +81,8 @@ class RISCVTargetAsmStreamer : public RISCVTargetStreamer {
7181
void emitDirectiveOptionNoRVC() override;
7282
void emitDirectiveOptionRelax() override;
7383
void emitDirectiveOptionNoRelax() override;
84+
void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args) override;
7485
void emitDirectiveVariantCC(MCSymbol &Symbol) override;
75-
void emitDirectiveOptionArchFullArch(StringRef Value,
76-
bool &PrefixEmitted) override;
77-
void emitDirectiveOptionArchPlusOrMinus(StringRef Value, bool Enable,
78-
bool &PrefixEmitted,
79-
bool EmitComma) override;
8086
};
8187

8288
}

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