@@ -120,19 +120,6 @@ static unsigned getVMSetForLMul(RISCVII::VLMUL LMUL) {
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llvm_unreachable (" Unknown VLMUL enum" );
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}
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- // / Inserts an operand at Idx in MI, pushing back any operands.
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- static void insertOperand (MachineInstr &MI, MachineOperand MO, unsigned Idx) {
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- SmallVector<MachineOperand> OpsToAddBack;
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- unsigned NumTailOps = MI.getNumOperands () - Idx;
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- for (unsigned I = 0 ; I < NumTailOps; I++) {
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- OpsToAddBack.push_back (MI.getOperand (Idx));
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- MI.removeOperand (Idx);
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- }
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- MI.addOperand (MO);
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- for (MachineOperand &TailOp : OpsToAddBack)
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- MI.addOperand (TailOp);
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- }
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-
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// Try to sink From to before To, also sinking any instructions between From and
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// To where there is a write-after-read dependency on a physical register.
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static bool sinkInstructionAndDeps (MachineInstr &From, MachineInstr &To) {
@@ -370,8 +357,8 @@ bool RISCVFoldMasks::foldVMergeIntoOps(MachineInstr &MI,
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// TODO: Increment MaskOpIdx by number of explicit defs in tablegen?
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unsigned MaskOpIdx = Info->MaskOpIdx + TrueMI.getNumExplicitDefs ();
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- insertOperand ( TrueMI, MachineOperand::CreateReg (RISCV::V0, false ),
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- MaskOpIdx );
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+ TrueMI. insert (& TrueMI. getOperand (MaskOpIdx ),
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+ MachineOperand::CreateReg (RISCV::V0, false ) );
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}
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// Update the AVL.
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