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momchil-velikovmomchil-velikov
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[AArch64] Lower extending sitofp using tbl
In a similar manner as in https://reviews.llvm.org/D133494 use `TBL` to place bytes in the *upper* part of `i32` elements and then convert to float using fixed-point `scvtf`, i.e. scvtf Vd.4s, Vn.4s, #24 Change-Id: Ib9df3e4243612cbee8560907b24b14e76b61f265
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lines changed

3 files changed

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‎llvm/lib/CodeGen/CodeGenPrepare.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -8333,7 +8333,8 @@ bool CodeGenPrepare::optimizeInst(Instruction *I, ModifyDT &ModifiedDT) {
83338333
if (OptimizeNoopCopyExpression(CI, *TLI, *DL))
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return true;
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8336-
if ((isa<UIToFPInst>(I) || isa<FPToUIInst>(I) || isa<TruncInst>(I)) &&
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if ((isa<UIToFPInst>(I) || isa<SIToFPInst>(I) || isa<FPToUIInst>(I) ||
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isa<TruncInst>(I)) &&
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TLI->optimizeExtendOrTruncateConversion(
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I, LI->getLoopFor(I->getParent()), *TTI))
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return true;

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

+35
Original file line numberDiff line numberDiff line change
@@ -15763,6 +15763,24 @@ static Value *createTblShuffleForZExt(IRBuilderBase &Builder, Value *Op,
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return Result;
1576415764
}
1576515765

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static Value *createTblShuffleForSExt(IRBuilderBase &Builder, Value *Op,
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FixedVectorType *DstTy,
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bool IsLittleEndian) {
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auto *SrcTy = cast<FixedVectorType>(Op->getType());
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auto SrcWidth = cast<IntegerType>(SrcTy->getElementType())->getBitWidth();
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auto DstWidth = cast<IntegerType>(DstTy->getElementType())->getBitWidth();
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SmallVector<int> Mask;
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if (!createTblShuffleMask(SrcWidth, DstWidth, SrcTy->getNumElements(),
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!IsLittleEndian, Mask))
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return nullptr;
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auto *FirstEltZero = Builder.CreateInsertElement(
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PoisonValue::get(SrcTy), Builder.getInt8(0), uint64_t(0));
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return Builder.CreateShuffleVector(Op, FirstEltZero, Mask);
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}
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static void createTblForTrunc(TruncInst *TI, bool IsLittleEndian) {
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IRBuilder<> Builder(TI);
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SmallVector<Value *> Parts;
@@ -15951,6 +15969,23 @@ bool AArch64TargetLowering::optimizeExtendOrTruncateConversion(
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return true;
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}
1595315971

15972+
auto *SIToFP = dyn_cast<SIToFPInst>(I);
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if (SIToFP && SrcTy->getElementType()->isIntegerTy(8) &&
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DstTy->getElementType()->isFloatTy()) {
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IRBuilder<> Builder(I);
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auto *Shuffle = createTblShuffleForSExt(Builder, I->getOperand(0),
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FixedVectorType::getInteger(DstTy),
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Subtarget->isLittleEndian());
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if (!Shuffle)
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return false;
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auto *Cast = Builder.CreateBitCast(Shuffle, VectorType::getInteger(DstTy));
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auto *AShr = Builder.CreateAShr(Cast, 24, "", true);
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auto *SI = Builder.CreateSIToFP(AShr, DstTy);
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I->replaceAllUsesWith(SI);
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I->eraseFromParent();
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return true;
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}
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// Convert 'fptoui <(8|16) x float> to <(8|16) x i8>' to a wide fptoui
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// followed by a truncate lowered to using tbl.4.
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auto *FPToUI = dyn_cast<FPToUIInst>(I);

‎llvm/test/CodeGen/AArch64/sitofp-to-tbl.ll

+196
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,196 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -verify-machineinstrs < %s | FileCheck %s
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target triple = "aarch64-linux"
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; CHECK-LABEL: .LCPI0_0:
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 5
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 6
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 7
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; CHECK-NEXT: .LCPI0_1:
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 2
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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define void @sitofp_v8i8_to_v8f32(ptr %src, ptr %dst) {
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; CHECK-LABEL: sitofp_v8i8_to_v8f32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: adrp x8, .LCPI0_0
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; CHECK-NEXT: adrp x9, .LCPI0_1
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; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI0_0]
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; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI0_1]
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; CHECK-NEXT: mov x8, xzr
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; CHECK-NEXT: .LBB0_1: // %loop
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldr d2, [x0, x8, lsl #3]
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; CHECK-NEXT: add x9, x1, x8, lsl #5
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; CHECK-NEXT: add x8, x8, #1
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; CHECK-NEXT: cmp x8, #1000
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; CHECK-NEXT: tbl v3.16b, { v2.16b }, v0.16b
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; CHECK-NEXT: tbl v2.16b, { v2.16b }, v1.16b
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; CHECK-NEXT: scvtf v3.4s, v3.4s, #24
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; CHECK-NEXT: scvtf v2.4s, v2.4s, #24
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; CHECK-NEXT: stp q2, q3, [x9]
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; CHECK-NEXT: b.eq .LBB0_1
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; CHECK-NEXT: // %bb.2: // %exit
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; CHECK-NEXT: ret
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entry:
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br label %loop
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loop:
66+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
67+
%gep.src = getelementptr inbounds <8 x i8>, ptr %src, i64 %iv
68+
%l = load <8 x i8>, ptr %gep.src
69+
%conv = sitofp <8 x i8> %l to <8 x float>
70+
%gep.dst = getelementptr inbounds <8 x float>, ptr %dst, i64 %iv
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store <8 x float> %conv, ptr %gep.dst
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%iv.next = add i64 %iv, 1
73+
%ec = icmp eq i64 %iv.next, 1000
74+
br i1 %ec, label %loop, label %exit
75+
76+
exit:
77+
ret void
78+
}
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; CHECK-LABEL: .LCPI1_0:
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 12
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 13
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 14
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 15
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; CHECK-NEXT: .LCPI1_1:
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 9
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 10
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 11
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; CHECK-NEXT: .LCPI1_2:
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 5
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 6
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 7
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; CHECK-NEXT: .LCPI1_3:
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 2
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 255
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; CHECK-NEXT: .byte 3
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149+
define void @sitofp_v16i8_to_v16f32(ptr %src, ptr %dst) {
150+
; CHECK-LABEL: sitofp_v16i8_to_v16f32:
151+
; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: adrp x8, .LCPI1_0
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; CHECK-NEXT: adrp x9, .LCPI1_1
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; CHECK-NEXT: adrp x10, .LCPI1_2
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; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI1_0]
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; CHECK-NEXT: adrp x8, .LCPI1_3
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; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI1_1]
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; CHECK-NEXT: ldr q2, [x10, :lo12:.LCPI1_2]
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; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI1_3]
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; CHECK-NEXT: mov x8, xzr
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; CHECK-NEXT: .LBB1_1: // %loop
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldr q4, [x0, x8, lsl #4]
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; CHECK-NEXT: add x9, x1, x8, lsl #6
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; CHECK-NEXT: add x8, x8, #1
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; CHECK-NEXT: cmp x8, #1000
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; CHECK-NEXT: tbl v5.16b, { v4.16b }, v0.16b
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; CHECK-NEXT: tbl v6.16b, { v4.16b }, v1.16b
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; CHECK-NEXT: tbl v7.16b, { v4.16b }, v2.16b
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; CHECK-NEXT: tbl v4.16b, { v4.16b }, v3.16b
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; CHECK-NEXT: scvtf v5.4s, v5.4s, #24
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; CHECK-NEXT: scvtf v6.4s, v6.4s, #24
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; CHECK-NEXT: scvtf v7.4s, v7.4s, #24
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; CHECK-NEXT: scvtf v4.4s, v4.4s, #24
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; CHECK-NEXT: stp q6, q5, [x9, #32]
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; CHECK-NEXT: stp q4, q7, [x9]
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; CHECK-NEXT: b.eq .LBB1_1
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; CHECK-NEXT: // %bb.2: // %exit
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; CHECK-NEXT: ret
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entry:
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br label %loop
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loop:
184+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
185+
%gep.src = getelementptr inbounds <16 x i8>, ptr %src, i64 %iv
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%l = load <16 x i8>, ptr %gep.src
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%conv = sitofp <16 x i8> %l to <16 x float>
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%gep.dst = getelementptr inbounds <16 x float>, ptr %dst, i64 %iv
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store <16 x float> %conv, ptr %gep.dst
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%iv.next = add i64 %iv, 1
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%ec = icmp eq i64 %iv.next, 1000
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br i1 %ec, label %loop, label %exit
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exit:
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ret void
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}

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