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[AMDGPU] Add live-through register set printing to GCNRegPressurePrinter pass. (#71096)
Add live-through register set printing, assuming live-through register is in live-in and live-out sets, has no redefinitions but may have uses in the block.
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‎llvm/lib/Target/AMDGPU/GCNRegPressure.cpp

+41
Original file line numberDiff line numberDiff line change
@@ -503,6 +503,34 @@ char &llvm::GCNRegPressurePrinterID = GCNRegPressurePrinter::ID;
503503

504504
INITIALIZE_PASS(GCNRegPressurePrinter, "amdgpu-print-rp", "", true, true)
505505

506+
// Return lanemask of Reg's subregs that are live-through at [Begin, End] and
507+
// are fully covered by Mask.
508+
static LaneBitmask
509+
getRegLiveThroughMask(const MachineRegisterInfo &MRI, const LiveIntervals &LIS,
510+
Register Reg, SlotIndex Begin, SlotIndex End,
511+
LaneBitmask Mask = LaneBitmask::getAll()) {
512+
513+
auto IsInOneSegment = [Begin, End](const LiveRange &LR) -> bool {
514+
auto *Segment = LR.getSegmentContaining(Begin);
515+
return Segment && Segment->contains(End);
516+
};
517+
518+
LaneBitmask LiveThroughMask;
519+
const LiveInterval &LI = LIS.getInterval(Reg);
520+
if (LI.hasSubRanges()) {
521+
for (auto &SR : LI.subranges()) {
522+
if ((SR.LaneMask & Mask) == SR.LaneMask && IsInOneSegment(SR))
523+
LiveThroughMask |= SR.LaneMask;
524+
}
525+
} else {
526+
LaneBitmask RegMask = MRI.getMaxLaneMaskForVReg(Reg);
527+
if ((RegMask & Mask) == RegMask && IsInOneSegment(LI))
528+
LiveThroughMask = RegMask;
529+
}
530+
531+
return LiveThroughMask;
532+
}
533+
506534
bool GCNRegPressurePrinter::runOnMachineFunction(MachineFunction &MF) {
507535
const MachineRegisterInfo &MRI = MF.getRegInfo();
508536
const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
@@ -604,6 +632,19 @@ bool GCNRegPressurePrinter::runOnMachineFunction(MachineFunction &MF) {
604632
OS << PFX " Live-out:" << llvm::print(LiveOut, MRI);
605633
if (UseDownwardTracker)
606634
ReportLISMismatchIfAny(LiveOut, getLiveRegs(MBBEndSlot, LIS, MRI));
635+
636+
GCNRPTracker::LiveRegSet LiveThrough;
637+
for (auto [Reg, Mask] : LiveIn) {
638+
LaneBitmask MaskIntersection = Mask & LiveOut.lookup(Reg);
639+
if (MaskIntersection.any()) {
640+
LaneBitmask LTMask = getRegLiveThroughMask(
641+
MRI, LIS, Reg, MBBStartSlot, MBBEndSlot, MaskIntersection);
642+
if (LTMask.any())
643+
LiveThrough[Reg] = LTMask;
644+
}
645+
}
646+
OS << PFX " Live-thr:" << llvm::print(LiveThrough, MRI);
647+
OS << printRP(getRegPressure(MRI, LiveThrough)) << '\n';
607648
}
608649
OS << "...\n";
609650
return false;

‎llvm/test/CodeGen/AMDGPU/regpressure_printer.mir

+46
Original file line numberDiff line numberDiff line change
@@ -17,18 +17,24 @@ body: |
1717
; RP-NEXT: 2 1 %1:sgpr_64 = IMPLICIT_DEF
1818
; RP-NEXT: 2 1
1919
; RP-NEXT: Live-out: %0:0000000000000003 %1:000000000000000F
20+
; RP-NEXT: Live-thr:
21+
; RP-NEXT: 0 0
2022
; RP-NEXT: bb.1:
2123
; RP-NEXT: Live-in: %0:0000000000000003 %1:000000000000000F
2224
; RP-NEXT: SGPR VGPR
2325
; RP-NEXT: 2 1
2426
; RP-NEXT: Live-out: %0:0000000000000003 %1:000000000000000F
27+
; RP-NEXT: Live-thr: %0:0000000000000003 %1:000000000000000F
28+
; RP-NEXT: 2 1
2529
; RP-NEXT: bb.2:
2630
; RP-NEXT: Live-in: %0:0000000000000003 %1:000000000000000F
2731
; RP-NEXT: SGPR VGPR
2832
; RP-NEXT: 2 1
2933
; RP-NEXT: 2 1 S_NOP 0, implicit %0:vgpr_32, implicit %1:sgpr_64
3034
; RP-NEXT: 0 0
3135
; RP-NEXT: Live-out:
36+
; RP-NEXT: Live-thr:
37+
; RP-NEXT: 0 0
3238
bb.0:
3339
%0:vgpr_32 = V_MOV_B32_e32 42, implicit $exec
3440
%1:sgpr_64 = IMPLICIT_DEF
@@ -49,6 +55,8 @@ body: |
4955
; RPU-NEXT: 3 0 %0:sgpr_128 = IMPLICIT_DEF
5056
; RPU-NEXT: 3 0
5157
; RPU-NEXT: Live-out: %0:00000000000000F3
58+
; RPU-NEXT: Live-thr:
59+
; RPU-NEXT: 0 0
5260
; RPU-NEXT: bb.1:
5361
; RPU-NEXT: Live-in: %0:00000000000000F3
5462
; RPU-NEXT: SGPR VGPR
@@ -68,13 +76,17 @@ body: |
6876
; RPU-NEXT: 2 0 S_NOP 0, implicit %0.sub3:sgpr_128
6977
; RPU-NEXT: 2 0
7078
; RPU-NEXT: Live-out: %0:00000000000000C3
79+
; RPU-NEXT: Live-thr: %0:00000000000000C0
80+
; RPU-NEXT: 1 0
7181
; RPU-NEXT: bb.2:
7282
; RPU-NEXT: Live-in: %0:00000000000000C3
7383
; RPU-NEXT: SGPR VGPR
7484
; RPU-NEXT: 2 0
7585
; RPU-NEXT: 2 0 S_NOP 0, implicit %0.sub3:sgpr_128, implicit %0.sub0:sgpr_128
7686
; RPU-NEXT: 0 0
7787
; RPU-NEXT: Live-out:
88+
; RPU-NEXT: Live-thr:
89+
; RPU-NEXT: 0 0
7890
;
7991
; RPD-LABEL: name: live_through_test
8092
; RPD: bb.0:
@@ -84,6 +96,8 @@ body: |
8496
; RPD-NEXT: 4 0 %0:sgpr_128 = IMPLICIT_DEF
8597
; RPD-NEXT: 3 0
8698
; RPD-NEXT: Live-out: %0:00000000000000F3
99+
; RPD-NEXT: Live-thr:
100+
; RPD-NEXT: 0 0
87101
; RPD-NEXT: bb.1:
88102
; RPD-NEXT: Live-in: %0:00000000000000F3
89103
; RPD-NEXT: SGPR VGPR
@@ -103,13 +117,17 @@ body: |
103117
; RPD-NEXT: 2 0 S_NOP 0, implicit %0.sub3:sgpr_128
104118
; RPD-NEXT: 2 0
105119
; RPD-NEXT: Live-out: %0:00000000000000C3
120+
; RPD-NEXT: Live-thr: %0:00000000000000C0
121+
; RPD-NEXT: 1 0
106122
; RPD-NEXT: bb.2:
107123
; RPD-NEXT: Live-in: %0:00000000000000C3
108124
; RPD-NEXT: SGPR VGPR
109125
; RPD-NEXT: 2 0
110126
; RPD-NEXT: 2 0 S_NOP 0, implicit %0.sub3:sgpr_128, implicit %0.sub0:sgpr_128
111127
; RPD-NEXT: 0 0
112128
; RPD-NEXT: Live-out:
129+
; RPD-NEXT: Live-thr:
130+
; RPD-NEXT: 0 0
113131
bb.0:
114132
%0:sgpr_128 = IMPLICIT_DEF
115133
bb.1:
@@ -146,18 +164,24 @@ body: |
146164
; RP-NEXT: 0 2 undef %1.sub1:vreg_64 = V_MOV_B32_e32 33, implicit $exec
147165
; RP-NEXT: 0 2
148166
; RP-NEXT: Live-out: %0:0000000000000003 %1:000000000000000C
167+
; RP-NEXT: Live-thr:
168+
; RP-NEXT: 0 0
149169
; RP-NEXT: bb.1:
150170
; RP-NEXT: Live-in: %0:0000000000000003 %1:000000000000000C
151171
; RP-NEXT: SGPR VGPR
152172
; RP-NEXT: 0 2
153173
; RP-NEXT: Live-out: %0:0000000000000003 %1:000000000000000C
174+
; RP-NEXT: Live-thr: %0:0000000000000003 %1:000000000000000C
175+
; RP-NEXT: 0 2
154176
; RP-NEXT: bb.2:
155177
; RP-NEXT: Live-in: %0:0000000000000003 %1:000000000000000C
156178
; RP-NEXT: SGPR VGPR
157179
; RP-NEXT: 0 2
158180
; RP-NEXT: 0 2 S_NOP 0, implicit %0:vreg_64, implicit %1:vreg_64
159181
; RP-NEXT: 0 0
160182
; RP-NEXT: Live-out:
183+
; RP-NEXT: Live-thr:
184+
; RP-NEXT: 0 0
161185
bb.0:
162186
undef %0.sub0:vreg_64 = V_MOV_B32_e32 42, implicit $exec
163187
undef %1.sub1:vreg_64 = V_MOV_B32_e32 33, implicit $exec
@@ -247,6 +271,8 @@ body: |
247271
; RPU-NEXT: 0 5 GLOBAL_STORE_DWORD %15:vreg_64, %18:vgpr_32, 0, 0, implicit $exec
248272
; RPU-NEXT: 0 2
249273
; RPU-NEXT: Live-out: %0:0000000000000003 %16:0000000000000003
274+
; RPU-NEXT: Live-thr:
275+
; RPU-NEXT: 0 0
250276
; RPU-NEXT: bb.1:
251277
; RPU-NEXT: Live-in: %0:0000000000000003 %16:0000000000000003
252278
; RPU-NEXT: SGPR VGPR
@@ -260,11 +286,15 @@ body: |
260286
; RPU-NEXT: DBG_VALUE
261287
; RPU-NEXT: 0 2
262288
; RPU-NEXT: Live-out: %0:0000000000000003 %16:0000000000000003
289+
; RPU-NEXT: Live-thr: %0:0000000000000003 %16:0000000000000003
290+
; RPU-NEXT: 0 2
263291
; RPU-NEXT: bb.2:
264292
; RPU-NEXT: Live-in: %0:0000000000000003 %16:0000000000000003
265293
; RPU-NEXT: SGPR VGPR
266294
; RPU-NEXT: 0 2
267295
; RPU-NEXT: Live-out: %0:0000000000000003 %16:0000000000000003
296+
; RPU-NEXT: Live-thr: %0:0000000000000003 %16:0000000000000003
297+
; RPU-NEXT: 0 2
268298
; RPU-NEXT: bb.3:
269299
; RPU-NEXT: Live-in: %0:0000000000000003 %16:0000000000000003
270300
; RPU-NEXT: SGPR VGPR
@@ -276,6 +306,8 @@ body: |
276306
; RPU-NEXT: 0 0 S_ENDPGM 0
277307
; RPU-NEXT: 0 0
278308
; RPU-NEXT: Live-out:
309+
; RPU-NEXT: Live-thr:
310+
; RPU-NEXT: 0 0
279311
;
280312
; RPD-LABEL: name: only_dbg_value_sched_region
281313
; RPD: bb.0:
@@ -350,6 +382,8 @@ body: |
350382
; RPD-NEXT: 0 5 GLOBAL_STORE_DWORD %15:vreg_64, %18:vgpr_32, 0, 0, implicit $exec
351383
; RPD-NEXT: 0 2
352384
; RPD-NEXT: Live-out: %0:0000000000000003 %16:0000000000000003
385+
; RPD-NEXT: Live-thr:
386+
; RPD-NEXT: 0 0
353387
; RPD-NEXT: bb.1:
354388
; RPD-NEXT: Live-in: %0:0000000000000003 %16:0000000000000003
355389
; RPD-NEXT: SGPR VGPR
@@ -363,11 +397,15 @@ body: |
363397
; RPD-NEXT: DBG_VALUE
364398
; RPD-NEXT: 0 2
365399
; RPD-NEXT: Live-out: %0:0000000000000003 %16:0000000000000003
400+
; RPD-NEXT: Live-thr: %0:0000000000000003 %16:0000000000000003
401+
; RPD-NEXT: 0 2
366402
; RPD-NEXT: bb.2:
367403
; RPD-NEXT: Live-in: %0:0000000000000003 %16:0000000000000003
368404
; RPD-NEXT: SGPR VGPR
369405
; RPD-NEXT: 0 2
370406
; RPD-NEXT: Live-out: %0:0000000000000003 %16:0000000000000003
407+
; RPD-NEXT: Live-thr: %0:0000000000000003 %16:0000000000000003
408+
; RPD-NEXT: 0 2
371409
; RPD-NEXT: bb.3:
372410
; RPD-NEXT: Live-in: %0:0000000000000003 %16:0000000000000003
373411
; RPD-NEXT: SGPR VGPR
@@ -379,6 +417,8 @@ body: |
379417
; RPD-NEXT: 0 0 S_ENDPGM 0
380418
; RPD-NEXT: 0 0
381419
; RPD-NEXT: Live-out:
420+
; RPD-NEXT: Live-thr:
421+
; RPD-NEXT: 0 0
382422
bb.0:
383423
liveins: $vgpr0
384424
@@ -449,6 +489,8 @@ body: |
449489
; RP-NEXT: 0 1 S_NOP 0, implicit %1:vgpr_32
450490
; RP-NEXT: 0 0
451491
; RP-NEXT: Live-out:
492+
; RP-NEXT: Live-thr:
493+
; RP-NEXT: 0 0
452494
%0:vgpr_32 = V_MOV_B32_e32 42, implicit $exec
453495
early-clobber %1:vgpr_32 = V_MOV_B32_e32 %0, implicit $exec
454496
S_NOP 0, implicit %1
@@ -469,6 +511,8 @@ body: |
469511
; RPU-NEXT: 0 1 S_NOP 0, implicit %1:vgpr_32
470512
; RPU-NEXT: 0 0
471513
; RPU-NEXT: Live-out:
514+
; RPU-NEXT: Live-thr:
515+
; RPU-NEXT: 0 0
472516
;
473517
; RPD-LABEL: name: test_not_early_clobber_trivial
474518
; RPD: Live-in:
@@ -481,6 +525,8 @@ body: |
481525
; RPD-NEXT: 0 1 S_NOP 0, implicit %1:vgpr_32
482526
; RPD-NEXT: 0 0
483527
; RPD-NEXT: Live-out:
528+
; RPD-NEXT: Live-thr:
529+
; RPD-NEXT: 0 0
484530
%0:vgpr_32 = V_MOV_B32_e32 42, implicit $exec
485531
%1:vgpr_32 = V_MOV_B32_e32 %0, implicit $exec
486532
S_NOP 0, implicit %1

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