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[Mips] Fix compiler crash when returning fp128 after calling a functi… (#117525)
…on returning { i8, i128 } Fixes #96432.
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+323
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lines changed

‎llvm/include/llvm/CodeGen/TargetLowering.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -4781,7 +4781,7 @@ class TargetLowering : public TargetLoweringBase {
47814781
virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
47824782
MachineFunction &/*MF*/, bool /*isVarArg*/,
47834783
const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
4784-
LLVMContext &/*Context*/) const
4784+
LLVMContext &/*Context*/, const Type *RetTy) const
47854785
{
47864786
// Return true by default to get preexisting behavior.
47874787
return true;

‎llvm/lib/CodeGen/SelectionDAG/FastISel.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -1001,7 +1001,7 @@ bool FastISel::lowerCallTo(CallLoweringInfo &CLI) {
10011001
GetReturnInfo(CLI.CallConv, CLI.RetTy, getReturnAttrs(CLI), Outs, TLI, DL);
10021002

10031003
bool CanLowerReturn = TLI.CanLowerReturn(
1004-
CLI.CallConv, *FuncInfo.MF, CLI.IsVarArg, Outs, CLI.RetTy->getContext());
1004+
CLI.CallConv, *FuncInfo.MF, CLI.IsVarArg, Outs, CLI.RetTy->getContext(), CLI.RetTy);
10051005

10061006
// FIXME: sret demotion isn't supported yet - bail out.
10071007
if (!CanLowerReturn)

‎llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -99,7 +99,7 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
9999
GetReturnInfo(CC, Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI,
100100
mf.getDataLayout());
101101
CanLowerReturn =
102-
TLI->CanLowerReturn(CC, *MF, Fn->isVarArg(), Outs, Fn->getContext());
102+
TLI->CanLowerReturn(CC, *MF, Fn->isVarArg(), Outs, Fn->getContext(), Fn->getReturnType());
103103

104104
// If this personality uses funclets, we need to do a bit more work.
105105
DenseMap<const AllocaInst *, TinyPtrVector<int *>> CatchObjects;

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -11008,7 +11008,7 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
1100811008

1100911009
bool CanLowerReturn =
1101011010
this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
11011-
CLI.IsVarArg, Outs, CLI.RetTy->getContext());
11011+
CLI.IsVarArg, Outs, CLI.RetTy->getContext(), CLI.RetTy);
1101211012

1101311013
SDValue DemoteStackSlot;
1101411014
int DemoteStackIdx = -100;

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -9702,7 +9702,8 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
97029702

97039703
bool AArch64TargetLowering::CanLowerReturn(
97049704
CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
9705-
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
9705+
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
9706+
const Type *RetTy) const {
97069707
CCAssignFn *RetCC = CCAssignFnForReturn(CallConv);
97079708
SmallVector<CCValAssign, 16> RVLocs;
97089709
CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);

‎llvm/lib/Target/AArch64/AArch64ISelLowering.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1103,7 +1103,7 @@ class AArch64TargetLowering : public TargetLowering {
11031103
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
11041104
bool isVarArg,
11051105
const SmallVectorImpl<ISD::OutputArg> &Outs,
1106-
LLVMContext &Context) const override;
1106+
LLVMContext &Context, const Type *RetTy) const override;
11071107

11081108
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
11091109
const SmallVectorImpl<ISD::OutputArg> &Outs,

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -3157,7 +3157,8 @@ SDValue SITargetLowering::LowerFormalArguments(
31573157
// possible in registers before passing on stack.
31583158
bool SITargetLowering::CanLowerReturn(
31593159
CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
3160-
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
3160+
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
3161+
const Type *RetTy) const {
31613162
// Replacing returns with sret/stack usage doesn't make sense for shaders.
31623163
// FIXME: Also sort of a workaround for custom vector splitting in LowerReturn
31633164
// for shaders. Vector types should be explicitly handled by CC.

‎llvm/lib/Target/AMDGPU/SIISelLowering.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -392,7 +392,7 @@ class SITargetLowering final : public AMDGPUTargetLowering {
392392
bool CanLowerReturn(CallingConv::ID CallConv,
393393
MachineFunction &MF, bool isVarArg,
394394
const SmallVectorImpl<ISD::OutputArg> &Outs,
395-
LLVMContext &Context) const override;
395+
LLVMContext &Context, const Type *RetTy) const override;
396396

397397
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
398398
const SmallVectorImpl<ISD::OutputArg> &Outs,

‎llvm/lib/Target/ARC/ARCISelLowering.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -630,7 +630,8 @@ SDValue ARCTargetLowering::LowerCallArguments(
630630

631631
bool ARCTargetLowering::CanLowerReturn(
632632
CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
633-
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
633+
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
634+
const Type *RetTy) const {
634635
SmallVector<CCValAssign, 16> RVLocs;
635636
CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
636637
if (!CCInfo.CheckReturn(Outs, RetCC_ARC))

‎llvm/lib/Target/ARC/ARCISelLowering.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,7 @@ class ARCTargetLowering : public TargetLowering {
112112
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
113113
bool isVarArg,
114114
const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
115-
LLVMContext &Context) const override;
115+
LLVMContext &Context, const Type *RetTy) const override;
116116

117117
bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
118118
};

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -3241,7 +3241,7 @@ bool
32413241
ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
32423242
MachineFunction &MF, bool isVarArg,
32433243
const SmallVectorImpl<ISD::OutputArg> &Outs,
3244-
LLVMContext &Context) const {
3244+
LLVMContext &Context, const Type *RetTy) const {
32453245
SmallVector<CCValAssign, 16> RVLocs;
32463246
CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
32473247
return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));

‎llvm/lib/Target/ARM/ARMISelLowering.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -965,7 +965,7 @@ class VectorType;
965965
bool CanLowerReturn(CallingConv::ID CallConv,
966966
MachineFunction &MF, bool isVarArg,
967967
const SmallVectorImpl<ISD::OutputArg> &Outs,
968-
LLVMContext &Context) const override;
968+
LLVMContext &Context, const Type *RetTy) const override;
969969

970970
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
971971
const SmallVectorImpl<ISD::OutputArg> &Outs,

‎llvm/lib/Target/AVR/AVRISelLowering.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -1670,7 +1670,8 @@ SDValue AVRTargetLowering::LowerCallResult(
16701670

16711671
bool AVRTargetLowering::CanLowerReturn(
16721672
CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
1673-
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
1673+
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
1674+
const Type *RetTy) const {
16741675
if (CallConv == CallingConv::AVR_BUILTIN) {
16751676
SmallVector<CCValAssign, 16> RVLocs;
16761677
CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);

‎llvm/lib/Target/AVR/AVRISelLowering.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -172,7 +172,7 @@ class AVRTargetLowering : public TargetLowering {
172172
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
173173
bool isVarArg,
174174
const SmallVectorImpl<ISD::OutputArg> &Outs,
175-
LLVMContext &Context) const override;
175+
LLVMContext &Context, const Type *RetTy) const override;
176176

177177
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
178178
const SmallVectorImpl<ISD::OutputArg> &Outs,

‎llvm/lib/Target/CSKY/CSKYISelLowering.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -426,7 +426,8 @@ SDValue CSKYTargetLowering::LowerFormalArguments(
426426

427427
bool CSKYTargetLowering::CanLowerReturn(
428428
CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
429-
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
429+
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
430+
const Type *RetTy) const {
430431
SmallVector<CCValAssign, 16> CSKYLocs;
431432
CCState CCInfo(CallConv, IsVarArg, MF, CSKYLocs, Context);
432433
return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg));

‎llvm/lib/Target/CSKY/CSKYISelLowering.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ class CSKYTargetLowering : public TargetLowering {
6161
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
6262
bool IsVarArg,
6363
const SmallVectorImpl<ISD::OutputArg> &Outs,
64-
LLVMContext &Context) const override;
64+
LLVMContext &Context, const Type *RetTy) const override;
6565

6666
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
6767
const SmallVectorImpl<ISD::OutputArg> &Outs,

‎llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -182,7 +182,7 @@ bool
182182
HexagonTargetLowering::CanLowerReturn(
183183
CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
184184
const SmallVectorImpl<ISD::OutputArg> &Outs,
185-
LLVMContext &Context) const {
185+
LLVMContext &Context, const Type *RetTy) const {
186186
SmallVector<CCValAssign, 16> RVLocs;
187187
CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
188188

‎llvm/lib/Target/Hexagon/HexagonISelLowering.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -249,7 +249,7 @@ class HexagonTargetLowering : public TargetLowering {
249249
bool CanLowerReturn(CallingConv::ID CallConv,
250250
MachineFunction &MF, bool isVarArg,
251251
const SmallVectorImpl<ISD::OutputArg> &Outs,
252-
LLVMContext &Context) const override;
252+
LLVMContext &Context, const Type *RetTy) const override;
253253

254254
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
255255
const SmallVectorImpl<ISD::OutputArg> &Outs,

‎llvm/lib/Target/Lanai/LanaiISelLowering.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -527,7 +527,8 @@ SDValue LanaiTargetLowering::LowerCCCArguments(
527527

528528
bool LanaiTargetLowering::CanLowerReturn(
529529
CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
530-
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
530+
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
531+
const Type *RetTy) const {
531532
SmallVector<CCValAssign, 16> RVLocs;
532533
CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
533534

‎llvm/lib/Target/Lanai/LanaiISelLowering.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,7 @@ class LanaiTargetLowering : public TargetLowering {
9393
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
9494
bool IsVarArg,
9595
const SmallVectorImpl<ISD::OutputArg> &Outs,
96-
LLVMContext &Context) const override;
96+
LLVMContext &Context, const Type *RetTy) const override;
9797

9898
Register getRegisterByName(const char *RegName, LLT VT,
9999
const MachineFunction &MF) const override;

‎llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -5677,7 +5677,8 @@ LoongArchTargetLowering::LowerCall(CallLoweringInfo &CLI,
56775677

56785678
bool LoongArchTargetLowering::CanLowerReturn(
56795679
CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
5680-
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
5680+
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
5681+
const Type *RetTy) const {
56815682
SmallVector<CCValAssign> RVLocs;
56825683
CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
56835684

‎llvm/lib/Target/LoongArch/LoongArchISelLowering.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -183,7 +183,7 @@ class LoongArchTargetLowering : public TargetLowering {
183183
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
184184
bool IsVarArg,
185185
const SmallVectorImpl<ISD::OutputArg> &Outs,
186-
LLVMContext &Context) const override;
186+
LLVMContext &Context, const Type *RetTy) const override;
187187
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
188188
const SmallVectorImpl<ISD::OutputArg> &Outs,
189189
const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,

‎llvm/lib/Target/M68k/M68kISelLowering.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -1060,7 +1060,8 @@ SDValue M68kTargetLowering::LowerFormalArguments(
10601060

10611061
bool M68kTargetLowering::CanLowerReturn(
10621062
CallingConv::ID CCID, MachineFunction &MF, bool IsVarArg,
1063-
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
1063+
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
1064+
const Type *RetTy) const {
10641065
SmallVector<CCValAssign, 16> RVLocs;
10651066
CCState CCInfo(CCID, IsVarArg, MF, RVLocs, Context);
10661067
return CCInfo.CheckReturn(Outs, RetCC_M68k);

‎llvm/lib/Target/M68k/M68kISelLowering.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -271,7 +271,7 @@ class M68kTargetLowering : public TargetLowering {
271271
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
272272
bool isVarArg,
273273
const SmallVectorImpl<ISD::OutputArg> &Outs,
274-
LLVMContext &Context) const override;
274+
LLVMContext &Context, const Type *RetTy) const override;
275275

276276
/// Lower the result values of a call into the
277277
/// appropriate copies out of appropriate physical registers.

‎llvm/lib/Target/MSP430/MSP430ISelLowering.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -723,7 +723,8 @@ MSP430TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
723723
MachineFunction &MF,
724724
bool IsVarArg,
725725
const SmallVectorImpl<ISD::OutputArg> &Outs,
726-
LLVMContext &Context) const {
726+
LLVMContext &Context,
727+
const Type *RetTy) const {
727728
SmallVector<CCValAssign, 16> RVLocs;
728729
CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
729730
return CCInfo.CheckReturn(Outs, RetCC_MSP430);

‎llvm/lib/Target/MSP430/MSP430ISelLowering.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -171,7 +171,7 @@ namespace llvm {
171171
MachineFunction &MF,
172172
bool IsVarArg,
173173
const SmallVectorImpl<ISD::OutputArg> &Outs,
174-
LLVMContext &Context) const override;
174+
LLVMContext &Context, const Type *RetTy) const override;
175175

176176
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
177177
const SmallVectorImpl<ISD::OutputArg> &Outs,

‎llvm/lib/Target/Mips/MipsCCState.cpp

+4-5
Original file line numberDiff line numberDiff line change
@@ -95,14 +95,13 @@ void MipsCCState::PreAnalyzeCallResultForF128(
9595

9696
/// Identify lowered values that originated from f128 or float arguments and
9797
/// record this for use by RetCC_MipsN.
98-
void MipsCCState::PreAnalyzeReturnForF128(
99-
const SmallVectorImpl<ISD::OutputArg> &Outs) {
100-
const MachineFunction &MF = getMachineFunction();
98+
void MipsCCState::PreAnalyzeCallReturnForF128(
99+
const SmallVectorImpl<ISD::OutputArg> &Outs, const Type *RetTy) {
101100
for (unsigned i = 0; i < Outs.size(); ++i) {
102101
OriginalArgWasF128.push_back(
103-
originalTypeIsF128(MF.getFunction().getReturnType(), nullptr));
102+
originalTypeIsF128(RetTy, nullptr));
104103
OriginalArgWasFloat.push_back(
105-
MF.getFunction().getReturnType()->isFloatingPointTy());
104+
RetTy->isFloatingPointTy());
106105
}
107106
}
108107

‎llvm/lib/Target/Mips/MipsCCState.h

+15-3
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@ class MipsCCState : public CCState {
4949

5050
/// Identify lowered values that originated from f128 arguments and record
5151
/// this for use by RetCC_MipsN.
52-
void PreAnalyzeReturnForF128(const SmallVectorImpl<ISD::OutputArg> &Outs);
52+
void PreAnalyzeCallReturnForF128(const SmallVectorImpl<ISD::OutputArg> &Outs, const Type *RetTy);
5353

5454
/// Identify lowered values that originated from f128 arguments and record
5555
/// this.
@@ -167,10 +167,11 @@ class MipsCCState : public CCState {
167167

168168
void PreAnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
169169
CCAssignFn Fn) {
170+
const MachineFunction &MF = getMachineFunction();
170171
OriginalArgWasFloat.clear();
171172
OriginalArgWasF128.clear();
172173
OriginalArgWasFloatVector.clear();
173-
PreAnalyzeReturnForF128(Outs);
174+
PreAnalyzeCallReturnForF128(Outs, MF.getFunction().getReturnType());
174175
PreAnalyzeReturnForVectorFloat(Outs);
175176
}
176177

@@ -182,7 +183,8 @@ class MipsCCState : public CCState {
182183

183184
bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
184185
CCAssignFn Fn) {
185-
PreAnalyzeReturnForF128(ArgsFlags);
186+
const MachineFunction &MF = getMachineFunction();
187+
PreAnalyzeCallReturnForF128(ArgsFlags, MF.getFunction().getReturnType());
186188
PreAnalyzeReturnForVectorFloat(ArgsFlags);
187189
bool Return = CCState::CheckReturn(ArgsFlags, Fn);
188190
OriginalArgWasFloat.clear();
@@ -191,6 +193,16 @@ class MipsCCState : public CCState {
191193
return Return;
192194
}
193195

196+
bool CheckCallReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
197+
CCAssignFn Fn, const Type *RetTy) {
198+
PreAnalyzeCallReturnForF128(ArgsFlags, RetTy);
199+
PreAnalyzeReturnForVectorFloat(ArgsFlags);
200+
bool Return = CCState::CheckReturn(ArgsFlags, Fn);
201+
OriginalArgWasFloat.clear();
202+
OriginalArgWasF128.clear();
203+
OriginalArgWasFloatVector.clear();
204+
return Return;
205+
}
194206
bool WasOriginalArgF128(unsigned ValNo) { return OriginalArgWasF128[ValNo]; }
195207
bool WasOriginalArgFloat(unsigned ValNo) {
196208
return OriginalArgWasFloat[ValNo];

‎llvm/lib/Target/Mips/MipsISelLowering.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -3864,10 +3864,10 @@ bool
38643864
MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
38653865
MachineFunction &MF, bool IsVarArg,
38663866
const SmallVectorImpl<ISD::OutputArg> &Outs,
3867-
LLVMContext &Context) const {
3867+
LLVMContext &Context, const Type *RetTy) const {
38683868
SmallVector<CCValAssign, 16> RVLocs;
38693869
MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3870-
return CCInfo.CheckReturn(Outs, RetCC_Mips);
3870+
return CCInfo.CheckCallReturn(Outs, RetCC_Mips, RetTy);
38713871
}
38723872

38733873
bool MipsTargetLowering::shouldSignExtendTypeInLibCall(Type *Ty,

‎llvm/lib/Target/Mips/MipsISelLowering.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -615,7 +615,7 @@ class TargetRegisterClass;
615615
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
616616
bool isVarArg,
617617
const SmallVectorImpl<ISD::OutputArg> &Outs,
618-
LLVMContext &Context) const override;
618+
LLVMContext &Context, const Type *RetTy) const override;
619619

620620
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
621621
const SmallVectorImpl<ISD::OutputArg> &Outs,

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -7868,7 +7868,8 @@ bool
78687868
PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
78697869
MachineFunction &MF, bool isVarArg,
78707870
const SmallVectorImpl<ISD::OutputArg> &Outs,
7871-
LLVMContext &Context) const {
7871+
LLVMContext &Context,
7872+
const Type *RetTy) const {
78727873
SmallVector<CCValAssign, 16> RVLocs;
78737874
CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
78747875
return CCInfo.CheckReturn(

‎llvm/lib/Target/PowerPC/PPCISelLowering.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1373,7 +1373,7 @@ namespace llvm {
13731373
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
13741374
bool isVarArg,
13751375
const SmallVectorImpl<ISD::OutputArg> &Outs,
1376-
LLVMContext &Context) const override;
1376+
LLVMContext &Context, const Type *RetTy) const override;
13771377

13781378
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
13791379
const SmallVectorImpl<ISD::OutputArg> &Outs,

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -20609,7 +20609,8 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
2060920609

2061020610
bool RISCVTargetLowering::CanLowerReturn(
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CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
20612-
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
20612+
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
20613+
const Type *RetTy) const {
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
2061520616

‎llvm/lib/Target/RISCV/RISCVISelLowering.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -766,7 +766,7 @@ class RISCVTargetLowering : public TargetLowering {
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bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
769-
LLVMContext &Context) const override;
769+
LLVMContext &Context, const Type *RetTy) const override;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,

‎llvm/lib/Target/Sparc/SparcISelLowering.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -234,7 +234,8 @@ static unsigned toCallerWindow(unsigned Reg) {
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bool SparcTargetLowering::CanLowerReturn(
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CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
237-
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
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const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
238+
const Type *RetTy) const {
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
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return CCInfo.CheckReturn(Outs, Subtarget->is64Bit() ? RetCC_Sparc64

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