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[TableGen] Fix minor index bugs in PseudoLoweringEmitter
This commit fixes some minor indices bugs in PseudoLoweringEmitter.cpp. I don't believe these bugs would have had much of an effect previously but they were causing some issues with some refactoring work with ".w" and ".n" operands I am working on currently.
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-17
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1 file changed

+20
-17
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llvm/utils/TableGen/PseudoLoweringEmitter.cpp

Lines changed: 20 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -76,8 +76,8 @@ unsigned PseudoLoweringEmitter::addDagOperandMapping(
7676
unsigned OpsAdded = 0;
7777
for (unsigned i = 0, e = Dag->getNumArgs(); i != e; ++i) {
7878
if (DefInit *DI = dyn_cast<DefInit>(Dag->getArg(i))) {
79-
// Physical register reference. Explicit check for the special case
80-
// "zero_reg" definition.
79+
// Physical register reference.
80+
// Explicit check for the special case "zero_reg" definition.
8181
if (DI->getDef()->isSubClassOf("Register") ||
8282
DI->getDef()->getName() == "zero_reg") {
8383
OperandMap[BaseIdx + i].Kind = OpData::Reg;
@@ -88,23 +88,26 @@ unsigned PseudoLoweringEmitter::addDagOperandMapping(
8888

8989
// Normal operands should always have the same type, or we have a
9090
// problem.
91-
// FIXME: We probably shouldn't ever get a non-zero BaseIdx here.
92-
assert(BaseIdx == 0 && "Named subargument in pseudo expansion?!");
91+
9392
// FIXME: Are the message operand types backward?
94-
if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) {
93+
if (DI->getDef() != Insn.Operands[i].Rec) {
9594
PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
9695
"', operand type '" + DI->getDef()->getName() +
9796
"' does not match expansion operand type '" +
98-
Insn.Operands[BaseIdx + i].Rec->getName() + "'");
97+
Insn.Operands[i].Rec->getName() + "'");
9998
PrintFatalNote(DI->getDef(),
10099
"Value was assigned at the following location:");
101100
}
102101
// Source operand maps to destination operand. The Data element
103102
// will be filled in later, just set the Kind for now. Do it
104103
// for each corresponding MachineInstr operand, not just the first.
105-
for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
104+
for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I) {
106105
OperandMap[BaseIdx + i + I].Kind = OpData::Operand;
106+
}
107107
OpsAdded += Insn.Operands[i].MINumOperands;
108+
if (Insn.Operands[i].MINumOperands > 0)
109+
BaseIdx += Insn.Operands[i].MINumOperands - 1;
110+
108111
} else if (IntInit *II = dyn_cast<IntInit>(Dag->getArg(i))) {
109112
OperandMap[BaseIdx + i].Kind = OpData::Imm;
110113
OperandMap[BaseIdx + i].Data.Imm = II->getValue();
@@ -164,21 +167,21 @@ void PseudoLoweringEmitter::evaluateExpansion(Record *Rec) {
164167
"Result was assigned at the following location:");
165168
}
166169

167-
if (Insn.Operands.size() != Dag->getNumArgs()) {
168-
PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
169-
"', result operator '" + Operator->getName() +
170-
"' has the wrong number of operands");
171-
PrintFatalNote(Rec->getValue("ResultInst"),
172-
"Result was assigned at the following location:");
173-
}
174-
175170
unsigned NumMIOperands = 0;
176171
for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i)
177172
NumMIOperands += Insn.Operands[i].MINumOperands;
178173
IndexedMap<OpData> OperandMap;
179174
OperandMap.grow(NumMIOperands);
180175

181-
addDagOperandMapping(Rec, Dag, Insn, OperandMap, 0);
176+
unsigned NumOps = addDagOperandMapping(Rec, Dag, Insn, OperandMap, 0);
177+
178+
if (NumOps < Dag->getNumArgs()) {
179+
PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
180+
"', result operator '" + Operator->getName() +
181+
"' has the wrong number of operands");
182+
PrintFatalNote(Rec->getValue("ResultInst"),
183+
"Result was assigned at the following location:");
184+
}
182185

183186
// If there are more operands that weren't in the DAG, they have to
184187
// be operands that have default values, or we have an error. Currently,
@@ -196,7 +199,7 @@ void PseudoLoweringEmitter::evaluateExpansion(Record *Rec) {
196199
SourceOperands[SourceInsn.Operands[i].Name] = i;
197200

198201
LLVM_DEBUG(dbgs() << " Operand mapping:\n");
199-
for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i) {
202+
for (unsigned i = 0, e = Dag->getNumArgs(); i != e; ++i) {
200203
// We've already handled constant values. Just map instruction operands
201204
// here.
202205
if (OperandMap[Insn.Operands[i].MIOperandNo].Kind != OpData::Operand)

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