@@ -103,6 +103,12 @@ RISCVRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
103
103
}
104
104
}
105
105
106
+ static const RegisterBankInfo::ValueMapping *getFPValueMapping (unsigned Size) {
107
+ assert (Size == 32 || Size == 64 );
108
+ unsigned Idx = Size == 64 ? RISCV::FPR64Idx : RISCV::FPR32Idx;
109
+ return &RISCV::ValueMappings[Idx];
110
+ }
111
+
106
112
const RegisterBankInfo::InstructionMapping &
107
113
RISCVRegisterBankInfo::getInstrMapping (const MachineInstr &MI) const {
108
114
const unsigned Opc = MI.getOpcode ();
@@ -185,47 +191,26 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
185
191
case TargetOpcode::G_FMAXNUM:
186
192
case TargetOpcode::G_FMINNUM: {
187
193
LLT Ty = MRI.getType (MI.getOperand (0 ).getReg ());
188
- OperandsMapping = Ty.getSizeInBits () == 64
189
- ? &RISCV::ValueMappings[RISCV::FPR64Idx]
190
- : &RISCV::ValueMappings[RISCV::FPR32Idx];
194
+ OperandsMapping = getFPValueMapping (Ty.getSizeInBits ());
191
195
break ;
192
196
}
193
197
case TargetOpcode::G_FMA: {
194
198
LLT Ty = MRI.getType (MI.getOperand (0 ).getReg ());
195
- OperandsMapping =
196
- Ty.getSizeInBits () == 64
197
- ? getOperandsMapping ({&RISCV::ValueMappings[RISCV::FPR64Idx],
198
- &RISCV::ValueMappings[RISCV::FPR64Idx],
199
- &RISCV::ValueMappings[RISCV::FPR64Idx],
200
- &RISCV::ValueMappings[RISCV::FPR64Idx]})
201
- : getOperandsMapping ({&RISCV::ValueMappings[RISCV::FPR32Idx],
202
- &RISCV::ValueMappings[RISCV::FPR32Idx],
203
- &RISCV::ValueMappings[RISCV::FPR32Idx],
204
- &RISCV::ValueMappings[RISCV::FPR32Idx]});
205
- break ;
206
- }
207
- case TargetOpcode::G_FPEXT: {
208
- LLT ToTy = MRI.getType (MI.getOperand (0 ).getReg ());
209
- (void )ToTy;
210
- LLT FromTy = MRI.getType (MI.getOperand (1 ).getReg ());
211
- (void )FromTy;
212
- assert (ToTy.getSizeInBits () == 64 && FromTy.getSizeInBits () == 32 &&
213
- " Unsupported size for G_FPEXT" );
214
- OperandsMapping =
215
- getOperandsMapping ({&RISCV::ValueMappings[RISCV::FPR64Idx],
216
- &RISCV::ValueMappings[RISCV::FPR32Idx]});
199
+ const RegisterBankInfo::ValueMapping *FPValueMapping =
200
+ getFPValueMapping (Ty.getSizeInBits ());
201
+ OperandsMapping = getOperandsMapping (
202
+ {FPValueMapping, FPValueMapping, FPValueMapping, FPValueMapping});
217
203
break ;
218
204
}
205
+ case TargetOpcode::G_FPEXT:
219
206
case TargetOpcode::G_FPTRUNC: {
220
207
LLT ToTy = MRI.getType (MI.getOperand (0 ).getReg ());
221
208
(void )ToTy;
222
209
LLT FromTy = MRI.getType (MI.getOperand (1 ).getReg ());
223
210
(void )FromTy;
224
- assert (ToTy.getSizeInBits () == 32 && FromTy.getSizeInBits () == 64 &&
225
- " Unsupported size for G_FPTRUNC" );
226
211
OperandsMapping =
227
- getOperandsMapping ({&RISCV::ValueMappings[RISCV::FPR32Idx] ,
228
- &RISCV::ValueMappings[RISCV::FPR64Idx] });
212
+ getOperandsMapping ({getFPValueMapping (ToTy. getSizeInBits ()) ,
213
+ getFPValueMapping (FromTy. getSizeInBits ()) });
229
214
break ;
230
215
}
231
216
default :
0 commit comments