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[AVR] Force relocations for non-encodable jumps (#121498)
This commit changes the branch emission logic so that instead of throwing the "branch target out of range" error, we emit a relocation instead.
1 parent dd42651 commit 814b34f

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24 files changed

+75
-50
lines changed

24 files changed

+75
-50
lines changed

‎llvm/include/llvm/MC/MCAsmBackend.h

+1
Original file line numberDiff line numberDiff line change
@@ -96,6 +96,7 @@ class MCAsmBackend {
9696
virtual bool shouldForceRelocation(const MCAssembler &Asm,
9797
const MCFixup &Fixup,
9898
const MCValue &Target,
99+
const uint64_t Value,
99100
const MCSubtargetInfo *STI) {
100101
return false;
101102
}

‎llvm/lib/MC/MCAssembler.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -222,7 +222,7 @@ bool MCAssembler::evaluateFixup(const MCFixup &Fixup, const MCFragment *DF,
222222

223223
// Let the backend force a relocation if needed.
224224
if (IsResolved &&
225-
getBackend().shouldForceRelocation(*this, Fixup, Target, STI)) {
225+
getBackend().shouldForceRelocation(*this, Fixup, Target, Value, STI)) {
226226
IsResolved = false;
227227
WasForced = true;
228228
}

‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -98,7 +98,7 @@ class AArch64AsmBackend : public MCAsmBackend {
9898
unsigned getFixupKindContainereSizeInBytes(unsigned Kind) const;
9999

100100
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
101-
const MCValue &Target,
101+
const MCValue &Target, const uint64_t Value,
102102
const MCSubtargetInfo *STI) override;
103103
};
104104

@@ -520,6 +520,7 @@ bool AArch64AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
520520
bool AArch64AsmBackend::shouldForceRelocation(const MCAssembler &Asm,
521521
const MCFixup &Fixup,
522522
const MCValue &Target,
523+
const uint64_t,
523524
const MCSubtargetInfo *STI) {
524525
unsigned Kind = Fixup.getKind();
525526
if (Kind >= FirstLiteralRelocationKind)

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ class AMDGPUAsmBackend : public MCAsmBackend {
5353
std::optional<MCFixupKind> getFixupKind(StringRef Name) const override;
5454
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
5555
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
56-
const MCValue &Target,
56+
const MCValue &Target, uint64_t Value,
5757
const MCSubtargetInfo *STI) override;
5858
};
5959

@@ -196,7 +196,7 @@ const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo(
196196

197197
bool AMDGPUAsmBackend::shouldForceRelocation(const MCAssembler &,
198198
const MCFixup &Fixup,
199-
const MCValue &,
199+
const MCValue &, const uint64_t,
200200
const MCSubtargetInfo *STI) {
201201
return Fixup.getKind() >= FirstLiteralRelocationKind;
202202
}

‎llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -955,7 +955,7 @@ unsigned ARMAsmBackend::adjustFixupValue(const MCAssembler &Asm,
955955

956956
bool ARMAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
957957
const MCFixup &Fixup,
958-
const MCValue &Target,
958+
const MCValue &Target, const uint64_t,
959959
const MCSubtargetInfo *STI) {
960960
const MCSymbolRefExpr *A = Target.getSymA();
961961
const MCSymbol *Sym = A ? &A->getSymbol() : nullptr;

‎llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ class ARMAsmBackend : public MCAsmBackend {
3636
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
3737

3838
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
39-
const MCValue &Target,
39+
const MCValue &Target, const uint64_t Value,
4040
const MCSubtargetInfo *STI) override;
4141

4242
unsigned adjustFixupValue(const MCAssembler &Asm, const MCFixup &Fixup,

‎llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp

+31-27
Original file line numberDiff line numberDiff line change
@@ -31,22 +31,6 @@ namespace adjust {
3131

3232
using namespace llvm;
3333

34-
static void signed_width(unsigned Width, uint64_t Value,
35-
std::string Description, const MCFixup &Fixup,
36-
MCContext *Ctx) {
37-
if (!isIntN(Width, Value)) {
38-
std::string Diagnostic = "out of range " + Description;
39-
40-
int64_t Min = minIntN(Width);
41-
int64_t Max = maxIntN(Width);
42-
43-
Diagnostic += " (expected an integer in the range " + std::to_string(Min) +
44-
" to " + std::to_string(Max) + ")";
45-
46-
Ctx->reportError(Fixup.getLoc(), Diagnostic);
47-
}
48-
}
49-
5034
static void unsigned_width(unsigned Width, uint64_t Value,
5135
std::string Description, const MCFixup &Fixup,
5236
MCContext *Ctx) {
@@ -74,17 +58,18 @@ static void adjustBranch(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
7458
}
7559

7660
/// Adjusts the value of a relative branch target before fixup application.
77-
static void adjustRelativeBranch(unsigned Size, const MCFixup &Fixup,
78-
uint64_t &Value, MCContext *Ctx) {
61+
static bool adjustRelativeBranch(unsigned Size, const MCFixup &Fixup,
62+
uint64_t &Value, const MCSubtargetInfo *STI) {
7963
// Jumps are relative to the current instruction.
8064
Value -= 2;
8165

8266
// We have one extra bit of precision because the value is rightshifted by
8367
// one.
8468
Size += 1;
8569

86-
if (!isIntN(Size, Value) &&
87-
Ctx->getSubtargetInfo()->hasFeature(AVR::FeatureWrappingRjmp)) {
70+
assert(STI && "STI can not be NULL");
71+
72+
if (!isIntN(Size, Value) && STI->hasFeature(AVR::FeatureWrappingRjmp)) {
8873
const int32_t FlashSize = 0x2000;
8974
int32_t SignedValue = Value;
9075

@@ -96,10 +81,14 @@ static void adjustRelativeBranch(unsigned Size, const MCFixup &Fixup,
9681
}
9782
}
9883

99-
signed_width(Size, Value, std::string("branch target"), Fixup, Ctx);
84+
if (!isIntN(Size, Value)) {
85+
return false;
86+
}
10087

10188
// Rightshifts the value by one.
10289
AVR::fixups::adjustBranchTarget(Value);
90+
91+
return true;
10392
}
10493

10594
/// 22-bit absolute fixup.
@@ -126,7 +115,9 @@ static void fixup_call(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
126115
/// Offset of 0 (so the result is left shifted by 3 bits before application).
127116
static void fixup_7_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
128117
MCContext *Ctx) {
129-
adjustRelativeBranch(Size, Fixup, Value, Ctx);
118+
if (!adjustRelativeBranch(Size, Fixup, Value, Ctx->getSubtargetInfo())) {
119+
llvm_unreachable("should've been emitted as a relocation");
120+
}
130121

131122
// Because the value may be negative, we must mask out the sign bits
132123
Value &= 0x7f;
@@ -140,7 +131,9 @@ static void fixup_7_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
140131
/// Offset of 0 (so the result isn't left-shifted before application).
141132
static void fixup_13_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
142133
MCContext *Ctx) {
143-
adjustRelativeBranch(Size, Fixup, Value, Ctx);
134+
if (!adjustRelativeBranch(Size, Fixup, Value, Ctx->getSubtargetInfo())) {
135+
llvm_unreachable("should've been emitted as a relocation");
136+
}
144137

145138
// Because the value may be negative, we must mask out the sign bits
146139
Value &= 0xfff;
@@ -181,7 +174,7 @@ static void fixup_port5(const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx) {
181174
Value <<= 3;
182175
}
183176

184-
/// 6-bit port number fixup on the `IN` family of instructions.
177+
/// 6-bit port number fixup on the IN family of instructions.
185178
///
186179
/// Resolves to:
187180
/// 1011 0AAd dddd AAAA
@@ -512,14 +505,25 @@ bool AVRAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
512505
bool AVRAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
513506
const MCFixup &Fixup,
514507
const MCValue &Target,
508+
const uint64_t Value,
515509
const MCSubtargetInfo *STI) {
516510
switch ((unsigned)Fixup.getKind()) {
517511
default:
518512
return Fixup.getKind() >= FirstLiteralRelocationKind;
513+
519514
case AVR::fixup_7_pcrel:
520-
case AVR::fixup_13_pcrel:
521-
// Always resolve relocations for PC-relative branches
522-
return false;
515+
case AVR::fixup_13_pcrel: {
516+
uint64_t ValueEx = Value;
517+
uint64_t Size = AVRAsmBackend::getFixupKindInfo(Fixup.getKind()).TargetSize;
518+
519+
// If the jump is too large to encode it, fall back to a relocation.
520+
//
521+
// Note that trying to actually link that relocation *would* fail, but the
522+
// hopes are that the module we're currently compiling won't be actually
523+
// linked to the final binary.
524+
return !adjust::adjustRelativeBranch(Size, Fixup, ValueEx, STI);
525+
}
526+
523527
case AVR::fixup_call:
524528
return true;
525529
}

‎llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ class AVRAsmBackend : public MCAsmBackend {
5353
const MCSubtargetInfo *STI) const override;
5454

5555
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
56-
const MCValue &Target,
56+
const MCValue &Target, const uint64_t Value,
5757
const MCSubtargetInfo *STI) override;
5858

5959
private:

‎llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp

+1
Original file line numberDiff line numberDiff line change
@@ -262,6 +262,7 @@ bool CSKYAsmBackend::mayNeedRelaxation(const MCInst &Inst,
262262
bool CSKYAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
263263
const MCFixup &Fixup,
264264
const MCValue &Target,
265+
const uint64_t /*Value*/,
265266
const MCSubtargetInfo * /*STI*/) {
266267
if (Fixup.getKind() >= FirstLiteralRelocationKind)
267268
return true;

‎llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,7 @@ class CSKYAsmBackend : public MCAsmBackend {
5252
const MCSubtargetInfo *STI) const override;
5353

5454
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
55-
const MCValue &Target,
55+
const MCValue &Target, const uint64_t Value,
5656
const MCSubtargetInfo *STI) override;
5757

5858
std::unique_ptr<MCObjectTargetWriter>

‎llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -201,7 +201,7 @@ class HexagonAsmBackend : public MCAsmBackend {
201201
}
202202

203203
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
204-
const MCValue &Target,
204+
const MCValue &Target, const uint64_t,
205205
const MCSubtargetInfo *STI) override {
206206
switch(Fixup.getTargetKind()) {
207207
default:

‎llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp

+1
Original file line numberDiff line numberDiff line change
@@ -251,6 +251,7 @@ bool LoongArchAsmBackend::shouldInsertFixupForCodeAlign(MCAssembler &Asm,
251251
bool LoongArchAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
252252
const MCFixup &Fixup,
253253
const MCValue &Target,
254+
const uint64_t,
254255
const MCSubtargetInfo *STI) {
255256
if (Fixup.getKind() >= FirstLiteralRelocationKind)
256257
return true;

‎llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ class LoongArchAsmBackend : public MCAsmBackend {
5757
MCAlignFragment &AF) override;
5858

5959
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
60-
const MCValue &Target,
60+
const MCValue &Target, const uint64_t Value,
6161
const MCSubtargetInfo *STI) override;
6262

6363
unsigned getNumFixupKinds() const override {

‎llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

+1
Original file line numberDiff line numberDiff line change
@@ -542,6 +542,7 @@ bool MipsAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
542542
bool MipsAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
543543
const MCFixup &Fixup,
544544
const MCValue &Target,
545+
const uint64_t,
545546
const MCSubtargetInfo *STI) {
546547
if (Fixup.getKind() >= FirstLiteralRelocationKind)
547548
return true;

‎llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,7 @@ class MipsAsmBackend : public MCAsmBackend {
5555
const MCSubtargetInfo *STI) const override;
5656

5757
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
58-
const MCValue &Target,
58+
const MCValue &Target, const uint64_t Value,
5959
const MCSubtargetInfo *STI) override;
6060

6161
bool isMicroMips(const MCSymbol *Sym) const override;

‎llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -161,7 +161,7 @@ class PPCAsmBackend : public MCAsmBackend {
161161
}
162162

163163
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
164-
const MCValue &Target,
164+
const MCValue &Target, const uint64_t,
165165
const MCSubtargetInfo *STI) override {
166166
MCFixupKind Kind = Fixup.getKind();
167167
switch ((unsigned)Kind) {

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -115,6 +115,7 @@ RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
115115
bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
116116
const MCFixup &Fixup,
117117
const MCValue &Target,
118+
const uint64_t,
118119
const MCSubtargetInfo *STI) {
119120
if (Fixup.getKind() >= FirstLiteralRelocationKind)
120121
return true;
@@ -570,7 +571,7 @@ bool RISCVAsmBackend::evaluateTargetFixup(const MCAssembler &Asm,
570571
Value = Asm.getSymbolOffset(SA) + AUIPCTarget.getConstant();
571572
Value -= Asm.getFragmentOffset(*AUIPCDF) + AUIPCFixup->getOffset();
572573

573-
if (shouldForceRelocation(Asm, *AUIPCFixup, AUIPCTarget, STI)) {
574+
if (shouldForceRelocation(Asm, *AUIPCFixup, AUIPCTarget, Value, STI)) {
574575
WasForced = true;
575576
return false;
576577
}

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,7 @@ class RISCVAsmBackend : public MCAsmBackend {
6565
createObjectTargetWriter() const override;
6666

6767
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
68-
const MCValue &Target,
68+
const MCValue &Target, const uint64_t Value,
6969
const MCSubtargetInfo *STI) override;
7070

7171
bool fixupNeedsRelaxationAdvanced(const MCAssembler &Asm,

‎llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -273,7 +273,7 @@ namespace {
273273
}
274274

275275
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
276-
const MCValue &Target,
276+
const MCValue &Target, const uint64_t,
277277
const MCSubtargetInfo *STI) override {
278278
if (Fixup.getKind() >= FirstLiteralRelocationKind)
279279
return true;

‎llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -116,7 +116,7 @@ class SystemZMCAsmBackend : public MCAsmBackend {
116116
std::optional<MCFixupKind> getFixupKind(StringRef Name) const override;
117117
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
118118
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
119-
const MCValue &Target,
119+
const MCValue &Target, const uint64_t Value,
120120
const MCSubtargetInfo *STI) override;
121121
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
122122
const MCValue &Target, MutableArrayRef<char> Data,
@@ -161,7 +161,7 @@ SystemZMCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
161161

162162
bool SystemZMCAsmBackend::shouldForceRelocation(const MCAssembler &,
163163
const MCFixup &Fixup,
164-
const MCValue &,
164+
const MCValue &, const uint64_t,
165165
const MCSubtargetInfo *STI) {
166166
return Fixup.getKind() >= FirstLiteralRelocationKind;
167167
}

‎llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -132,7 +132,7 @@ class VEAsmBackend : public MCAsmBackend {
132132
}
133133

134134
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
135-
const MCValue &Target,
135+
const MCValue &Target, const uint64_t,
136136
const MCSubtargetInfo *STI) override {
137137
switch ((VE::Fixups)Fixup.getKind()) {
138138
default:

‎llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -172,7 +172,7 @@ class X86AsmBackend : public MCAsmBackend {
172172
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
173173

174174
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
175-
const MCValue &Target,
175+
const MCValue &Target, const uint64_t Value,
176176
const MCSubtargetInfo *STI) override;
177177

178178
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
@@ -659,6 +659,7 @@ const MCFixupKindInfo &X86AsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
659659

660660
bool X86AsmBackend::shouldForceRelocation(const MCAssembler &,
661661
const MCFixup &Fixup, const MCValue &,
662+
const uint64_t,
662663
const MCSubtargetInfo *STI) {
663664
return Fixup.getKind() >= FirstLiteralRelocationKind;
664665
}

‎llvm/test/CodeGen/AVR/branch-relaxation-long-backward.ll

+9-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; RUN: llc < %s -mtriple=avr -mcpu=attiny85 -filetype=obj -o - | llvm-objdump --mcpu=attiny85 -dr --no-show-raw-insn --no-leading-addr - | FileCheck --check-prefix=ATTINY85 %s
2-
; RUN: not llc < %s -mtriple=avr -mcpu=avr25 -filetype=obj -o - 2>&1 | FileCheck --check-prefix=AVR25 %s
2+
; RUN: llc < %s -mtriple=avr -mcpu=avr25 -filetype=obj -o - | llvm-objdump --mcpu=avr25 -dr --no-show-raw-insn --no-leading-addr - | FileCheck --check-prefix=AVR25 %s
33
; RUN: llc < %s -mtriple=avr -mcpu=avr3 -filetype=obj -o - | llvm-objdump --mcpu=avr3 -dr --no-show-raw-insn --no-leading-addr - | FileCheck --check-prefix=AVR3 %s
44

55
; ATTINY85: <main>:
@@ -10,7 +10,14 @@
1010
; ATTINY85: ldi r24, 0x3
1111
; ATTINY85-NEXT: ret
1212

13-
; AVR25: error: out of range branch target (expected an integer in the range -4096 to 4095)
13+
; AVR25: <main>:
14+
; AVR25-NEXT: andi r24, 0x1
15+
; AVR25: cpi r24, 0x0
16+
; AVR25-NEXT: breq .+2
17+
; AVR25-NEXT: rjmp .-2
18+
; AVR25-NEXT: R_AVR_13_PCREL .text+0x2
19+
; AVR25: ldi r24, 0x3
20+
; AVR25-NEXT: ret
1421

1522
; AVR3: <main>:
1623
; AVR3-NEXT: andi r24, 0x1

‎llvm/test/CodeGen/AVR/branch-relaxation-long-forward.ll

+9-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; RUN: llc < %s -mtriple=avr -mcpu=attiny85 -filetype=obj -o - | llvm-objdump --mcpu=attiny85 -dr --no-show-raw-insn --no-leading-addr - | FileCheck --check-prefix=ATTINY85 %s
2-
; RUN: not llc < %s -mtriple=avr -mcpu=avr25 -filetype=obj -o - 2>&1 | FileCheck --check-prefix=AVR25 %s
2+
; RUN: llc < %s -mtriple=avr -mcpu=avr25 -filetype=obj -o - | llvm-objdump --mcpu=avr25 -dr --no-show-raw-insn --no-leading-addr - | FileCheck --check-prefix=AVR25 %s
33
; RUN: llc < %s -mtriple=avr -mcpu=avr3 -filetype=obj -o - | llvm-objdump --mcpu=avr3 -dr --no-show-raw-insn --no-leading-addr - | FileCheck --check-prefix=AVR3 %s
44

55
; ATTINY85: <main>:
@@ -10,7 +10,14 @@
1010
; ATTINY85: ldi r24, 0x3
1111
; ATTINY85-NEXT: ret
1212

13-
; AVR25: error: out of range branch target (expected an integer in the range -4096 to 4095)
13+
; AVR25: <main>:
14+
; AVR25-NEXT: andi r24, 0x1
15+
; AVR25-NEXT: cpi r24, 0x0
16+
; AVR25-NEXT: brne .+2
17+
; AVR25-NEXT: rjmp .-2
18+
; AVR25-NEXT: R_AVR_13_PCREL .text+0x100c
19+
; AVR25: ldi r24, 0x3
20+
; AVR25-NEXT: ret
1421

1522
; AVR3: <main>:
1623
; AVR3-NEXT: andi r24, 0x1

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