fixup! pair down the number of instructions supported in getOperandInfo

Author: michaelmaitland

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

@@ -103,9 +103,10 @@ static cl::opt<bool> EnableVSETVLIAfterRVVRegAlloc(
     cl::desc("Insert vsetvls after vector register allocation"),
     cl::init(true));
 
-static cl::opt<bool> EnableVLOptimizer("riscv-enable-vl-optimizer",
-                                       cl::desc("Enable the VL Optimizer pass"),
-                                       cl::init(true), cl::Hidden);
+static cl::opt<bool>
+    EnableVLOptimizer("riscv-enable-vl-optimizer",
+                      cl::desc("Enable the RISC-V VL Optimizer pass"),
+                      cl::init(false), cl::Hidden);
 
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
   RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());