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tgymnichtgymnich
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[SPIRV] Add sign intrinsic part 1 (#101987)
partially fixes #70078 ### Changes - Added `int_spv_sign` intrinsic in `IntrinsicsSPIRV.td` - Added lowering and map to `int_spv_sign in `SPIRVInstructionSelector.cpp` - Added SPIR-V backend test case in `llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sign.ll` ### Related PRs - #101988 - #101989
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‎llvm/include/llvm/IR/IntrinsicsSPIRV.td

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@@ -80,4 +80,5 @@ let TargetPrefix = "spv" in {
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[llvm_anyint_ty, LLVMScalarOrSameVectorWidth<0, LLVMVectorElementType<0>>],
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[IntrNoMem, Commutative] >;
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def int_spv_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>;
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def int_spv_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty]>;
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}

‎llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

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@@ -28,6 +28,7 @@
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfoImpls.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Register.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/IR/IntrinsicsSPIRV.h"
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#include "llvm/Support/Debug.h"
@@ -184,6 +185,9 @@ class SPIRVInstructionSelector : public InstructionSelector {
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bool selectRsqrt(Register ResVReg, const SPIRVType *ResType,
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MachineInstr &I) const;
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bool selectSign(Register ResVReg, const SPIRVType *ResType,
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MachineInstr &I) const;
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bool selectFloatDot(Register ResVReg, const SPIRVType *ResType,
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MachineInstr &I) const;
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@@ -1603,6 +1607,52 @@ bool SPIRVInstructionSelector::selectSaturate(Register ResVReg,
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.constrainAllUses(TII, TRI, RBI);
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}
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bool SPIRVInstructionSelector::selectSign(Register ResVReg,
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const SPIRVType *ResType,
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MachineInstr &I) const {
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assert(I.getNumOperands() == 3);
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assert(I.getOperand(2).isReg());
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MachineBasicBlock &BB = *I.getParent();
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Register InputRegister = I.getOperand(2).getReg();
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SPIRVType *InputType = GR.getSPIRVTypeForVReg(InputRegister);
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auto &DL = I.getDebugLoc();
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if (!InputType)
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report_fatal_error("Input Type could not be determined.");
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bool IsFloatTy = GR.isScalarOrVectorOfType(InputRegister, SPIRV::OpTypeFloat);
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unsigned SignBitWidth = GR.getScalarOrVectorBitWidth(InputType);
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unsigned ResBitWidth = GR.getScalarOrVectorBitWidth(ResType);
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bool NeedsConversion = IsFloatTy || SignBitWidth != ResBitWidth;
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auto SignOpcode = IsFloatTy ? GL::FSign : GL::SSign;
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Register SignReg = NeedsConversion
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? MRI->createVirtualRegister(&SPIRV::IDRegClass)
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: ResVReg;
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bool Result =
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BuildMI(BB, I, DL, TII.get(SPIRV::OpExtInst))
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.addDef(SignReg)
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.addUse(GR.getSPIRVTypeID(InputType))
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.addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
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.addImm(SignOpcode)
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.addUse(InputRegister)
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.constrainAllUses(TII, TRI, RBI);
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if (NeedsConversion) {
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auto ConvertOpcode = IsFloatTy ? SPIRV::OpConvertFToS : SPIRV::OpSConvert;
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Result |= BuildMI(*I.getParent(), I, DL, TII.get(ConvertOpcode))
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.addDef(ResVReg)
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.addUse(GR.getSPIRVTypeID(ResType))
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.addUse(SignReg)
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.constrainAllUses(TII, TRI, RBI);
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}
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return Result;
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}
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bool SPIRVInstructionSelector::selectBitreverse(Register ResVReg,
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const SPIRVType *ResType,
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MachineInstr &I) const {
@@ -2339,6 +2389,8 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
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return selectNormalize(ResVReg, ResType, I);
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case Intrinsic::spv_rsqrt:
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return selectRsqrt(ResVReg, ResType, I);
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case Intrinsic::spv_sign:
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return selectSign(ResVReg, ResType, I);
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case Intrinsic::spv_lifetime_start:
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case Intrinsic::spv_lifetime_end: {
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unsigned Op = IID == Intrinsic::spv_lifetime_start ? SPIRV::OpLifetimeStart

‎llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sign.ll

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@@ -0,0 +1,143 @@
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; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
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; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450"
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; CHECK-DAG: %[[#float_16:]] = OpTypeFloat 16
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; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32
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; CHECK-DAG: %[[#float_64:]] = OpTypeFloat 64
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; CHECK-DAG: %[[#int_16:]] = OpTypeInt 16
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; CHECK-DAG: %[[#int_32:]] = OpTypeInt 32
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; CHECK-DAG: %[[#int_64:]] = OpTypeInt 64
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; CHECK-DAG: %[[#vec4_float_16:]] = OpTypeVector %[[#float_16]] 4
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; CHECK-DAG: %[[#vec4_float_32:]] = OpTypeVector %[[#float_32]] 4
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; CHECK-DAG: %[[#vec4_float_64:]] = OpTypeVector %[[#float_64]] 4
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; CHECK-DAG: %[[#vec4_int_16:]] = OpTypeVector %[[#int_16]] 4
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; CHECK-DAG: %[[#vec4_int_32:]] = OpTypeVector %[[#int_32]] 4
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; CHECK-DAG: %[[#vec4_int_64:]] = OpTypeVector %[[#int_64]] 4
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define noundef i32 @sign_half(half noundef %a) {
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entry:
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; CHECK: %[[#float_16_arg:]] = OpFunctionParameter %[[#float_16]]
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; CHECK: %[[#fsign:]] = OpExtInst %[[#float_16]] %[[#op_ext_glsl]] FSign %[[#float_16_arg]]
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; CHECK: %[[#]] = OpConvertFToS %[[#int_32]] %[[#fsign]]
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%elt.sign = call i32 @llvm.spv.sign.f16(half %a)
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ret i32 %elt.sign
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}
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define noundef i32 @sign_float(float noundef %a) {
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entry:
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; CHECK: %[[#float_32_arg:]] = OpFunctionParameter %[[#float_32]]
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; CHECK: %[[#fsign:]] = OpExtInst %[[#float_32]] %[[#op_ext_glsl]] FSign %[[#float_32_arg]]
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; CHECK: %[[#]] = OpConvertFToS %[[#int_32]] %[[#fsign]]
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%elt.sign = call i32 @llvm.spv.sign.f32(float %a)
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ret i32 %elt.sign
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}
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define noundef i32 @sign_double(double noundef %a) {
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entry:
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; CHECK: %[[#float_64_arg:]] = OpFunctionParameter %[[#float_64]]
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; CHECK: %[[#fsign:]] = OpExtInst %[[#float_64]] %[[#op_ext_glsl]] FSign %[[#float_64_arg]]
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; CHECK: %[[#]] = OpConvertFToS %[[#int_32]] %[[#fsign]]
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%elt.sign = call i32 @llvm.spv.sign.f64(double %a)
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ret i32 %elt.sign
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}
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define noundef i32 @sign_i16(i16 noundef %a) {
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entry:
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; CHECK: %[[#int_16_arg:]] = OpFunctionParameter %[[#int_16]]
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; CHECK: %[[#ssign:]] = OpExtInst %[[#int_16]] %[[#op_ext_glsl]] SSign %[[#int_16_arg]]
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; CHECK: %[[#]] = OpSConvert %[[#int_32]] %[[#ssign]]
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%elt.sign = call i32 @llvm.spv.sign.i16(i16 %a)
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ret i32 %elt.sign
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}
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define noundef i32 @sign_i32(i32 noundef %a) {
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entry:
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; CHECK: %[[#int_32_arg:]] = OpFunctionParameter %[[#int_32]]
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; CHECK: %[[#]] = OpExtInst %[[#int_32]] %[[#op_ext_glsl]] SSign %[[#int_32_arg]]
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%elt.sign = call i32 @llvm.spv.sign.i32(i32 %a)
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ret i32 %elt.sign
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}
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define noundef i32 @sign_i64(i64 noundef %a) {
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entry:
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; CHECK: %[[#int_64_arg:]] = OpFunctionParameter %[[#int_64]]
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; CHECK: %[[#ssign:]] = OpExtInst %[[#int_64]] %[[#op_ext_glsl]] SSign %[[#int_64_arg]]
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; CHECK: %[[#]] = OpSConvert %[[#int_32]] %[[#ssign]]
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%elt.sign = call i32 @llvm.spv.sign.i64(i64 %a)
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ret i32 %elt.sign
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}
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define noundef <4 x i32> @sign_half_vector(<4 x half> noundef %a) {
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entry:
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; CHECK: %[[#vec4_float_16_arg:]] = OpFunctionParameter %[[#vec4_float_16]]
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; CHECK: %[[#fsign:]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext_glsl]] FSign %[[#vec4_float_16_arg]]
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; CHECK: %[[#]] = OpConvertFToS %[[#vec4_int_32]] %[[#fsign]]
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%elt.sign = call <4 x i32> @llvm.spv.sign.v4f16(<4 x half> %a)
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ret <4 x i32> %elt.sign
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}
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define noundef <4 x i32> @sign_float_vector(<4 x float> noundef %a) {
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entry:
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; CHECK: %[[#vec4_float_32_arg:]] = OpFunctionParameter %[[#vec4_float_32]]
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; CHECK: %[[#fsign:]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext_glsl]] FSign %[[#vec4_float_32_arg]]
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; CHECK: %[[#]] = OpConvertFToS %[[#vec4_int_32]] %[[#fsign]]
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%elt.sign = call <4 x i32> @llvm.spv.sign.v4f32(<4 x float> %a)
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ret <4 x i32> %elt.sign
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}
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define noundef <4 x i32> @sign_double_vector(<4 x double> noundef %a) {
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entry:
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; CHECK: %[[#vec4_float_64_arg:]] = OpFunctionParameter %[[#vec4_float_64]]
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; CHECK: %[[#fsign:]] = OpExtInst %[[#vec4_float_64]] %[[#op_ext_glsl]] FSign %[[#vec4_float_64_arg]]
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; CHECK: %[[#]] = OpConvertFToS %[[#vec4_int_32]] %[[#fsign]]
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%elt.sign = call <4 x i32> @llvm.spv.sign.v4f64(<4 x double> %a)
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ret <4 x i32> %elt.sign
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}
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define noundef <4 x i32> @sign_i16_vector(<4 x i16> noundef %a) {
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entry:
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; CHECK: %[[#vec4_int_16_arg:]] = OpFunctionParameter %[[#vec4_int_16]]
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; CHECK: %[[#ssign:]] = OpExtInst %[[#vec4_int_16]] %[[#op_ext_glsl]] SSign %[[#vec4_int_16_arg]]
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; CHECK: %[[#]] = OpSConvert %[[#vec4_int_32]] %[[#ssign]]
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%elt.sign = call <4 x i32> @llvm.spv.sign.v4i16(<4 x i16> %a)
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ret <4 x i32> %elt.sign
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}
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define noundef <4 x i32> @sign_i32_vector(<4 x i32> noundef %a) {
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entry:
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; CHECK: %[[#vec4_int_32_arg:]] = OpFunctionParameter %[[#vec4_int_32]]
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; CHECK: %[[#]] = OpExtInst %[[#vec4_int_32]] %[[#op_ext_glsl]] SSign %[[#vec4_int_32_arg]]
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%elt.sign = call <4 x i32> @llvm.spv.sign.v4i32(<4 x i32> %a)
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ret <4 x i32> %elt.sign
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}
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define noundef <4 x i32> @sign_i64_vector(<4 x i64> noundef %a) {
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entry:
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; CHECK: %[[#vec4_int_64_arg:]] = OpFunctionParameter %[[#vec4_int_64]]
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; CHECK: %[[#ssign:]] = OpExtInst %[[#vec4_int_64]] %[[#op_ext_glsl]] SSign %[[#vec4_int_64_arg]]
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; CHECK: %[[#]] = OpSConvert %[[#vec4_int_32]] %[[#ssign]]
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%elt.sign = call <4 x i32> @llvm.spv.sign.v4i64(<4 x i64> %a)
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ret <4 x i32> %elt.sign
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}
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declare i32 @llvm.spv.sign.f16(half)
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declare i32 @llvm.spv.sign.f32(float)
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declare i32 @llvm.spv.sign.f64(double)
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declare i32 @llvm.spv.sign.i16(i16)
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declare i32 @llvm.spv.sign.i32(i32)
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declare i32 @llvm.spv.sign.i64(i64)
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declare <4 x i32> @llvm.spv.sign.v4f16(<4 x half>)
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declare <4 x i32> @llvm.spv.sign.v4f32(<4 x float>)
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declare <4 x i32> @llvm.spv.sign.v4f64(<4 x double>)
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declare <4 x i32> @llvm.spv.sign.v4i16(<4 x i16>)
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declare <4 x i32> @llvm.spv.sign.v4i32(<4 x i32>)
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declare <4 x i32> @llvm.spv.sign.v4i64(<4 x i64>)

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