@@ -860,7 +860,7 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
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.addUse (GV);
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return MIB.constrainAllUses (TII, TRI, RBI) &&
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BuildMI (BB, I, I.getDebugLoc (),
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- TII.get (STI.isVulkanEnv ()
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+ TII.get (STI.isLogicalSPIRV ()
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? SPIRV::OpInBoundsAccessChain
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: SPIRV::OpInBoundsPtrAccessChain))
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.addDef (ResVReg)
@@ -1034,7 +1034,7 @@ bool SPIRVInstructionSelector::selectUnOp(Register ResVReg,
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const SPIRVType *ResType,
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MachineInstr &I,
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unsigned Opcode) const {
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- if (STI.isOpenCLEnv () && I.getOperand (1 ).isReg ()) {
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+ if (STI.isPhysicalSPIRV () && I.getOperand (1 ).isReg ()) {
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Register SrcReg = I.getOperand (1 ).getReg ();
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bool IsGV = false ;
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for (MachineRegisterInfo::def_instr_iterator DefIt =
@@ -2062,7 +2062,7 @@ bool SPIRVInstructionSelector::selectDot4AddPackedExpansion(
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auto ExtractOp =
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Signed ? SPIRV::OpBitFieldSExtract : SPIRV::OpBitFieldUExtract;
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- bool ZeroAsNull = STI.isOpenCLEnv ();
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+ bool ZeroAsNull = ! STI.isShader ();
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// Extract the i8 element, multiply and add it to the accumulator
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for (unsigned i = 0 ; i < 4 ; i++) {
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// A[i]
@@ -2202,7 +2202,7 @@ bool SPIRVInstructionSelector::selectWaveOpInst(Register ResVReg,
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.addDef (ResVReg)
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.addUse (GR.getSPIRVTypeID (ResType))
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.addUse (GR.getOrCreateConstInt (SPIRV::Scope::Subgroup, I,
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- IntTy, TII, STI.isOpenCLEnv ()));
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+ IntTy, TII, ! STI.isShader ()));
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for (unsigned J = 2 ; J < I.getNumOperands (); J++) {
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BMI.addUse (I.getOperand (J).getReg ());
@@ -2226,7 +2226,7 @@ bool SPIRVInstructionSelector::selectWaveActiveCountBits(
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.addDef (ResVReg)
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.addUse (GR.getSPIRVTypeID (ResType))
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.addUse (GR.getOrCreateConstInt (SPIRV::Scope::Subgroup, I, IntTy,
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- TII, STI.isOpenCLEnv ()))
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+ TII, ! STI.isShader ()))
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.addImm (SPIRV::GroupOperation::Reduce)
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.addUse (BallotReg)
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.constrainAllUses (TII, TRI, RBI);
@@ -2257,7 +2257,7 @@ bool SPIRVInstructionSelector::selectWaveReduceMax(Register ResVReg,
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.addDef (ResVReg)
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.addUse (GR.getSPIRVTypeID (ResType))
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.addUse (GR.getOrCreateConstInt (SPIRV::Scope::Subgroup, I, IntTy, TII,
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- STI.isOpenCLEnv ()))
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+ ! STI.isShader ()))
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.addImm (SPIRV::GroupOperation::Reduce)
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.addUse (I.getOperand (2 ).getReg ())
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.constrainAllUses (TII, TRI, RBI);
@@ -2284,7 +2284,7 @@ bool SPIRVInstructionSelector::selectWaveReduceSum(Register ResVReg,
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.addDef (ResVReg)
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.addUse (GR.getSPIRVTypeID (ResType))
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.addUse (GR.getOrCreateConstInt (SPIRV::Scope::Subgroup, I, IntTy, TII,
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- STI.isOpenCLEnv ()))
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+ ! STI.isShader ()))
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.addImm (SPIRV::GroupOperation::Reduce)
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.addUse (I.getOperand (2 ).getReg ());
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}
@@ -2506,7 +2506,7 @@ bool SPIRVInstructionSelector::selectFCmp(Register ResVReg,
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Register SPIRVInstructionSelector::buildZerosVal (const SPIRVType *ResType,
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MachineInstr &I) const {
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// OpenCL uses nulls for Zero. In HLSL we don't use null constants.
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- bool ZeroAsNull = STI.isOpenCLEnv ();
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+ bool ZeroAsNull = ! STI.isShader ();
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if (ResType->getOpcode () == SPIRV::OpTypeVector)
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return GR.getOrCreateConstVector (0UL , I, ResType, TII, ZeroAsNull);
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return GR.getOrCreateConstInt (0 , I, ResType, TII, ZeroAsNull);
@@ -2515,7 +2515,7 @@ Register SPIRVInstructionSelector::buildZerosVal(const SPIRVType *ResType,
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Register SPIRVInstructionSelector::buildZerosValF (const SPIRVType *ResType,
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MachineInstr &I) const {
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// OpenCL uses nulls for Zero. In HLSL we don't use null constants.
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- bool ZeroAsNull = STI.isOpenCLEnv ();
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+ bool ZeroAsNull = ! STI.isShader ();
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APFloat VZero = getZeroFP (GR.getTypeForSPIRVType (ResType));
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if (ResType->getOpcode () == SPIRV::OpTypeVector)
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return GR.getOrCreateConstVector (VZero, I, ResType, TII, ZeroAsNull);
@@ -2525,7 +2525,7 @@ Register SPIRVInstructionSelector::buildZerosValF(const SPIRVType *ResType,
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Register SPIRVInstructionSelector::buildOnesValF (const SPIRVType *ResType,
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MachineInstr &I) const {
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// OpenCL uses nulls for Zero. In HLSL we don't use null constants.
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- bool ZeroAsNull = STI.isOpenCLEnv ();
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+ bool ZeroAsNull = ! STI.isShader ();
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APFloat VOne = getOneFP (GR.getTypeForSPIRVType (ResType));
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if (ResType->getOpcode () == SPIRV::OpTypeVector)
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return GR.getOrCreateConstVector (VOne, I, ResType, TII, ZeroAsNull);
@@ -2713,10 +2713,10 @@ bool SPIRVInstructionSelector::selectConst(Register ResVReg,
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Reg = GR.getOrCreateConstNullPtr (MIRBuilder, ResType);
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} else if (Opcode == TargetOpcode::G_FCONSTANT) {
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Reg = GR.getOrCreateConstFP (I.getOperand (1 ).getFPImm ()->getValue (), I,
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- ResType, TII, STI.isOpenCLEnv ());
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+ ResType, TII, ! STI.isShader ());
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} else {
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Reg = GR.getOrCreateConstInt (I.getOperand (1 ).getCImm ()->getZExtValue (), I,
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- ResType, TII, STI.isOpenCLEnv ());
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+ ResType, TII, ! STI.isShader ());
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}
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return Reg == ResVReg ? true : BuildCOPY (ResVReg, Reg, I);
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}
@@ -2796,7 +2796,7 @@ bool SPIRVInstructionSelector::selectGEP(Register ResVReg,
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// OpAccessChain could be used for OpenCL, but the SPIRV-LLVM Translator only
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// relies on PtrAccessChain, so we'll try not to deviate. For Vulkan however,
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// we have to use Op[InBounds]AccessChain.
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- const unsigned Opcode = STI.isVulkanEnv ()
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+ const unsigned Opcode = STI.isLogicalSPIRV ()
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? (IsGEPInBounds ? SPIRV::OpInBoundsAccessChain
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: SPIRV::OpAccessChain)
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: (IsGEPInBounds ? SPIRV::OpInBoundsPtrAccessChain
@@ -3493,7 +3493,7 @@ bool SPIRVInstructionSelector::selectFirstBitSet64Overflow(
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// On odd component counts we need to handle one more component
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if (CurrentComponent != ComponentCount) {
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- bool ZeroAsNull = STI.isOpenCLEnv ();
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+ bool ZeroAsNull = ! STI.isShader ();
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Register FinalElemReg = MRI->createVirtualRegister (GR.getRegClass (I64Type));
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Register ConstIntLastIdx = GR.getOrCreateConstInt (
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ComponentCount - 1 , I, BaseType, TII, ZeroAsNull);
@@ -3523,7 +3523,7 @@ bool SPIRVInstructionSelector::selectFirstBitSet64(
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Register SrcReg, unsigned BitSetOpcode, bool SwapPrimarySide) const {
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unsigned ComponentCount = GR.getScalarOrVectorComponentCount (ResType);
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SPIRVType *BaseType = GR.retrieveScalarOrVectorIntType (ResType);
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- bool ZeroAsNull = STI.isOpenCLEnv ();
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+ bool ZeroAsNull = ! STI.isShader ();
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Register ConstIntZero =
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GR.getOrCreateConstInt (0 , I, BaseType, TII, ZeroAsNull);
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Register ConstIntOne =
@@ -3725,7 +3725,7 @@ bool SPIRVInstructionSelector::selectAllocaArray(Register ResVReg,
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.addUse (GR.getSPIRVTypeID (ResType))
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.addUse (I.getOperand (2 ).getReg ())
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.constrainAllUses (TII, TRI, RBI);
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- if (!STI.isVulkanEnv ()) {
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+ if (!STI.isShader ()) {
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unsigned Alignment = I.getOperand (3 ).getImm ();
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buildOpDecorate (ResVReg, I, TII, SPIRV::Decoration::Alignment, {Alignment});
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}
@@ -3744,7 +3744,7 @@ bool SPIRVInstructionSelector::selectFrameIndex(Register ResVReg,
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.addUse (GR.getSPIRVTypeID (ResType))
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.addImm (static_cast <uint32_t >(SPIRV::StorageClass::Function))
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.constrainAllUses (TII, TRI, RBI);
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- if (!STI.isVulkanEnv ()) {
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+ if (!STI.isShader ()) {
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unsigned Alignment = I.getOperand (2 ).getImm ();
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buildOpDecorate (ResVReg, *It, TII, SPIRV::Decoration::Alignment,
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{Alignment});
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