[NVPTX] Tighten up legal v2i16 ops a bit

TargetLoweringBase makes almost all ops legal by default, so make ones
that Expand explicit and remove redundant legal settings.

Author: d0k

llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp

@@ -467,8 +467,6 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
   addRegisterClass(MVT::v2bf16, &NVPTX::Int32RegsRegClass);
 
   // Conversion to/from FP16/FP16x2 is always legal.
-  setOperationAction(ISD::SINT_TO_FP, MVT::f16, Legal);
-  setOperationAction(ISD::FP_TO_SINT, MVT::f16, Legal);
   setOperationAction(ISD::BUILD_VECTOR, MVT::v2f16, Custom);
   setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom);
   setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f16, Expand);
@@ -478,8 +476,6 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
   setFP16OperationAction(ISD::SETCC, MVT::v2f16, Legal, Expand);
 
   // Conversion to/from BFP16/BFP16x2 is always legal.
-  setOperationAction(ISD::SINT_TO_FP, MVT::bf16, Legal);
-  setOperationAction(ISD::FP_TO_SINT, MVT::bf16, Legal);
   setOperationAction(ISD::BUILD_VECTOR, MVT::v2bf16, Custom);
   setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2bf16, Custom);
   setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2bf16, Expand);
@@ -644,6 +640,13 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
   setI16x2OperationAction(ISD::SREM, MVT::v2i16, Legal, Custom);
   setI16x2OperationAction(ISD::UREM, MVT::v2i16, Legal, Custom);
 
+  // Other arithmetic and logic ops are unsupported.
+  setOperationAction({ISD::AND, ISD::OR, ISD::XOR, ISD::SDIV, ISD::UDIV,
+                      ISD::SRA, ISD::SRL, ISD::MULHS, ISD::MULHU,
+                      ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::SINT_TO_FP,
+                      ISD::UINT_TO_FP},
+                     MVT::v2i16, Expand);
+
   setOperationAction(ISD::ADDC, MVT::i32, Legal);
   setOperationAction(ISD::ADDE, MVT::i32, Legal);
   setOperationAction(ISD::SUBC, MVT::i32, Legal);

llvm/test/CodeGen/NVPTX/f16x2-instructions.ll

@@ -1468,5 +1468,23 @@ define <2 x half> @test_insertelement(<2 x half> %a, half %x) #0 {
   ret <2 x half> %i
 }
 
+; CHECK-LABEL: test_sitofp_2xi16_to_2xhalf(
+; CHECK:      cvt.rn.f16.s16
+; CHECK:      cvt.rn.f16.s16
+; CHECK:      ret;
+define <2 x half> @test_sitofp_2xi16_to_2xhalf(<2 x i16> %a) #0 {
+  %r = sitofp <2 x i16> %a to <2 x half>
+  ret <2 x half> %r
+}
+
+; CHECK-LABEL: test_uitofp_2xi16_to_2xhalf(
+; CHECK:      cvt.rn.f16.u16
+; CHECK:      cvt.rn.f16.u16
+; CHECK:      ret;
+define <2 x half> @test_uitofp_2xi16_to_2xhalf(<2 x i16> %a) #0 {
+  %r = uitofp <2 x i16> %a to <2 x half>
+  ret <2 x half> %r
+}
+
 attributes #0 = { nounwind }
 attributes #1 = { "unsafe-fp-math" = "true" }

llvm/test/CodeGen/NVPTX/i16x2-instructions.ll

@@ -534,4 +534,22 @@ define <2 x i16> @test_insertelement(<2 x i16> %a, i16 %x) #0 {
   ret <2 x i16> %i
 }
 
+; COMMON-LABEL: test_fptosi_2xhalf_to_2xi16(
+; COMMON:      cvt.rzi.s16.f16
+; COMMON:      cvt.rzi.s16.f16
+; COMMON:      ret;
+define <2 x i16> @test_fptosi_2xhalf_to_2xi16(<2 x half> %a) #0 {
+  %r = fptosi <2 x half> %a to <2 x i16>
+  ret <2 x i16> %r
+}
+
+; COMMON-LABEL: test_fptoui_2xhalf_to_2xi16(
+; COMMON:      cvt.rzi.u16.f16
+; COMMON:      cvt.rzi.u16.f16
+; COMMON:      ret;
+define <2 x i16> @test_fptoui_2xhalf_to_2xi16(<2 x half> %a) #0 {
+  %r = fptoui <2 x half> %a to <2 x i16>
+  ret <2 x i16> %r
+}
+
 attributes #0 = { nounwind }