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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 |
| 2 | +; RUN: llc -mtriple=xtensa -verify-machineinstrs < %s \ |
| 3 | +; RUN: | FileCheck %s |
| 4 | + |
| 5 | +define i64 @test_1(i32 %v) { |
| 6 | +; CHECK-LABEL: test_1: |
| 7 | +; CHECK: .cfi_startproc |
| 8 | +; CHECK-NEXT: # %bb.0: |
| 9 | +; CHECK-NEXT: l32r a8, .LCPI0_0 |
| 10 | +; CHECK-NEXT: add a2, a2, a8 |
| 11 | +; CHECK-NEXT: movi a3, 0 |
| 12 | +; CHECK-NEXT: ret |
| 13 | + %addres = add i32 %v, -65536 |
| 14 | + %res = zext i32 %addres to i64 |
| 15 | + ret i64 %res |
| 16 | +} |
| 17 | + |
| 18 | +define i64 @test_2(i32 %v) { |
| 19 | +; CHECK-LABEL: test_2: |
| 20 | +; CHECK: .cfi_startproc |
| 21 | +; CHECK-NEXT: # %bb.0: |
| 22 | +; CHECK-NEXT: l32r a8, .LCPI1_0 |
| 23 | +; CHECK-NEXT: add a2, a2, a8 |
| 24 | +; CHECK-NEXT: movi a3, 0 |
| 25 | +; CHECK-NEXT: ret |
| 26 | + %addres = add i32 %v, 65536 |
| 27 | + %res = zext i32 %addres to i64 |
| 28 | + ret i64 %res |
| 29 | +} |
| 30 | + |
| 31 | +define i64 @test_3(i32 %v) { |
| 32 | +; CHECK-LABEL: test_3: |
| 33 | +; CHECK: .cfi_startproc |
| 34 | +; CHECK-NEXT: # %bb.0: |
| 35 | +; CHECK-NEXT: addmi a2, a2, -32768 |
| 36 | +; CHECK-NEXT: movi a3, 0 |
| 37 | +; CHECK-NEXT: ret |
| 38 | + %addres = add i32 %v, -32768 |
| 39 | + %res = zext i32 %addres to i64 |
| 40 | + ret i64 %res |
| 41 | +} |
| 42 | + |
| 43 | +define i64 @test_4(i32 %v) { |
| 44 | +; CHECK-LABEL: test_4: |
| 45 | +; CHECK: .cfi_startproc |
| 46 | +; CHECK-NEXT: # %bb.0: |
| 47 | +; CHECK-NEXT: addmi a2, a2, 32512 |
| 48 | +; CHECK-NEXT: movi a3, 0 |
| 49 | +; CHECK-NEXT: ret |
| 50 | + %addres = add i32 %v, 32512 |
| 51 | + %res = zext i32 %addres to i64 |
| 52 | + ret i64 %res |
| 53 | +} |
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