[VE] Remove CodeGen deps from MCTargetDesc, NFC

See issue #64166 for more information about the layering issue.

Author: rnk

llvm/lib/Target/VE/VE.h

@@ -16,8 +16,6 @@
 
 #include "MCTargetDesc/VEMCTargetDesc.h"
 #include "llvm/ADT/StringSwitch.h"
-#include "llvm/CodeGen/ISDOpcodes.h"
-#include "llvm/CodeGen/SelectionDAGNodes.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Target/TargetMachine.h"
 
@@ -204,80 +202,6 @@ inline static unsigned VECondCodeToVal(VECC::CondCode CC) {
   }
 }
 
-/// Convert a DAG integer condition code to a VE ICC condition.
-inline static VECC::CondCode intCondCode2Icc(ISD::CondCode CC) {
-  switch (CC) {
-  default:
-    llvm_unreachable("Unknown integer condition code!");
-  case ISD::SETEQ:
-    return VECC::CC_IEQ;
-  case ISD::SETNE:
-    return VECC::CC_INE;
-  case ISD::SETLT:
-    return VECC::CC_IL;
-  case ISD::SETGT:
-    return VECC::CC_IG;
-  case ISD::SETLE:
-    return VECC::CC_ILE;
-  case ISD::SETGE:
-    return VECC::CC_IGE;
-  case ISD::SETULT:
-    return VECC::CC_IL;
-  case ISD::SETULE:
-    return VECC::CC_ILE;
-  case ISD::SETUGT:
-    return VECC::CC_IG;
-  case ISD::SETUGE:
-    return VECC::CC_IGE;
-  }
-}
-
-/// Convert a DAG floating point condition code to a VE FCC condition.
-inline static VECC::CondCode fpCondCode2Fcc(ISD::CondCode CC) {
-  switch (CC) {
-  default:
-    llvm_unreachable("Unknown fp condition code!");
-  case ISD::SETFALSE:
-    return VECC::CC_AF;
-  case ISD::SETEQ:
-  case ISD::SETOEQ:
-    return VECC::CC_EQ;
-  case ISD::SETNE:
-  case ISD::SETONE:
-    return VECC::CC_NE;
-  case ISD::SETLT:
-  case ISD::SETOLT:
-    return VECC::CC_L;
-  case ISD::SETGT:
-  case ISD::SETOGT:
-    return VECC::CC_G;
-  case ISD::SETLE:
-  case ISD::SETOLE:
-    return VECC::CC_LE;
-  case ISD::SETGE:
-  case ISD::SETOGE:
-    return VECC::CC_GE;
-  case ISD::SETO:
-    return VECC::CC_NUM;
-  case ISD::SETUO:
-    return VECC::CC_NAN;
-  case ISD::SETUEQ:
-    return VECC::CC_EQNAN;
-  case ISD::SETUNE:
-    return VECC::CC_NENAN;
-  case ISD::SETULT:
-    return VECC::CC_LNAN;
-  case ISD::SETUGT:
-    return VECC::CC_GNAN;
-  case ISD::SETULE:
-    return VECC::CC_LENAN;
-  case ISD::SETUGE:
-    return VECC::CC_GENAN;
-  case ISD::SETTRUE:
-    return VECC::CC_AT;
-  }
-}
-
 inline static VECC::CondCode VEValToCondCode(unsigned Val, bool IsInteger) {
   if (IsInteger) {
     switch (Val) {
@@ -402,22 +326,6 @@ inline static VERD::RoundingMode VEValToRD(unsigned Val) {
   llvm_unreachable("Invalid branch predicates");
 }
 
-/// getImmVal - get immediate representation of integer value
-inline static uint64_t getImmVal(const ConstantSDNode *N) {
-  return N->getSExtValue();
-}
-
-/// getFpImmVal - get immediate representation of floating point value
-inline static uint64_t getFpImmVal(const ConstantFPSDNode *N) {
-  const APInt &Imm = N->getValueAPF().bitcastToAPInt();
-  uint64_t Val = Imm.getZExtValue();
-  if (Imm.getBitWidth() == 32) {
-    // Immediate value of float place places at higher bits on VE.
-    Val <<= 32;
-  }
-  return Val;
-}
-
 // MImm - Special immediate value of sequential bit stream of 0 or 1.
 //   See VEInstrInfo.td for details.
 inline static bool isMImmVal(uint64_t Val) {

llvm/lib/Target/VE/VEISelLowering.h

@@ -65,6 +65,96 @@ enum NodeType : unsigned {
 };
 }
 
+/// Convert a DAG integer condition code to a VE ICC condition.
+inline static VECC::CondCode intCondCode2Icc(ISD::CondCode CC) {
+  switch (CC) {
+  default:
+    llvm_unreachable("Unknown integer condition code!");
+  case ISD::SETEQ:
+    return VECC::CC_IEQ;
+  case ISD::SETNE:
+    return VECC::CC_INE;
+  case ISD::SETLT:
+    return VECC::CC_IL;
+  case ISD::SETGT:
+    return VECC::CC_IG;
+  case ISD::SETLE:
+    return VECC::CC_ILE;
+  case ISD::SETGE:
+    return VECC::CC_IGE;
+  case ISD::SETULT:
+    return VECC::CC_IL;
+  case ISD::SETULE:
+    return VECC::CC_ILE;
+  case ISD::SETUGT:
+    return VECC::CC_IG;
+  case ISD::SETUGE:
+    return VECC::CC_IGE;
+  }
+}
+
+/// Convert a DAG floating point condition code to a VE FCC condition.
+inline static VECC::CondCode fpCondCode2Fcc(ISD::CondCode CC) {
+  switch (CC) {
+  default:
+    llvm_unreachable("Unknown fp condition code!");
+  case ISD::SETFALSE:
+    return VECC::CC_AF;
+  case ISD::SETEQ:
+  case ISD::SETOEQ:
+    return VECC::CC_EQ;
+  case ISD::SETNE:
+  case ISD::SETONE:
+    return VECC::CC_NE;
+  case ISD::SETLT:
+  case ISD::SETOLT:
+    return VECC::CC_L;
+  case ISD::SETGT:
+  case ISD::SETOGT:
+    return VECC::CC_G;
+  case ISD::SETLE:
+  case ISD::SETOLE:
+    return VECC::CC_LE;
+  case ISD::SETGE:
+  case ISD::SETOGE:
+    return VECC::CC_GE;
+  case ISD::SETO:
+    return VECC::CC_NUM;
+  case ISD::SETUO:
+    return VECC::CC_NAN;
+  case ISD::SETUEQ:
+    return VECC::CC_EQNAN;
+  case ISD::SETUNE:
+    return VECC::CC_NENAN;
+  case ISD::SETULT:
+    return VECC::CC_LNAN;
+  case ISD::SETUGT:
+    return VECC::CC_GNAN;
+  case ISD::SETULE:
+    return VECC::CC_LENAN;
+  case ISD::SETUGE:
+    return VECC::CC_GENAN;
+  case ISD::SETTRUE:
+    return VECC::CC_AT;
+  }
+}
+
+/// getImmVal - get immediate representation of integer value
+inline static uint64_t getImmVal(const ConstantSDNode *N) {
+  return N->getSExtValue();
+}
+
+/// getFpImmVal - get immediate representation of floating point value
+inline static uint64_t getFpImmVal(const ConstantFPSDNode *N) {
+  const APInt &Imm = N->getValueAPF().bitcastToAPInt();
+  uint64_t Val = Imm.getZExtValue();
+  if (Imm.getBitWidth() == 32) {
+    // Immediate value of float place places at higher bits on VE.
+    Val <<= 32;
+  }
+  return Val;
+}
+
 class VECustomDAG;
 
 class VETargetLowering : public TargetLowering {