Skip to content

Commit d772ce4

Browse files
ostannardostannard
committed
clang-format
1 parent d6d22cf commit d772ce4

File tree

3 files changed

+53
-21
lines changed

3 files changed

+53
-21
lines changed

‎llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@ const MCPhysReg*
6363
ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
6464
const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
6565
ARMSubtarget::PushPopSplitVariation PushPopSplit =
66-
STI.getPushPopSplitVariation(*MF);
66+
STI.getPushPopSplitVariation(*MF);
6767
const Function &F = MF->getFunction();
6868

6969
if (F.getCallingConv() == CallingConv::GHC) {

‎llvm/lib/Target/ARM/ARMBaseRegisterInfo.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,6 @@ namespace ARMRI {
4141

4242
} // end namespace ARMRI
4343

44-
4544
static inline bool isCalleeSavedRegister(unsigned Reg,
4645
const MCPhysReg *CSRegs) {
4746
for (unsigned i = 0; CSRegs[i]; ++i)

‎llvm/lib/Target/ARM/ARMFrameLowering.cpp‎

Lines changed: 52 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -215,11 +215,19 @@ SpillArea getSpillArea(Register Reg,
215215
case ARM::FPCXTNS:
216216
return SpillArea::FPCXT;
217217

218-
case ARM::R0: case ARM::R1: case ARM::R2: case ARM::R3:
219-
case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
218+
case ARM::R0:
219+
case ARM::R1:
220+
case ARM::R2:
221+
case ARM::R3:
222+
case ARM::R4:
223+
case ARM::R5:
224+
case ARM::R6:
225+
case ARM::R7:
220226
return SpillArea::GPRCS1;
221227

222-
case ARM::R8: case ARM::R9: case ARM::R10:
228+
case ARM::R8:
229+
case ARM::R9:
230+
case ARM::R10:
223231
if (Variation == ARMSubtarget::SplitR7)
224232
return SpillArea::GPRCS2;
225233
else
@@ -243,21 +251,45 @@ SpillArea getSpillArea(Register Reg,
243251
else
244252
return SpillArea::GPRCS1;
245253

246-
case ARM::D0: case ARM::D1: case ARM::D2: case ARM::D3:
247-
case ARM::D4: case ARM::D5: case ARM::D6: case ARM::D7:
254+
case ARM::D0:
255+
case ARM::D1:
256+
case ARM::D2:
257+
case ARM::D3:
258+
case ARM::D4:
259+
case ARM::D5:
260+
case ARM::D6:
261+
case ARM::D7:
248262
return SpillArea::DPRCS1;
249263

250-
case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
251-
case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
264+
case ARM::D8:
265+
case ARM::D9:
266+
case ARM::D10:
267+
case ARM::D11:
268+
case ARM::D12:
269+
case ARM::D13:
270+
case ARM::D14:
271+
case ARM::D15:
252272
if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
253273
return SpillArea::DPRCS2;
254274
else
255275
return SpillArea::DPRCS1;
256276

257-
case ARM::D16: case ARM::D17: case ARM::D18: case ARM::D19:
258-
case ARM::D20: case ARM::D21: case ARM::D22: case ARM::D23:
259-
case ARM::D24: case ARM::D25: case ARM::D26: case ARM::D27:
260-
case ARM::D28: case ARM::D29: case ARM::D30: case ARM::D31:
277+
case ARM::D16:
278+
case ARM::D17:
279+
case ARM::D18:
280+
case ARM::D19:
281+
case ARM::D20:
282+
case ARM::D21:
283+
case ARM::D22:
284+
case ARM::D23:
285+
case ARM::D24:
286+
case ARM::D25:
287+
case ARM::D26:
288+
case ARM::D27:
289+
case ARM::D28:
290+
case ARM::D29:
291+
case ARM::D30:
292+
case ARM::D31:
261293
return SpillArea::DPRCS1;
262294
}
263295
}
@@ -819,7 +851,7 @@ static void emitAligningInstructions(MachineFunction &MF, ARMFunctionInfo *AFI,
819851
static int getMaxFPOffset(const ARMSubtarget &STI, const ARMFunctionInfo &AFI,
820852
const MachineFunction &MF) {
821853
ARMSubtarget::PushPopSplitVariation PushPopSplit =
822-
STI.getPushPopSplitVariation(MF);
854+
STI.getPushPopSplitVariation(MF);
823855
// For Thumb1, push.w isn't available, so the first push will always push
824856
// r7 and lr onto the stack first.
825857
if (AFI.isThumb1OnlyFunction())
@@ -856,7 +888,7 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
856888
int FPCXTSaveSize = 0;
857889
bool NeedsWinCFI = needsWinCFI(MF);
858890
ARMSubtarget::PushPopSplitVariation PushPopSplit =
859-
STI.getPushPopSplitVariation(MF);
891+
STI.getPushPopSplitVariation(MF);
860892

861893
LLVM_DEBUG(dbgs() << "Emitting prologue for " << MF.getName() << "\n");
862894

@@ -1218,7 +1250,8 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
12181250
if (CFIPos.isValid()) {
12191251
int CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
12201252
nullptr,
1221-
MRI->getDwarfRegNum(Reg == ARM::R12 ? ARM::RA_AUTH_CODE : Reg, true),
1253+
MRI->getDwarfRegNum(Reg == ARM::R12 ? ARM::RA_AUTH_CODE : Reg,
1254+
true),
12221255
MFI.getObjectOffset(FI)));
12231256
BuildMI(MBB, CFIPos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
12241257
.addCFIIndex(CFIIndex)
@@ -1312,7 +1345,7 @@ void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
13121345
"This emitEpilogue does not support Thumb1!");
13131346
bool isARM = !AFI->isThumbFunction();
13141347
ARMSubtarget::PushPopSplitVariation PushPopSplit =
1315-
STI.getPushPopSplitVariation(MF);
1348+
STI.getPushPopSplitVariation(MF);
13161349

13171350
LLVM_DEBUG(dbgs() << "Emitting epilogue for " << MF.getName() << "\n");
13181351

@@ -1646,7 +1679,7 @@ void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
16461679
bool isTrap = false;
16471680
bool isCmseEntry = false;
16481681
ARMSubtarget::PushPopSplitVariation PushPopSplit =
1649-
STI.getPushPopSplitVariation(MF);
1682+
STI.getPushPopSplitVariation(MF);
16501683
if (MBB.end() != MI) {
16511684
DL = MI->getDebugLoc();
16521685
unsigned RetOpcode = MI->getOpcode();
@@ -2016,7 +2049,7 @@ bool ARMFrameLowering::spillCalleeSavedRegisters(
20162049
MachineFunction &MF = *MBB.getParent();
20172050
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
20182051
ARMSubtarget::PushPopSplitVariation PushPopSplit =
2019-
STI.getPushPopSplitVariation(MF);
2052+
STI.getPushPopSplitVariation(MF);
20202053
const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo();
20212054

20222055
unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
@@ -2090,7 +2123,7 @@ bool ARMFrameLowering::restoreCalleeSavedRegisters(
20902123
bool isVarArg = AFI->getArgRegsSaveSize() > 0;
20912124
unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
20922125
ARMSubtarget::PushPopSplitVariation PushPopSplit =
2093-
STI.getPushPopSplitVariation(MF);
2126+
STI.getPushPopSplitVariation(MF);
20942127

20952128
// The emitPopInst calls below do not insert reloads for the aligned DPRCS2
20962129
// registers. Do that here instead.
@@ -2350,7 +2383,7 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
23502383
(void)TRI; // Silence unused warning in non-assert builds.
23512384
Register FramePtr = RegInfo->getFrameRegister(MF);
23522385
ARMSubtarget::PushPopSplitVariation PushPopSplit =
2353-
STI.getPushPopSplitVariation(MF);
2386+
STI.getPushPopSplitVariation(MF);
23542387

23552388
// Spill R4 if Thumb2 function requires stack realignment - it will be used as
23562389
// scratch register. Also spill R4 if Thumb2 function has varsized objects,

0 commit comments

Comments
 (0)