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leecheechen
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[LoongArch] Add some binary IR instructions testcases for LASX (#74031)
The IR instructions include: - Binary Operations: add fadd sub fsub mul fmul udiv sdiv fdiv - Bitwise Binary Operations: shl lshr ashr
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‎llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll‎

Lines changed: 122 additions & 0 deletions
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
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define void @add_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: add_v32i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a2, 0
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; CHECK-NEXT: xvld $xr1, $a1, 0
9+
; CHECK-NEXT: xvadd.b $xr0, $xr1, $xr0
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
13+
%v0 = load <32 x i8>, ptr %a0
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%v1 = load <32 x i8>, ptr %a1
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%v2 = add <32 x i8> %v0, %v1
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store <32 x i8> %v2, ptr %res
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ret void
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}
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define void @add_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: add_v16i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a2, 0
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; CHECK-NEXT: xvld $xr1, $a1, 0
25+
; CHECK-NEXT: xvadd.h $xr0, $xr1, $xr0
26+
; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
29+
%v0 = load <16 x i16>, ptr %a0
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%v1 = load <16 x i16>, ptr %a1
31+
%v2 = add <16 x i16> %v0, %v1
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store <16 x i16> %v2, ptr %res
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ret void
34+
}
35+
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define void @add_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: add_v8i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a2, 0
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; CHECK-NEXT: xvld $xr1, $a1, 0
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; CHECK-NEXT: xvadd.w $xr0, $xr1, $xr0
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
45+
%v0 = load <8 x i32>, ptr %a0
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%v1 = load <8 x i32>, ptr %a1
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%v2 = add <8 x i32> %v0, %v1
48+
store <8 x i32> %v2, ptr %res
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ret void
50+
}
51+
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define void @add_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind {
53+
; CHECK-LABEL: add_v4i64:
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; CHECK: # %bb.0: # %entry
55+
; CHECK-NEXT: xvld $xr0, $a2, 0
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; CHECK-NEXT: xvld $xr1, $a1, 0
57+
; CHECK-NEXT: xvadd.d $xr0, $xr1, $xr0
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x i64>, ptr %a0
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%v1 = load <4 x i64>, ptr %a1
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%v2 = add <4 x i64> %v0, %v1
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store <4 x i64> %v2, ptr %res
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ret void
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}
67+
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define void @add_v32i8_31(ptr %res, ptr %a0) nounwind {
69+
; CHECK-LABEL: add_v32i8_31:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvaddi.bu $xr0, $xr0, 31
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <32 x i8>, ptr %a0
77+
%v1 = add <32 x i8> %v0, <i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31>
78+
store <32 x i8> %v1, ptr %res
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ret void
80+
}
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define void @add_v16i16_31(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: add_v16i16_31:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvaddi.hu $xr0, $xr0, 31
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <16 x i16>, ptr %a0
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%v1 = add <16 x i16> %v0, <i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31>
92+
store <16 x i16> %v1, ptr %res
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ret void
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}
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define void @add_v8i32_31(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: add_v8i32_31:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvaddi.wu $xr0, $xr0, 31
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x i32>, ptr %a0
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%v1 = add <8 x i32> %v0, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
106+
store <8 x i32> %v1, ptr %res
107+
ret void
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}
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define void @add_v4i64_31(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: add_v4i64_31:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvaddi.du $xr0, $xr0, 31
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x i64>, ptr %a0
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%v1 = add <4 x i64> %v0, <i64 31, i64 31, i64 31, i64 31>
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store <4 x i64> %v1, ptr %res
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ret void
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}

‎llvm/test/CodeGen/LoongArch/lasx/ir-instruction/ashr.ll‎

Lines changed: 178 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
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define void @ashr_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: ashr_v32i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a2, 0
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; CHECK-NEXT: xvld $xr1, $a1, 0
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; CHECK-NEXT: xvsra.b $xr0, $xr1, $xr0
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <32 x i8>, ptr %a0
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%v1 = load <32 x i8>, ptr %a1
15+
%v2 = ashr <32 x i8> %v0, %v1
16+
store <32 x i8> %v2, ptr %res
17+
ret void
18+
}
19+
20+
define void @ashr_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: ashr_v16i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a2, 0
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; CHECK-NEXT: xvld $xr1, $a1, 0
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; CHECK-NEXT: xvsra.h $xr0, $xr1, $xr0
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
29+
%v0 = load <16 x i16>, ptr %a0
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%v1 = load <16 x i16>, ptr %a1
31+
%v2 = ashr <16 x i16> %v0, %v1
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store <16 x i16> %v2, ptr %res
33+
ret void
34+
}
35+
36+
define void @ashr_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: ashr_v8i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a2, 0
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; CHECK-NEXT: xvld $xr1, $a1, 0
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; CHECK-NEXT: xvsra.w $xr0, $xr1, $xr0
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x i32>, ptr %a0
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%v1 = load <8 x i32>, ptr %a1
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%v2 = ashr <8 x i32> %v0, %v1
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store <8 x i32> %v2, ptr %res
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ret void
50+
}
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define void @ashr_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind {
53+
; CHECK-LABEL: ashr_v4i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a2, 0
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; CHECK-NEXT: xvld $xr1, $a1, 0
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; CHECK-NEXT: xvsra.d $xr0, $xr1, $xr0
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
61+
%v0 = load <4 x i64>, ptr %a0
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%v1 = load <4 x i64>, ptr %a1
63+
%v2 = ashr <4 x i64> %v0, %v1
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store <4 x i64> %v2, ptr %res
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ret void
66+
}
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define void @ashr_v32i8_1(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: ashr_v32i8_1:
70+
; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvsrai.b $xr0, $xr0, 1
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
76+
%v0 = load <32 x i8>, ptr %a0
77+
%v1 = ashr <32 x i8> %v0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
78+
store <32 x i8> %v1, ptr %res
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ret void
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}
81+
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define void @ashr_v32i8_7(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: ashr_v32i8_7:
84+
; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvsrai.b $xr0, $xr0, 7
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
90+
%v0 = load <32 x i8>, ptr %a0
91+
%v1 = ashr <32 x i8> %v0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
92+
store <32 x i8> %v1, ptr %res
93+
ret void
94+
}
95+
96+
define void @ashr_v16i16_1(ptr %res, ptr %a0) nounwind {
97+
; CHECK-LABEL: ashr_v16i16_1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvsrai.h $xr0, $xr0, 1
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
104+
%v0 = load <16 x i16>, ptr %a0
105+
%v1 = ashr <16 x i16> %v0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
106+
store <16 x i16> %v1, ptr %res
107+
ret void
108+
}
109+
110+
define void @ashr_v16i16_15(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: ashr_v16i16_15:
112+
; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvsrai.h $xr0, $xr0, 15
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
118+
%v0 = load <16 x i16>, ptr %a0
119+
%v1 = ashr <16 x i16> %v0, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
120+
store <16 x i16> %v1, ptr %res
121+
ret void
122+
}
123+
124+
define void @ashr_v8i32_1(ptr %res, ptr %a0) nounwind {
125+
; CHECK-LABEL: ashr_v8i32_1:
126+
; CHECK: # %bb.0: # %entry
127+
; CHECK-NEXT: xvld $xr0, $a1, 0
128+
; CHECK-NEXT: xvsrai.w $xr0, $xr0, 1
129+
; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
131+
entry:
132+
%v0 = load <8 x i32>, ptr %a0
133+
%v1 = ashr <8 x i32> %v0, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
134+
store <8 x i32> %v1, ptr %res
135+
ret void
136+
}
137+
138+
define void @ashr_v8i32_31(ptr %res, ptr %a0) nounwind {
139+
; CHECK-LABEL: ashr_v8i32_31:
140+
; CHECK: # %bb.0: # %entry
141+
; CHECK-NEXT: xvld $xr0, $a1, 0
142+
; CHECK-NEXT: xvsrai.w $xr0, $xr0, 31
143+
; CHECK-NEXT: xvst $xr0, $a0, 0
144+
; CHECK-NEXT: ret
145+
entry:
146+
%v0 = load <8 x i32>, ptr %a0
147+
%v1 = ashr <8 x i32> %v0, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
148+
store <8 x i32> %v1, ptr %res
149+
ret void
150+
}
151+
152+
define void @ashr_v4i64_1(ptr %res, ptr %a0) nounwind {
153+
; CHECK-LABEL: ashr_v4i64_1:
154+
; CHECK: # %bb.0: # %entry
155+
; CHECK-NEXT: xvld $xr0, $a1, 0
156+
; CHECK-NEXT: xvsrai.d $xr0, $xr0, 1
157+
; CHECK-NEXT: xvst $xr0, $a0, 0
158+
; CHECK-NEXT: ret
159+
entry:
160+
%v0 = load <4 x i64>, ptr %a0
161+
%v1 = ashr <4 x i64> %v0, <i64 1, i64 1, i64 1, i64 1>
162+
store <4 x i64> %v1, ptr %res
163+
ret void
164+
}
165+
166+
define void @ashr_v4i64_63(ptr %res, ptr %a0) nounwind {
167+
; CHECK-LABEL: ashr_v4i64_63:
168+
; CHECK: # %bb.0: # %entry
169+
; CHECK-NEXT: xvld $xr0, $a1, 0
170+
; CHECK-NEXT: xvsrai.d $xr0, $xr0, 63
171+
; CHECK-NEXT: xvst $xr0, $a0, 0
172+
; CHECK-NEXT: ret
173+
entry:
174+
%v0 = load <4 x i64>, ptr %a0
175+
%v1 = ashr <4 x i64> %v0, <i64 63, i64 63, i64 63, i64 63>
176+
store <4 x i64> %v1, ptr %res
177+
ret void
178+
}

‎llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fadd.ll‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2+
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
3+
4+
define void @fadd_v8f32(ptr %res, ptr %a0, ptr %a1) nounwind {
5+
; CHECK-LABEL: fadd_v8f32:
6+
; CHECK: # %bb.0: # %entry
7+
; CHECK-NEXT: xvld $xr0, $a2, 0
8+
; CHECK-NEXT: xvld $xr1, $a1, 0
9+
; CHECK-NEXT: xvfadd.s $xr0, $xr1, $xr0
10+
; CHECK-NEXT: xvst $xr0, $a0, 0
11+
; CHECK-NEXT: ret
12+
entry:
13+
%v0 = load <8 x float>, ptr %a0
14+
%v1 = load <8 x float>, ptr %a1
15+
%v2 = fadd <8 x float> %v0, %v1
16+
store <8 x float> %v2, ptr %res
17+
ret void
18+
}
19+
20+
define void @fadd_v4f64(ptr %res, ptr %a0, ptr %a1) nounwind {
21+
; CHECK-LABEL: fadd_v4f64:
22+
; CHECK: # %bb.0: # %entry
23+
; CHECK-NEXT: xvld $xr0, $a2, 0
24+
; CHECK-NEXT: xvld $xr1, $a1, 0
25+
; CHECK-NEXT: xvfadd.d $xr0, $xr1, $xr0
26+
; CHECK-NEXT: xvst $xr0, $a0, 0
27+
; CHECK-NEXT: ret
28+
entry:
29+
%v0 = load <4 x double>, ptr %a0
30+
%v1 = load <4 x double>, ptr %a1
31+
%v2 = fadd <4 x double> %v0, %v1
32+
store <4 x double> %v2, ptr %res
33+
ret void
34+
}

‎llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fdiv.ll‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2+
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
3+
4+
define void @fdiv_v8f32(ptr %res, ptr %a0, ptr %a1) nounwind {
5+
; CHECK-LABEL: fdiv_v8f32:
6+
; CHECK: # %bb.0: # %entry
7+
; CHECK-NEXT: xvld $xr0, $a2, 0
8+
; CHECK-NEXT: xvld $xr1, $a1, 0
9+
; CHECK-NEXT: xvfdiv.s $xr0, $xr1, $xr0
10+
; CHECK-NEXT: xvst $xr0, $a0, 0
11+
; CHECK-NEXT: ret
12+
entry:
13+
%v0 = load <8 x float>, ptr %a0
14+
%v1 = load <8 x float>, ptr %a1
15+
%v2 = fdiv <8 x float> %v0, %v1
16+
store <8 x float> %v2, ptr %res
17+
ret void
18+
}
19+
20+
define void @fdiv_v4f64(ptr %res, ptr %a0, ptr %a1) nounwind {
21+
; CHECK-LABEL: fdiv_v4f64:
22+
; CHECK: # %bb.0: # %entry
23+
; CHECK-NEXT: xvld $xr0, $a2, 0
24+
; CHECK-NEXT: xvld $xr1, $a1, 0
25+
; CHECK-NEXT: xvfdiv.d $xr0, $xr1, $xr0
26+
; CHECK-NEXT: xvst $xr0, $a0, 0
27+
; CHECK-NEXT: ret
28+
entry:
29+
%v0 = load <4 x double>, ptr %a0
30+
%v1 = load <4 x double>, ptr %a1
31+
%v2 = fdiv <4 x double> %v0, %v1
32+
store <4 x double> %v2, ptr %res
33+
ret void
34+
}

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