Skip to content

Commit e45cc4e

Browse files
committed
rebased, fix broken test (r2m now executed)
Signed-off-by: Nathan Gauër <[email protected]>
1 parent fbf29b2 commit e45cc4e

File tree

1 file changed

+25
-12
lines changed

1 file changed

+25
-12
lines changed

llvm/test/CodeGen/SPIRV/structurizer/condition-linear.ll

Lines changed: 25 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,9 @@
11
; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - -verify-machineinstrs | FileCheck %s --match-full-lines
22
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %}
33

4+
; NOTE: Many BB have 2 reg2mem registers: one for the register usage moved
5+
; to memory, and a second one just after caused by a PHI node.
6+
47
target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"
58
target triple = "spirv-unknown-vulkan-compute"
69

@@ -26,8 +29,8 @@ entry:
2629
}
2730

2831

29-
; CHECK-DAG: OpName %[[#reg_0:]] "cond.reg2mem"
30-
; CHECK-DAG: OpName %[[#reg_1:]] "cond9.reg2mem"
32+
; CHECK-DAG: OpName %[[#a:]] "a"
33+
; CHECK-DAG: OpName %[[#b:]] "b"
3134

3235
define internal spir_func void @main() #0 {
3336
; CHECK: OpSelectionMerge %[[#cond1_merge:]] None
@@ -39,21 +42,27 @@ entry:
3942
br i1 true, label %cond1_true, label %cond1_false
4043

4144
; CHECK: %[[#cond1_true]] = OpLabel
42-
; CHECK: OpStore %[[#reg_0]] %[[#]]
45+
; CHECK: %[[#tmp1:]] = OpLoad %[[#]] %[[#a]] Aligned 4
46+
; CHECK: OpStore %[[#tmp2:]] %[[#tmp1]] Aligned 4
47+
; CHECK: %[[#tmp3:]] = OpLoad %[[#]] %[[#tmp2]] Aligned 4
48+
; CHECK: OpStore %[[#r2m:]] %[[#tmp3]] Aligned 4
4349
; CHECK: OpBranch %[[#cond1_merge]]
4450
cond1_true:
4551
%2 = load i32, ptr %a, align 4
4652
br label %cond1_merge
4753

4854
; CHECK: %[[#cond1_false]] = OpLabel
49-
; CHECK: OpStore %[[#reg_0]] %[[#]]
55+
; CHECK: %[[#tmp1:]] = OpLoad %[[#]] %[[#b]] Aligned 4
56+
; CHECK: OpStore %[[#tmp2:]] %[[#tmp1]] Aligned 4
57+
; CHECK: %[[#tmp3:]] = OpLoad %[[#]] %[[#tmp2]] Aligned 4
58+
; CHECK: OpStore %[[#r2m]] %[[#tmp3]] Aligned 4
5059
; CHECK: OpBranch %[[#cond1_merge]]
5160
cond1_false:
5261
%3 = load i32, ptr %b, align 4
5362
br label %cond1_merge
5463

5564
; CHECK: %[[#cond1_merge]] = OpLabel
56-
; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#reg_0]]
65+
; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#r2m]] Aligned 4
5766
; CHECK: %[[#cond:]] = OpINotEqual %[[#]] %[[#tmp]] %[[#]]
5867
; CHECK: OpSelectionMerge %[[#cond2_merge:]] None
5968
; CHECK: OpBranchConditional %[[#cond]] %[[#cond2_true:]] %[[#cond2_merge]]
@@ -69,32 +78,36 @@ cond2_true:
6978
br label %cond2_merge
7079

7180
; CHECK: %[[#cond2_merge]] = OpLabel
72-
; CHECK: OpFunctionCall
81+
; CHECK: %[[#]] = OpFunctionCall %[[#]] %[[#]]
7382
; CHECK: OpSelectionMerge %[[#cond3_merge:]] None
7483
; CHECK: OpBranchConditional %[[#]] %[[#cond3_true:]] %[[#cond3_false:]]
7584
cond2_merge:
7685
%call2 = call spir_func noundef i32 @fn() #4 [ "convergencectrl"(token %0) ]
7786
br i1 true, label %cond3_true, label %cond3_false
7887

7988
; CHECK: %[[#cond3_true]] = OpLabel
80-
; CHECK: OpFunctionCall
81-
; CHECK: OpStore %[[#reg_1]] %[[#]]
89+
; CHECK: %[[#tmp1:]] = OpFunctionCall %[[#]] %[[#]]
90+
; CHECK: OpStore %[[#tmp2:]] %[[#tmp1]] Aligned 4
91+
; CHECK: %[[#tmp3:]] = OpLoad %[[#]] %[[#tmp2]] Aligned 4
92+
; CHECK: OpStore %[[#r2m2:]] %[[#tmp3]] Aligned 4
8293
; CHECK: OpBranch %[[#cond3_merge]]
8394
cond3_true:
8495
%call5 = call spir_func noundef i32 @fn1() #4 [ "convergencectrl"(token %0) ]
8596
br label %cond3_merge
8697

8798
; CHECK: %[[#cond3_false]] = OpLabel
88-
; CHECK: OpFunctionCall
89-
; CHECK: OpStore %[[#reg_1]] %[[#]]
99+
; CHECK: %[[#tmp1:]] = OpFunctionCall %[[#]] %[[#]]
100+
; CHECK: OpStore %[[#tmp2:]] %[[#tmp1]] Aligned 4
101+
; CHECK: %[[#tmp3:]] = OpLoad %[[#]] %[[#tmp2]] Aligned 4
102+
; CHECK: OpStore %[[#r2m2]] %[[#tmp3]] Aligned 4
90103
; CHECK: OpBranch %[[#cond3_merge]]
91104
cond3_false:
92105
%call7 = call spir_func noundef i32 @fn2() #4 [ "convergencectrl"(token %0) ]
93106
br label %cond3_merge
94107

95108
; CHECK: %[[#cond3_merge]] = OpLabel
96-
; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#reg_1]]
97-
; CHECK: %[[#cond:]] = OpINotEqual %[[#]] %[[#tmp]] %[[#]]
109+
; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#r2m2]] Aligned 4
110+
; CHECK: %[[#cond:]] = OpINotEqual %[[#]] %[[#tmp]] %[[#]]
98111
; CHECK: OpSelectionMerge %[[#cond4_merge:]] None
99112
; CHECK: OpBranchConditional %[[#cond]] %[[#cond4_true:]] %[[#cond4_merge]]
100113
cond3_merge:

0 commit comments

Comments
 (0)