ARM Assembler does not support syntax for implementation defined DSB instructions

[RichBarton-Arm]

Bugzilla Link	13138
Resolution	FIXED
Resolved on	Dec 09, 2015 10:59
Version	trunk
OS	All
Blocks	llvm/llvm-bugzilla-archive#18926
CC	@rengolin

Extended Description

The DSB (Data Synchronization Barrier) instruction ensures the completion of memory accesses and has assembly syntax:

DSB{}{} {}

Where the optional value can impose a limitation on the types of memory accesses effected. There are a number of proscribed assembly strings for this option, the default is "SY"

The ARMARM says the following about this value:

"All other encodings of option are reserved. It is implementation defined whether options other than SY are implemented. All unsupported and reserved options must execute as a full system DSB operation, but software must not rely on this behavior."

Currently, the MC Assembler does not have any syntax for the reserved option values. GNU recognises "DSB 0x0" for example as the reserved option value 0. The ARM assembler in MC throws a syntax error on this instruction.

In addition, all encodings of this instruction with any of bits 12:19 unset or any of the bits 8:11 set is UNPREDICTABLE. The MC decoder does not recognise this.

Reproduce with:

echo "DSB #​0x1" | .../llvm-mc -triple armv7 -show-inst -show-encoding
echo "0x4f 0xf0 0x7e 0xfa | .../llvm-mc -triple armv7 -disassemble -show-isnt -show-encoding

[llvmbot]

For gcc, we have the following disassembly,

f3bf 8f4f dsb sy
f3bf 8f40 dsb #​0
f3bf 8f41 dsb #​1
f3bf 8f42 dsb oshst
f3bf 8f43 dsb osh
f3bf 8f44 dsb #​4
f3bf 8f45 dsb #​5
f3bf 8f46 dsb unst
f3bf 8f47 dsb un
f3bf 8f48 dsb #​8
f3bf 8f49 dsb #​9
f3bf 8f4a dsb ishst
f3bf 8f4b dsb ish
f3bf 8f4c dsb #​12
f3bf 8f4d dsb #​13
f3bf 8f4e dsb st
f3bf 8f4f dsb sy

for the assembly code below,

    DSB     SY
    DSB     #​0x0
    DSB     #​0x1
    DSB     #​0x2
    DSB     #​0x3
    DSB     #​0x4
    DSB     #​0x5
    DSB     #​0x6
    DSB     #​0x7
    DSB     #​0x8
    DSB     #​0x9
    DSB     #​0xa
    DSB     #​0xb
    DSB     #​0xc
    DSB     #​0xd
    DSB     #​0xe
    DSB     #​0xf

[rengolin]

Hi Richard,

Seems to be working now:

$ echo "0x4f 0xf0 0x7f 0xf5" | llvm-mc -triple armv7 -disassemble -show-inst -show-encoding
.text
dsb sy @ encoding: [0x4f,0xf0,0x7f,0xf5]
@ <MCInst #​146 DSB
@ >
$ echo "DSB #​0xF" | llvm-mc -triple armv7 -show-inst -show-encoding
.text
dsb sy @ encoding: [0x4f,0xf0,0x7f,0xf5]
@ <MCInst #​146 DSB
@ >

[rengolin]

$ llvm-mc -triple armv7 dsb.s
.text
dsb sy
dsb #0x0
dsb #0x1
dsb oshst
dsb osh
dsb #0x4
dsb #0x5
dsb nshst
dsb nsh
dsb #0x8
dsb #0x9
dsb ishst
dsb ish
dsb #0xc
dsb #0xd
dsb st
dsb sy

$ echo "DSB #​0x3" | llvm-mc -triple armv7 -show-inst -show-encoding
.text
dsb osh @ encoding: [0x43,0xf0,0x7f,0xf5]
@ <MCInst #​100 DSB
@ >
$ echo 0x43 0xf0 0x7f 0xf5 | llvm-mc -triple armv7 -disassemble -show-inst -show-encoding
.text
dsb osh @ encoding: [0x43,0xf0,0x7f,0xf5]
@ <MCInst #​100 DSB
@ >

LGTM.

[rengolin]

mentioned in issue llvm/llvm-bugzilla-archive#18926