[HLSL] Propose generic bitfield intrinsics in LLVM

[bogner]

As per the conclusions in #87367, we should propose adding bitfield instructions as generic LLVM intrinsics. Specifically, we need operations for Bfi, Ibfe, and Ubfe.

These operations exist in several ISAs (sometimes spelled differently, as in BFX on ARM archs), so I think it's reasonable to argue that having a generic for intrinsic for them is useful.

Acceptance Criteria

• Either consensus from the LLVM community that we should add these operations, or a well reasoned rejection
  • this discussion will occur on the LLVM discourse

[pinskia]

Note GCC's IRs have BIT_FIELD_REF/BIT_INSERT_EXPR (gimple) and zero_extract/sign_extract (RTL; zero_extract can be on lhs of an RTL insn) which is used for both bit field extractions and inserts.

BIT_FIELD_REF takes 3 operands, 0: the original SSA_NAME; 1: bit width, 2: bits starting psoition (1 and 2 have to be constants); the resulting type needs to be the same precision as the bit width (the sign/zero extract is implicit with the cast afterwards)
BIT_INSERT_EXPR takes 3 operands, 0: the original SSA_NAME, 1: the replacement value (SSA_NAME or constant), 2: starting position. The width is taken based on the replacement value precision/size

zero_extract/sign_extract takes 3 operands, similar as BIT_FIELD_REF except for the resulting mode is the same as the inner mode is the same as the outer mode. To do an bit insert, you have a zero_extract on the lhs describing which bits are inserted including width.

how this helps to see understand how at least one other compiler handle this.