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Merged
merged 26 commits into from
Oct 25, 2024
Merged

[RISCV] Add Smrnmi extension #111668

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c7a9b55
Update RISCVSystemOperands.td
dong-miao Oct 9, 2024
91125a1
Update machine-csr-names.s
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6014139
Update riscv-target-features.c
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Update RISCVUsage.rst
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6844754
Update RISCVFeatures.td
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7922fbb
Update attributes.ll
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Update attributes.ll
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Update attribute-arch.s
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805fd8a
Update RISCVISAInfoTest.cpp
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Update riscv-target-features.c
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Update riscv-target-features.c
dong-miao Oct 9, 2024
7db01e7
Update RISCVInstrInfo.td
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29eaa52
Update priv-valid.s
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Update priv-invalid.s
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Update RISCVFeatures.td
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Update RISCVFeatures.td
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Update RISCVInstrInfo.td
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95567b3
Update RISCVSystemOperands.td
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88dfe2b
Update priv-invalid.s
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Update priv-valid.s
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116aa08
Create smrnmi-invalid.s
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Create smrnmi-valid.s
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6249ffb
Update llvm/docs/RISCVUsage.rst
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2452b33
Merge branch 'main' into develop
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5a58844
Update attribute-arch.s
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Update print-supported-extensions-riscv.c
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9 changes: 9 additions & 0 deletions clang/test/Preprocessor/riscv-target-features.c
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Expand Up @@ -30,6 +30,7 @@
// CHECK-NOT: __riscv_smcdeleg {{.*$}}
// CHECK-NOT: __riscv_smcsrind {{.*$}}
// CHECK-NOT: __riscv_smepmp {{.*$}}
// CHECK-NOT: __riscv_smrnmi {{.*$}}
// CHECK-NOT: __riscv_smstateen {{.*$}}
// CHECK-NOT: __riscv_ssaia {{.*$}}
// CHECK-NOT: __riscv_ssccfg {{.*$}}
Expand Down Expand Up @@ -1449,6 +1450,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SMEPMP-EXT %s
// CHECK-SMEPMP-EXT: __riscv_smepmp 1000000{{$}}

// RUN: %clang --target=riscv32 \
// RUN: -march=rv32ismrnmi1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMRNMI-EXT %s
// RUN: %clang --target=riscv64 \
// RUN: -march=rv64ismrnmi1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMRNMI-EXT %s
// CHECK-SMRNMI-EXT: __riscv_smrnmi 1000000{{$}}

// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32izfa -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s
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1 change: 1 addition & 0 deletions llvm/docs/RISCVUsage.rst
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Expand Up @@ -129,6 +129,7 @@ on support follow.
``Smcdeleg`` Supported
``Smcsrind`` Supported
``Smepmp`` Supported
``Smrnmi`` Supported
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This should probably be "Assembly Support" - some of the other *ret instructions have support in clang for __attribute((interrupt(<kind>))) which doesn't yet exist for mnret - there's no obligation to add this support in the first PR, but this should mean no one expects it has the same level of featureas as the other *ret instructions.

Suggested change
``Smrnmi`` Supported
``Smrnmi`` Assembly Support

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Okay, thanks for your help.

``Smstateen`` Assembly Support
``Ssaia`` Supported
``Ssccfg`` Supported
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4 changes: 4 additions & 0 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
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Expand Up @@ -931,6 +931,10 @@ def FeatureStdExtSmepmp
: RISCVExtension<"smepmp", 1, 0,
"'Smepmp' (Enhanced Physical Memory Protection)">;

def FeatureStdExtSmrnmi
: RISCVExtension<"smrnmi", 1, 0,
"'Smrnmi' (Extension for Resumable Non-Maskable Interrupts)">;
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I don't think we usually write "Extension for" in the description.

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Okay, I have deleted the relevant content.


def FeatureStdExtSmcdeleg
: RISCVExtension<"smcdeleg", 1, 0,
"'Smcdeleg' (Counter Delegation Machine Level)">;
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9 changes: 9 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.td
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Expand Up @@ -66,6 +66,8 @@ def riscv_sret_glue : SDNode<"RISCVISD::SRET_GLUE", SDTNone,
[SDNPHasChain, SDNPOptInGlue]>;
def riscv_mret_glue : SDNode<"RISCVISD::MRET_GLUE", SDTNone,
[SDNPHasChain, SDNPOptInGlue]>;
def riscv_mnret_glue : SDNode<"RISCVISD::MNRET_GLUE", SDTNone,
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@wangpc-pp wangpc-pp Oct 10, 2024 •
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This should be in another patch for CodeGen. And, do we really need it? It will only be used in supervisor IIUC.

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RISCVISD::MNRET_GLUE isn't defined in this patch so it should definitely be removed.

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Thanks, I have removed the relevant content.

[SDNPHasChain, SDNPOptInGlue]>;
def riscv_selectcc : SDNode<"RISCVISD::SELECT_CC", SDT_RISCVSelectCC>;
def riscv_brcc : SDNode<"RISCVISD::BR_CC", SDT_RISCVBrCC,
[SDNPHasChain]>;
Expand Down Expand Up @@ -813,6 +815,12 @@ def MRET : Priv<"mret", 0b0011000>, Sched<[]> {
let rs1 = 0;
let rs2 = 0b00010;
}

def MNRET : Priv<"mnret", 0b0111000>, Sched<[]> {
let rd = 0;
let rs1 = 0;
let rs2 = 0b00010;
}
} // isBarrier = 1, isReturn = 1, isTerminator = 1

def WFI : Priv<"wfi", 0b0001000>, Sched<[]> {
Expand Down Expand Up @@ -1581,6 +1589,7 @@ def : Pat<(riscv_call texternalsym:$func), (PseudoCALL texternalsym:$func)>;

def : Pat<(riscv_sret_glue), (SRET)>;
def : Pat<(riscv_mret_glue), (MRET)>;
def : Pat<(riscv_mnret_glue), (MNRET)>;

let isCall = 1, Defs = [X1] in {
let Predicates = [NoStdExtZicfilp] in
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8 changes: 8 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSystemOperands.td
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Expand Up @@ -276,6 +276,14 @@ foreach i = 0...15 in {
foreach i = 0...63 in
def : SysReg<"pmpaddr"#i, !add(0x3B0, i)>;

//===----------------------------------------------------------------------===//
// Machine Non-Maskable Interrupt Handling
//===----------------------------------------------------------------------===//
def:SysReg<"mnscratch",0x740>;
def:SysReg<"mnepc",0x741>;
def:SysReg<"mncause",0x742>;
def:SysReg<"mnstatus",0x744>;

//===----------------------------------------------------------------------===//
// Machine Counter and Timers
//===----------------------------------------------------------------------===//
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4 changes: 4 additions & 0 deletions llvm/test/CodeGen/RISCV/attributes.ll
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Expand Up @@ -118,6 +118,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s
; RUN: llc -mtriple=riscv32 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCDELEG %s
; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s
; RUN: llc -mtriple=riscv32 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV32SMRNMI %s
; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFWMA %s
Expand Down Expand Up @@ -261,6 +262,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s
; RUN: llc -mtriple=riscv64 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCDELEG %s
; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s
; RUN: llc -mtriple=riscv64 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV64SMRNMI %s
; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFWMA %s
Expand Down Expand Up @@ -410,6 +412,7 @@
; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0"
; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
; RV32SMRNMI: .attribute 5, "rv32i2p1_smrnmi1p0"
; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
Expand Down Expand Up @@ -551,6 +554,7 @@
; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0"
; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
; RV64SMRNMI: .attribute 5, "rv64i2p1_smrnmi1p0"
; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"
; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
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3 changes: 3 additions & 0 deletions llvm/test/MC/RISCV/attribute-arch.s
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Expand Up @@ -327,6 +327,9 @@
.attribute arch, "rv32i_smepmp1p0"
# CHECK: attribute 5, "rv32i2p1_smepmp1p0"

.attribute arch, "rv32i_smrnmi1p0"
# CHECK: attribute 5, "rv32i2p1_smrnmid1p0"

.attribute arch, "rv32i_ssccfg1p0"
# CHECK: attribute 5, "rv32i2p1_ssccfg1p0"

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60 changes: 60 additions & 0 deletions llvm/test/MC/RISCV/machine-csr-names.s
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Expand Up @@ -1913,6 +1913,66 @@ csrrs t1, mhpmcounter31, zero
csrrs t2, 0xB1F, zero


######################################
# Machine Counter Setup
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Section title is incorrect.

The registers are already tested in rv32-machine-csr-names.s but they should be in this file. That was a mistake.

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Okay, I haven't made any modifications to the content of this file

######################################
# mnscratch
# name
# CHECK-INST: csrrs t1, mnscratch, zero
# CHECK-ENC: encoding: [0x73,0x23,0x00,0x74]
# CHECK-INST-ALIAS: csrr t1, mnscratch
# uimm12
# CHECK-INST: csrrs t2, mnscratch, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x74]
# CHECK-INST-ALIAS: csrr t2, mnscratch
# name
csrrs t1, mnscratch, zero
# uimm12
csrrs t2, 0x740, zero

# mnepc
# name
# CHECK-INST: csrrs t1, mnepc, zero
# CHECK-ENC: encoding: [0x73,0x23,0x10,0x74]
# CHECK-INST-ALIAS: csrr t1, mnepc
# uimm12
# CHECK-INST: csrrs t2, mnepc, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x74]
# CHECK-INST-ALIAS: csrr t2, mnepc
# name
csrrs t1, mnepc, zero
# uimm12
csrrs t2, 0x741, zero

# mncause
# name
# CHECK-INST: csrrs t1, mncause, zero
# CHECK-ENC: encoding: [0x73,0x23,0x20,0x74]
# CHECK-INST-ALIAS: csrr t1, mncause
# uimm12
# CHECK-INST: csrrs t2, mncause, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x74]
# CHECK-INST-ALIAS: csrr t2, mncause
# name
csrrs t1, mncause, zero
# uimm12
csrrs t2, 0x742, zero

# mnstatus
# name
# CHECK-INST: csrrs t1, mnstatus, zero
# CHECK-ENC: encoding: [0x73,0x23,0x40,0x74]
# CHECK-INST-ALIAS: csrr t1, mnstatus
# uimm12
# CHECK-INST: csrrs t2, mnstatus, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x74]
# CHECK-INST-ALIAS: csrr t2, mnstatus
# name
csrrs t1, mnstatus, zero
# uimm12
csrrs t2, 0x744, zero


######################################
# Machine Counter Setup
######################################
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2 changes: 2 additions & 0 deletions llvm/test/MC/RISCV/priv-invalid.s
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Expand Up @@ -2,6 +2,8 @@

mret 0x10 # CHECK: :[[@LINE]]:6: error: invalid operand for instruction

mnret 0x10 # CHECK: :[[@LINE]]:6: error: invalid operand for instruction

sfence.vma zero, a1, a2 # CHECK: :[[@LINE]]:22: error: invalid operand for instruction

sfence.vma a0, 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
Expand Down
4 changes: 4 additions & 0 deletions llvm/test/MC/RISCV/priv-valid.s
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Expand Up @@ -17,6 +17,10 @@ sret
# CHECK: encoding: [0x73,0x00,0x20,0x30]
mret

# CHECK-INST: mnret
# CHECK: encoding: [0x73,0x00,0x20,0x70]
mnret

# CHECK-INST: wfi
# CHECK: encoding: [0x73,0x00,0x50,0x10]
wfi
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1 change: 1 addition & 0 deletions llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
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Expand Up @@ -1065,6 +1065,7 @@ R"(All available -march extensions for RISC-V
smcdeleg 1.0
smcsrind 1.0
smepmp 1.0
smrnmi 1.0
smstateen 1.0
ssaia 1.0
ssccfg 1.0
Expand Down