diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 86b99a5210924..d5a07e616236e 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -12020,7 +12020,7 @@ SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { if (const auto *C = dyn_cast(PHIOp)) { Register &RegOut = ConstantsOut[C]; if (!RegOut) { - RegOut = FuncInfo.CreateRegs(C); + RegOut = FuncInfo.CreateRegs(&PN); // We need to zero/sign extend ConstantInt phi operands to match // assumptions in FunctionLoweringInfo::ComputePHILiveOutRegInfo. ISD::NodeType ExtendType = ISD::ANY_EXTEND; diff --git a/llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll b/llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll index 9988b2fa1eaf0..55a560c8d9b2f 100644 --- a/llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll +++ b/llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll @@ -8,13 +8,11 @@ define i32 @prolog_spill(i32 %arg0, i32 %arg1, i32 %arg2) { ; REGALLOC-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; REGALLOC-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2 ; REGALLOC-NEXT: {{ $}} - ; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr2, %stack.5, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5) - ; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr1, %stack.4, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) + ; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr2, %stack.4, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) + ; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr1, %stack.3, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) ; REGALLOC-NEXT: renamable $sgpr4 = S_MOV_B32 49 ; REGALLOC-NEXT: renamable $sgpr4_sgpr5 = V_CMP_GT_I32_e64 killed $vgpr0, killed $sgpr4, implicit $exec - ; REGALLOC-NEXT: renamable $sgpr6 = IMPLICIT_DEF - ; REGALLOC-NEXT: renamable $vgpr0 = COPY killed renamable $sgpr6 - ; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr0, %stack.3, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) + ; REGALLOC-NEXT: renamable $vgpr0 = IMPLICIT_DEF ; REGALLOC-NEXT: renamable $sgpr6_sgpr7 = COPY $exec, implicit-def $exec ; REGALLOC-NEXT: renamable $sgpr4_sgpr5 = S_AND_B64 renamable $sgpr6_sgpr7, killed renamable $sgpr4_sgpr5, implicit-def dead $scc ; REGALLOC-NEXT: renamable $sgpr6_sgpr7 = S_XOR_B64 renamable $sgpr4_sgpr5, killed renamable $sgpr6_sgpr7, implicit-def dead $scc @@ -33,8 +31,8 @@ define i32 @prolog_spill(i32 %arg0, i32 %arg1, i32 %arg2) { ; REGALLOC-NEXT: $sgpr4 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 0, implicit-def $sgpr4_sgpr5 ; REGALLOC-NEXT: $sgpr5 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 1 ; REGALLOC-NEXT: renamable $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 killed renamable $sgpr4_sgpr5, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; REGALLOC-NEXT: $vgpr0 = SI_SPILL_V32_RESTORE %stack.3, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) - ; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr0, %stack.6, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5) + ; REGALLOC-NEXT: $vgpr0 = SI_SPILL_V32_RESTORE %stack.6, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.6, addrspace 5) + ; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr0, %stack.5, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5) ; REGALLOC-NEXT: renamable $sgpr4_sgpr5 = S_AND_B64 $exec, killed renamable $sgpr4_sgpr5, implicit-def dead $scc ; REGALLOC-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr4, 2, $vgpr63, implicit-def $sgpr4_sgpr5, implicit $sgpr4_sgpr5 ; REGALLOC-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr5, 3, $vgpr63, implicit $sgpr4_sgpr5 @@ -46,19 +44,19 @@ define i32 @prolog_spill(i32 %arg0, i32 %arg1, i32 %arg2) { ; REGALLOC-NEXT: bb.2.bb.1: ; REGALLOC-NEXT: successors: %bb.4(0x80000000) ; REGALLOC-NEXT: {{ $}} - ; REGALLOC-NEXT: $vgpr0 = SI_SPILL_V32_RESTORE %stack.4, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5) + ; REGALLOC-NEXT: $vgpr0 = SI_SPILL_V32_RESTORE %stack.3, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) ; REGALLOC-NEXT: renamable $sgpr4 = S_MOV_B32 10 ; REGALLOC-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $vgpr0, killed $sgpr4, 0, implicit $exec - ; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr0, %stack.6, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5) + ; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr0, %stack.5, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5) ; REGALLOC-NEXT: S_BRANCH %bb.4 ; REGALLOC-NEXT: {{ $}} ; REGALLOC-NEXT: bb.3.bb.2: ; REGALLOC-NEXT: successors: %bb.1(0x80000000) ; REGALLOC-NEXT: {{ $}} - ; REGALLOC-NEXT: $vgpr0 = SI_SPILL_V32_RESTORE %stack.5, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.5, addrspace 5) + ; REGALLOC-NEXT: $vgpr0 = SI_SPILL_V32_RESTORE %stack.4, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5) ; REGALLOC-NEXT: renamable $sgpr4 = S_MOV_B32 20 ; REGALLOC-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $vgpr0, killed $sgpr4, 0, implicit $exec - ; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr0, %stack.3, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) + ; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr0, %stack.6, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5) ; REGALLOC-NEXT: S_BRANCH %bb.1 ; REGALLOC-NEXT: {{ $}} ; REGALLOC-NEXT: bb.4.bb.3: @@ -66,7 +64,7 @@ define i32 @prolog_spill(i32 %arg0, i32 %arg1, i32 %arg2) { ; REGALLOC-NEXT: $sgpr4 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 2, implicit-def $sgpr4_sgpr5 ; REGALLOC-NEXT: $sgpr5 = SI_RESTORE_S32_FROM_VGPR killed $vgpr63, 3 ; REGALLOC-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr4_sgpr5, implicit-def dead $scc - ; REGALLOC-NEXT: $vgpr0 = SI_SPILL_V32_RESTORE %stack.6, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.6, addrspace 5) + ; REGALLOC-NEXT: $vgpr0 = SI_SPILL_V32_RESTORE %stack.5, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.5, addrspace 5) ; REGALLOC-NEXT: renamable $vgpr0 = V_LSHL_ADD_U32_e64 killed $vgpr0, 2, $vgpr0, implicit $exec ; REGALLOC-NEXT: SI_RETURN implicit killed $vgpr0 bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll b/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll index fdae1696a5a49..3305cac0d7ea6 100644 --- a/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll +++ b/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll @@ -73,76 +73,76 @@ define void @test_sinkable_flat_small_offset_i32(ptr %out, ptr %in, i32 %cond) { ; GFX7-LABEL: test_sinkable_flat_small_offset_i32: ; GFX7: ; %bb.0: ; %entry ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-NEXT: v_mov_b32_e32 v5, 0 ; GFX7-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; GFX7-NEXT: v_mov_b32_e32 v4, 0 ; GFX7-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX7-NEXT: s_cbranch_execz .LBB0_2 ; GFX7-NEXT: ; %bb.1: ; %if ; GFX7-NEXT: v_add_i32_e32 v2, vcc, 28, v2 ; GFX7-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; GFX7-NEXT: flat_load_dword v4, v[2:3] +; GFX7-NEXT: flat_load_dword v5, v[2:3] ; GFX7-NEXT: .LBB0_2: ; %endif ; GFX7-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX7-NEXT: v_add_i32_e32 v0, vcc, 0x3d08fc, v0 ; GFX7-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v4 +; GFX7-NEXT: flat_store_dword v[0:1], v5 ; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: test_sinkable_flat_small_offset_i32: ; GFX8: ; %bb.0: ; %entry ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v5, 0 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; GFX8-NEXT: v_mov_b32_e32 v4, 0 ; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX8-NEXT: s_cbranch_execz .LBB0_2 ; GFX8-NEXT: ; %bb.1: ; %if ; GFX8-NEXT: v_add_u32_e32 v2, vcc, 28, v2 ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; GFX8-NEXT: flat_load_dword v4, v[2:3] +; GFX8-NEXT: flat_load_dword v5, v[2:3] ; GFX8-NEXT: .LBB0_2: ; %endif ; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0x3d08fc, v0 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_store_dword v[0:1], v4 +; GFX8-NEXT: flat_store_dword v[0:1], v5 ; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: test_sinkable_flat_small_offset_i32: ; GFX9: ; %bb.0: ; %entry ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v5, 0 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX9-NEXT: s_cbranch_execz .LBB0_2 ; GFX9-NEXT: ; %bb.1: ; %if -; GFX9-NEXT: flat_load_dword v4, v[2:3] offset:28 +; GFX9-NEXT: flat_load_dword v5, v[2:3] offset:28 ; GFX9-NEXT: .LBB0_2: ; %endif ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x3d0000, v0 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: flat_store_dword v[0:1], v4 offset:2300 +; GFX9-NEXT: flat_store_dword v[0:1], v5 offset:2300 ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: test_sinkable_flat_small_offset_i32: ; GFX10: ; %bb.0: ; %entry ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_mov_b32_e32 v4, 0 -; GFX10-NEXT: s_and_saveexec_b32 s4, vcc_lo +; GFX10-NEXT: v_mov_b32_e32 v5, 0 +; GFX10-NEXT: s_mov_b32 s4, exec_lo +; GFX10-NEXT: v_cmpx_ne_u32_e32 0, v4 ; GFX10-NEXT: s_cbranch_execz .LBB0_2 ; GFX10-NEXT: ; %bb.1: ; %if -; GFX10-NEXT: flat_load_dword v4, v[2:3] offset:28 +; GFX10-NEXT: flat_load_dword v5, v[2:3] offset:28 ; GFX10-NEXT: .LBB0_2: ; %endif ; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x3d0800, v0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX10-NEXT: flat_store_dword v[0:1], v4 offset:252 +; GFX10-NEXT: flat_store_dword v[0:1], v5 offset:252 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_setpc_b64 s[30:31] entry: @@ -228,78 +228,78 @@ define void @test_sink_noop_addrspacecast_flat_to_global_i32(ptr %out, ptr %in, ; GFX7-LABEL: test_sink_noop_addrspacecast_flat_to_global_i32: ; GFX7: ; %bb.0: ; %entry ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: s_mov_b32 s6, 0 +; GFX7-NEXT: v_mov_b32_e32 v5, 0 ; GFX7-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; GFX7-NEXT: v_mov_b32_e32 v4, 0 -; GFX7-NEXT: s_and_saveexec_b64 s[8:9], vcc +; GFX7-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX7-NEXT: s_cbranch_execz .LBB1_2 ; GFX7-NEXT: ; %bb.1: ; %if -; GFX7-NEXT: s_mov_b32 s7, 0xf000 -; GFX7-NEXT: s_mov_b32 s4, s6 -; GFX7-NEXT: s_mov_b32 s5, s6 -; GFX7-NEXT: buffer_load_dword v4, v[2:3], s[4:7], 0 addr64 offset:28 +; GFX7-NEXT: s_mov_b32 s10, 0 +; GFX7-NEXT: s_mov_b32 s11, 0xf000 +; GFX7-NEXT: s_mov_b32 s8, s10 +; GFX7-NEXT: s_mov_b32 s9, s10 +; GFX7-NEXT: buffer_load_dword v5, v[2:3], s[8:11], 0 addr64 offset:28 ; GFX7-NEXT: .LBB1_2: ; %endif -; GFX7-NEXT: s_or_b64 exec, exec, s[8:9] +; GFX7-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX7-NEXT: v_add_i32_e32 v0, vcc, 0x3d08fc, v0 ; GFX7-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v4 +; GFX7-NEXT: flat_store_dword v[0:1], v5 ; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: test_sink_noop_addrspacecast_flat_to_global_i32: ; GFX8: ; %bb.0: ; %entry ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v5, 0 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; GFX8-NEXT: v_mov_b32_e32 v4, 0 ; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX8-NEXT: s_cbranch_execz .LBB1_2 ; GFX8-NEXT: ; %bb.1: ; %if ; GFX8-NEXT: v_add_u32_e32 v2, vcc, 28, v2 ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; GFX8-NEXT: flat_load_dword v4, v[2:3] +; GFX8-NEXT: flat_load_dword v5, v[2:3] ; GFX8-NEXT: .LBB1_2: ; %endif ; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0x3d08fc, v0 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: flat_store_dword v[0:1], v4 +; GFX8-NEXT: flat_store_dword v[0:1], v5 ; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: test_sink_noop_addrspacecast_flat_to_global_i32: ; GFX9: ; %bb.0: ; %entry ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v5, 0 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX9-NEXT: s_cbranch_execz .LBB1_2 ; GFX9-NEXT: ; %bb.1: ; %if -; GFX9-NEXT: global_load_dword v4, v[2:3], off offset:28 +; GFX9-NEXT: global_load_dword v5, v[2:3], off offset:28 ; GFX9-NEXT: .LBB1_2: ; %endif ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x3d0000, v0 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: flat_store_dword v[0:1], v4 offset:2300 +; GFX9-NEXT: flat_store_dword v[0:1], v5 offset:2300 ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: test_sink_noop_addrspacecast_flat_to_global_i32: ; GFX10: ; %bb.0: ; %entry ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_mov_b32_e32 v4, 0 -; GFX10-NEXT: s_and_saveexec_b32 s4, vcc_lo +; GFX10-NEXT: v_mov_b32_e32 v5, 0 +; GFX10-NEXT: s_mov_b32 s4, exec_lo +; GFX10-NEXT: v_cmpx_ne_u32_e32 0, v4 ; GFX10-NEXT: s_cbranch_execz .LBB1_2 ; GFX10-NEXT: ; %bb.1: ; %if -; GFX10-NEXT: global_load_dword v4, v[2:3], off offset:28 +; GFX10-NEXT: global_load_dword v5, v[2:3], off offset:28 ; GFX10-NEXT: .LBB1_2: ; %endif ; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x3d0800, v0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: flat_store_dword v[0:1], v4 offset:252 +; GFX10-NEXT: flat_store_dword v[0:1], v5 offset:252 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_setpc_b64 s[30:31] entry: @@ -341,78 +341,78 @@ define void @test_sink_noop_addrspacecast_flat_to_constant_i32(ptr %out, ptr %in ; GFX7-LABEL: test_sink_noop_addrspacecast_flat_to_constant_i32: ; GFX7: ; %bb.0: ; %entry ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: s_mov_b32 s6, 0 +; GFX7-NEXT: v_mov_b32_e32 v5, 0 ; GFX7-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; GFX7-NEXT: v_mov_b32_e32 v4, 0 -; GFX7-NEXT: s_and_saveexec_b64 s[8:9], vcc +; GFX7-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX7-NEXT: s_cbranch_execz .LBB2_2 ; GFX7-NEXT: ; %bb.1: ; %if -; GFX7-NEXT: s_mov_b32 s7, 0xf000 -; GFX7-NEXT: s_mov_b32 s4, s6 -; GFX7-NEXT: s_mov_b32 s5, s6 -; GFX7-NEXT: buffer_load_dword v4, v[2:3], s[4:7], 0 addr64 offset:28 +; GFX7-NEXT: s_mov_b32 s10, 0 +; GFX7-NEXT: s_mov_b32 s11, 0xf000 +; GFX7-NEXT: s_mov_b32 s8, s10 +; GFX7-NEXT: s_mov_b32 s9, s10 +; GFX7-NEXT: buffer_load_dword v5, v[2:3], s[8:11], 0 addr64 offset:28 ; GFX7-NEXT: .LBB2_2: ; %endif -; GFX7-NEXT: s_or_b64 exec, exec, s[8:9] +; GFX7-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX7-NEXT: v_add_i32_e32 v0, vcc, 0x3d08fc, v0 ; GFX7-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v4 +; GFX7-NEXT: flat_store_dword v[0:1], v5 ; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: test_sink_noop_addrspacecast_flat_to_constant_i32: ; GFX8: ; %bb.0: ; %entry ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v5, 0 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; GFX8-NEXT: v_mov_b32_e32 v4, 0 ; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX8-NEXT: s_cbranch_execz .LBB2_2 ; GFX8-NEXT: ; %bb.1: ; %if ; GFX8-NEXT: v_add_u32_e32 v2, vcc, 28, v2 ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; GFX8-NEXT: flat_load_dword v4, v[2:3] +; GFX8-NEXT: flat_load_dword v5, v[2:3] ; GFX8-NEXT: .LBB2_2: ; %endif ; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0x3d08fc, v0 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: flat_store_dword v[0:1], v4 +; GFX8-NEXT: flat_store_dword v[0:1], v5 ; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: test_sink_noop_addrspacecast_flat_to_constant_i32: ; GFX9: ; %bb.0: ; %entry ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v5, 0 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX9-NEXT: s_cbranch_execz .LBB2_2 ; GFX9-NEXT: ; %bb.1: ; %if -; GFX9-NEXT: global_load_dword v4, v[2:3], off offset:28 +; GFX9-NEXT: global_load_dword v5, v[2:3], off offset:28 ; GFX9-NEXT: .LBB2_2: ; %endif ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x3d0000, v0 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: flat_store_dword v[0:1], v4 offset:2300 +; GFX9-NEXT: flat_store_dword v[0:1], v5 offset:2300 ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: test_sink_noop_addrspacecast_flat_to_constant_i32: ; GFX10: ; %bb.0: ; %entry ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_mov_b32_e32 v4, 0 -; GFX10-NEXT: s_and_saveexec_b32 s4, vcc_lo +; GFX10-NEXT: v_mov_b32_e32 v5, 0 +; GFX10-NEXT: s_mov_b32 s4, exec_lo +; GFX10-NEXT: v_cmpx_ne_u32_e32 0, v4 ; GFX10-NEXT: s_cbranch_execz .LBB2_2 ; GFX10-NEXT: ; %bb.1: ; %if -; GFX10-NEXT: global_load_dword v4, v[2:3], off offset:28 +; GFX10-NEXT: global_load_dword v5, v[2:3], off offset:28 ; GFX10-NEXT: .LBB2_2: ; %endif ; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x3d0800, v0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: flat_store_dword v[0:1], v4 offset:252 +; GFX10-NEXT: flat_store_dword v[0:1], v5 offset:252 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_setpc_b64 s[30:31] entry: @@ -570,10 +570,10 @@ define void @test_sink_flat_small_max_flat_offset(ptr %out, ptr %in) #1 { ; GFX10-LABEL: test_sink_flat_small_max_flat_offset: ; GFX10: ; %bb.0: ; %entry ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_mbcnt_lo_u32_b32 v4, -1, 0 -; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4 +; GFX10-NEXT: v_mbcnt_lo_u32_b32 v5, -1, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0 -; GFX10-NEXT: s_and_saveexec_b32 s4, vcc_lo +; GFX10-NEXT: s_mov_b32 s4, exec_lo +; GFX10-NEXT: v_cmpx_ne_u32_e32 0, v5 ; GFX10-NEXT: s_cbranch_execz .LBB3_2 ; GFX10-NEXT: ; %bb.1: ; %if ; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, 0x800, v2 @@ -693,10 +693,10 @@ define void @test_sink_flat_small_max_plus_1_flat_offset(ptr %out, ptr %in) #1 { ; GFX10-LABEL: test_sink_flat_small_max_plus_1_flat_offset: ; GFX10: ; %bb.0: ; %entry ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_mbcnt_lo_u32_b32 v4, -1, 0 -; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4 +; GFX10-NEXT: v_mbcnt_lo_u32_b32 v5, -1, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0 -; GFX10-NEXT: s_and_saveexec_b32 s4, vcc_lo +; GFX10-NEXT: s_mov_b32 s4, exec_lo +; GFX10-NEXT: v_cmpx_ne_u32_e32 0, v5 ; GFX10-NEXT: s_cbranch_execz .LBB4_2 ; GFX10-NEXT: ; %bb.1: ; %if ; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, 0x1000, v2 @@ -816,10 +816,10 @@ define void @test_sinkable_flat_reg_offset(ptr %out, ptr %in, i64 %reg) #1 { ; GFX10-LABEL: test_sinkable_flat_reg_offset: ; GFX10: ; %bb.0: ; %entry ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_mbcnt_lo_u32_b32 v6, -1, 0 -; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6 +; GFX10-NEXT: v_mbcnt_lo_u32_b32 v7, -1, 0 ; GFX10-NEXT: v_mov_b32_e32 v6, 0 -; GFX10-NEXT: s_and_saveexec_b32 s4, vcc_lo +; GFX10-NEXT: s_mov_b32 s4, exec_lo +; GFX10-NEXT: v_cmpx_ne_u32_e32 0, v7 ; GFX10-NEXT: s_cbranch_execz .LBB5_2 ; GFX10-NEXT: ; %bb.1: ; %if ; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4 diff --git a/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll b/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll index b44f8ca87fd8b..81f768f303ca1 100644 --- a/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll +++ b/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: opt -S -passes='require,function(codegenprepare)' -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefix=OPT %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefix=GCN %s @@ -25,10 +25,10 @@ define amdgpu_kernel void @test_sink_small_offset_global_atomic_csub_i32(ptr add ; GCN-LABEL: test_sink_small_offset_global_atomic_csub_i32: ; GCN: ; %bb.0: ; %entry ; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 -; GCN-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0 -; GCN-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GCN-NEXT: v_mbcnt_lo_u32_b32 v1, -1, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0 -; GCN-NEXT: s_and_saveexec_b32 s4, vcc_lo +; GCN-NEXT: s_mov_b32 s4, exec_lo +; GCN-NEXT: v_cmpx_ne_u32_e32 0, v1 ; GCN-NEXT: s_cbranch_execz .LBB0_2 ; GCN-NEXT: ; %bb.1: ; %if ; GCN-NEXT: v_mov_b32_e32 v0, 0 diff --git a/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll b/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll index 50c9c0cb64ccd..a47ecb2c5d7f2 100644 --- a/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll +++ b/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll @@ -981,21 +981,21 @@ define void @scc_liveness(i32 %arg) local_unnamed_addr #0 { ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_movk_i32 s4, 0x207 ; GCN-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0 -; GCN-NEXT: s_mov_b32 s8, 0 ; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 -; GCN-NEXT: s_mov_b64 s[12:13], 0 +; GCN-NEXT: s_mov_b64 s[8:9], 0 +; GCN-NEXT: v_mov_b32_e32 v7, 0 ; GCN-NEXT: s_mov_b64 s[6:7], 0 ; GCN-NEXT: s_branch .LBB5_3 ; GCN-NEXT: .LBB5_1: ; %Flow ; GCN-NEXT: ; in Loop: Header=BB5_3 Depth=1 -; GCN-NEXT: s_or_b64 exec, exec, s[10:11] +; GCN-NEXT: s_or_b64 exec, exec, s[12:13] ; GCN-NEXT: .LBB5_2: ; %bb10 ; GCN-NEXT: ; in Loop: Header=BB5_3 Depth=1 -; GCN-NEXT: s_or_b64 exec, exec, s[14:15] +; GCN-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-NEXT: s_and_b64 s[6:7], exec, s[4:5] -; GCN-NEXT: s_or_b64 s[12:13], s[6:7], s[12:13] +; GCN-NEXT: s_or_b64 s[8:9], s[6:7], s[8:9] ; GCN-NEXT: s_mov_b64 s[6:7], 0 -; GCN-NEXT: s_andn2_b64 exec, exec, s[12:13] +; GCN-NEXT: s_andn2_b64 exec, exec, s[8:9] ; GCN-NEXT: s_cbranch_execz .LBB5_7 ; GCN-NEXT: .LBB5_3: ; %bb1 ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -1006,43 +1006,36 @@ define void @scc_liveness(i32 %arg) local_unnamed_addr #0 { ; GCN-NEXT: ; %bb.4: ; %bb2 ; GCN-NEXT: ; in Loop: Header=BB5_3 Depth=1 ; GCN-NEXT: s_or_b64 exec, exec, s[6:7] -; GCN-NEXT: s_mov_b32 s9, s8 -; GCN-NEXT: s_mov_b32 s10, s8 -; GCN-NEXT: s_mov_b32 s11, s8 -; GCN-NEXT: v_mov_b32_e32 v0, s8 -; GCN-NEXT: v_mov_b32_e32 v1, s9 -; GCN-NEXT: v_mov_b32_e32 v2, s10 -; GCN-NEXT: v_mov_b32_e32 v3, s11 -; GCN-NEXT: s_and_saveexec_b64 s[14:15], s[4:5] +; GCN-NEXT: v_mov_b32_e32 v8, v7 +; GCN-NEXT: v_mov_b32_e32 v2, v7 +; GCN-NEXT: v_mov_b32_e32 v6, v7 +; GCN-NEXT: s_and_saveexec_b64 s[10:11], s[4:5] ; GCN-NEXT: s_cbranch_execz .LBB5_2 ; GCN-NEXT: ; %bb.5: ; %bb4 ; GCN-NEXT: ; in Loop: Header=BB5_3 Depth=1 ; GCN-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen +; GCN-NEXT: v_mov_b32_e32 v8, v7 +; GCN-NEXT: v_mov_b32_e32 v2, v7 +; GCN-NEXT: v_mov_b32_e32 v6, v7 ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: v_cmp_gt_f32_e64 s[6:7], 0, v0 -; GCN-NEXT: v_mov_b32_e32 v0, s8 -; GCN-NEXT: v_mov_b32_e32 v1, s9 -; GCN-NEXT: v_mov_b32_e32 v2, s10 -; GCN-NEXT: v_mov_b32_e32 v3, s11 -; GCN-NEXT: s_and_saveexec_b64 s[10:11], s[6:7] +; GCN-NEXT: s_and_saveexec_b64 s[12:13], s[6:7] ; GCN-NEXT: s_cbranch_execz .LBB5_1 ; GCN-NEXT: ; %bb.6: ; %bb8 ; GCN-NEXT: ; in Loop: Header=BB5_3 Depth=1 -; GCN-NEXT: s_mov_b32 s9, s8 -; GCN-NEXT: v_mov_b32_e32 v0, s8 -; GCN-NEXT: v_mov_b32_e32 v1, s9 -; GCN-NEXT: v_mov_b32_e32 v2, s10 -; GCN-NEXT: v_mov_b32_e32 v3, s11 +; GCN-NEXT: v_mov_b32_e32 v8, v7 +; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3 +; GCN-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6 ; GCN-NEXT: s_branch .LBB5_1 ; GCN-NEXT: .LBB5_7: ; %bb12 -; GCN-NEXT: s_or_b64 exec, exec, s[12:13] -; GCN-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen +; GCN-NEXT: s_or_b64 exec, exec, s[8:9] +; GCN-NEXT: buffer_store_dword v6, v0, s[0:3], 0 offen ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen +; GCN-NEXT: buffer_store_dword v8, v0, s[0:3], 0 offen ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: buffer_store_dword v0, v0, s[0:3], 0 offen +; GCN-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; GCN-NEXT: s_setpc_b64 s[30:31] ; @@ -1050,47 +1043,47 @@ define void @scc_liveness(i32 %arg) local_unnamed_addr #0 { ; GCN-O0: ; %bb.0: ; %bb ; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; GCN-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GCN-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill ; GCN-O0-NEXT: s_mov_b64 exec, s[4:5] ; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GCN-O0-NEXT: s_mov_b64 s[4:5], 0 ; GCN-O0-NEXT: s_mov_b64 s[6:7], s[4:5] -; GCN-O0-NEXT: ; implicit-def: $vgpr6 : SGPR spill to VGPR lane +; GCN-O0-NEXT: ; implicit-def: $vgpr7 : SGPR spill to VGPR lane ; GCN-O0-NEXT: s_waitcnt expcnt(1) -; GCN-O0-NEXT: v_writelane_b32 v6, s6, 0 -; GCN-O0-NEXT: v_writelane_b32 v6, s7, 1 -; GCN-O0-NEXT: v_writelane_b32 v6, s4, 2 -; GCN-O0-NEXT: v_writelane_b32 v6, s5, 3 +; GCN-O0-NEXT: v_writelane_b32 v7, s6, 0 +; GCN-O0-NEXT: v_writelane_b32 v7, s7, 1 +; GCN-O0-NEXT: v_writelane_b32 v7, s4, 2 +; GCN-O0-NEXT: v_writelane_b32 v7, s5, 3 ; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1 -; GCN-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 ; 4-byte Folded Spill +; GCN-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 ; 4-byte Folded Spill ; GCN-O0-NEXT: s_mov_b64 exec, s[14:15] ; GCN-O0-NEXT: .LBB5_1: ; %bb1 ; GCN-O0-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1 ; GCN-O0-NEXT: s_waitcnt expcnt(0) -; GCN-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 ; 4-byte Folded Reload +; GCN-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 ; 4-byte Folded Reload ; GCN-O0-NEXT: s_mov_b64 exec, s[14:15] ; GCN-O0-NEXT: s_waitcnt vmcnt(0) -; GCN-O0-NEXT: v_readlane_b32 s8, v6, 2 -; GCN-O0-NEXT: v_readlane_b32 s9, v6, 3 -; GCN-O0-NEXT: v_readlane_b32 s6, v6, 0 -; GCN-O0-NEXT: v_readlane_b32 s7, v6, 1 -; GCN-O0-NEXT: v_writelane_b32 v6, s6, 4 -; GCN-O0-NEXT: v_writelane_b32 v6, s7, 5 +; GCN-O0-NEXT: v_readlane_b32 s8, v7, 2 +; GCN-O0-NEXT: v_readlane_b32 s9, v7, 3 +; GCN-O0-NEXT: v_readlane_b32 s6, v7, 0 +; GCN-O0-NEXT: v_readlane_b32 s7, v7, 1 +; GCN-O0-NEXT: v_writelane_b32 v7, s6, 4 +; GCN-O0-NEXT: v_writelane_b32 v7, s7, 5 ; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload ; GCN-O0-NEXT: s_mov_b32 s4, 0x207 ; GCN-O0-NEXT: s_waitcnt vmcnt(0) ; GCN-O0-NEXT: v_cmp_lt_i32_e64 s[4:5], v0, s4 ; GCN-O0-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9] -; GCN-O0-NEXT: v_writelane_b32 v6, s4, 6 -; GCN-O0-NEXT: v_writelane_b32 v6, s5, 7 -; GCN-O0-NEXT: v_writelane_b32 v6, s6, 0 -; GCN-O0-NEXT: v_writelane_b32 v6, s7, 1 +; GCN-O0-NEXT: v_writelane_b32 v7, s4, 6 +; GCN-O0-NEXT: v_writelane_b32 v7, s5, 7 +; GCN-O0-NEXT: v_writelane_b32 v7, s6, 0 +; GCN-O0-NEXT: v_writelane_b32 v7, s7, 1 ; GCN-O0-NEXT: s_mov_b64 s[6:7], s[4:5] -; GCN-O0-NEXT: v_writelane_b32 v6, s6, 2 -; GCN-O0-NEXT: v_writelane_b32 v6, s7, 3 +; GCN-O0-NEXT: v_writelane_b32 v7, s6, 2 +; GCN-O0-NEXT: v_writelane_b32 v7, s7, 3 ; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1 -; GCN-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 ; 4-byte Folded Spill +; GCN-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 ; 4-byte Folded Spill ; GCN-O0-NEXT: s_mov_b64 exec, s[14:15] ; GCN-O0-NEXT: s_andn2_b64 exec, exec, s[4:5] ; GCN-O0-NEXT: s_cbranch_execnz .LBB5_1 @@ -1098,37 +1091,37 @@ define void @scc_liveness(i32 %arg) local_unnamed_addr #0 { ; GCN-O0-NEXT: ; in Loop: Header=BB5_1 Depth=1 ; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1 ; GCN-O0-NEXT: s_waitcnt expcnt(0) -; GCN-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 ; 4-byte Folded Reload +; GCN-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 ; 4-byte Folded Reload ; GCN-O0-NEXT: s_mov_b64 exec, s[14:15] ; GCN-O0-NEXT: s_waitcnt vmcnt(0) -; GCN-O0-NEXT: v_readlane_b32 s4, v6, 6 -; GCN-O0-NEXT: v_readlane_b32 s5, v6, 7 +; GCN-O0-NEXT: v_readlane_b32 s4, v7, 6 +; GCN-O0-NEXT: v_readlane_b32 s5, v7, 7 ; GCN-O0-NEXT: s_or_b64 exec, exec, s[4:5] ; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload ; GCN-O0-NEXT: s_mov_b32 s6, 0 ; GCN-O0-NEXT: s_waitcnt vmcnt(0) ; GCN-O0-NEXT: v_cmp_ne_u32_e64 s[4:5], v0, s6 ; GCN-O0-NEXT: v_cmp_eq_u32_e64 s[6:7], v0, s6 -; GCN-O0-NEXT: v_writelane_b32 v6, s4, 8 -; GCN-O0-NEXT: v_writelane_b32 v6, s5, 9 +; GCN-O0-NEXT: v_writelane_b32 v7, s4, 8 +; GCN-O0-NEXT: v_writelane_b32 v7, s5, 9 ; GCN-O0-NEXT: s_mov_b32 s4, 0 -; GCN-O0-NEXT: s_mov_b32 s8, s4 -; GCN-O0-NEXT: s_mov_b32 s9, s4 -; GCN-O0-NEXT: s_mov_b32 s10, s4 -; GCN-O0-NEXT: s_mov_b32 s11, s4 -; GCN-O0-NEXT: v_mov_b32_e32 v0, s8 -; GCN-O0-NEXT: v_mov_b32_e32 v1, s9 -; GCN-O0-NEXT: v_mov_b32_e32 v2, s10 -; GCN-O0-NEXT: v_mov_b32_e32 v3, s11 +; GCN-O0-NEXT: v_mov_b32_e32 v0, s4 +; GCN-O0-NEXT: v_mov_b32_e32 v6, s4 +; GCN-O0-NEXT: v_mov_b32_e32 v5, s4 +; GCN-O0-NEXT: v_mov_b32_e32 v4, s4 +; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3 killed $exec +; GCN-O0-NEXT: v_mov_b32_e32 v1, v6 +; GCN-O0-NEXT: v_mov_b32_e32 v2, v5 +; GCN-O0-NEXT: v_mov_b32_e32 v3, v4 ; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; GCN-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill ; GCN-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill ; GCN-O0-NEXT: s_mov_b64 s[4:5], exec -; GCN-O0-NEXT: v_writelane_b32 v6, s4, 10 -; GCN-O0-NEXT: v_writelane_b32 v6, s5, 11 +; GCN-O0-NEXT: v_writelane_b32 v7, s4, 10 +; GCN-O0-NEXT: v_writelane_b32 v7, s5, 11 ; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1 -; GCN-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 ; 4-byte Folded Spill +; GCN-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 ; 4-byte Folded Spill ; GCN-O0-NEXT: s_mov_b64 exec, s[14:15] ; GCN-O0-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7] ; GCN-O0-NEXT: s_mov_b64 exec, s[4:5] @@ -1137,7 +1130,7 @@ define void @scc_liveness(i32 %arg) local_unnamed_addr #0 { ; GCN-O0-NEXT: ; in Loop: Header=BB5_1 Depth=1 ; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1 ; GCN-O0-NEXT: s_waitcnt expcnt(0) -; GCN-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 ; 4-byte Folded Reload +; GCN-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 ; 4-byte Folded Reload ; GCN-O0-NEXT: s_mov_b64 exec, s[14:15] ; GCN-O0-NEXT: ; implicit-def: $sgpr4 ; GCN-O0-NEXT: v_mov_b32_e32 v0, s4 @@ -1145,23 +1138,23 @@ define void @scc_liveness(i32 %arg) local_unnamed_addr #0 { ; GCN-O0-NEXT: s_mov_b32 s4, 0 ; GCN-O0-NEXT: s_waitcnt vmcnt(0) ; GCN-O0-NEXT: v_cmp_lt_f32_e64 s[6:7], v0, s4 -; GCN-O0-NEXT: s_mov_b32 s8, s4 -; GCN-O0-NEXT: s_mov_b32 s9, s4 -; GCN-O0-NEXT: s_mov_b32 s10, s4 -; GCN-O0-NEXT: s_mov_b32 s11, s4 -; GCN-O0-NEXT: v_mov_b32_e32 v0, s8 -; GCN-O0-NEXT: v_mov_b32_e32 v1, s9 -; GCN-O0-NEXT: v_mov_b32_e32 v2, s10 -; GCN-O0-NEXT: v_mov_b32_e32 v3, s11 +; GCN-O0-NEXT: v_mov_b32_e32 v0, s4 +; GCN-O0-NEXT: v_mov_b32_e32 v6, s4 +; GCN-O0-NEXT: v_mov_b32_e32 v5, s4 +; GCN-O0-NEXT: v_mov_b32_e32 v4, s4 +; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3 killed $exec +; GCN-O0-NEXT: v_mov_b32_e32 v1, v6 +; GCN-O0-NEXT: v_mov_b32_e32 v2, v5 +; GCN-O0-NEXT: v_mov_b32_e32 v3, v4 ; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill ; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill ; GCN-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill ; GCN-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill ; GCN-O0-NEXT: s_mov_b64 s[4:5], exec -; GCN-O0-NEXT: v_writelane_b32 v6, s4, 12 -; GCN-O0-NEXT: v_writelane_b32 v6, s5, 13 +; GCN-O0-NEXT: v_writelane_b32 v7, s4, 12 +; GCN-O0-NEXT: v_writelane_b32 v7, s5, 13 ; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1 -; GCN-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 ; 4-byte Folded Spill +; GCN-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 ; 4-byte Folded Spill ; GCN-O0-NEXT: s_mov_b64 exec, s[14:15] ; GCN-O0-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7] ; GCN-O0-NEXT: s_mov_b64 exec, s[4:5] @@ -1193,11 +1186,11 @@ define void @scc_liveness(i32 %arg) local_unnamed_addr #0 { ; GCN-O0-NEXT: ; in Loop: Header=BB5_1 Depth=1 ; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1 ; GCN-O0-NEXT: s_waitcnt expcnt(0) -; GCN-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 ; 4-byte Folded Reload +; GCN-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 ; 4-byte Folded Reload ; GCN-O0-NEXT: s_mov_b64 exec, s[14:15] ; GCN-O0-NEXT: s_waitcnt vmcnt(0) -; GCN-O0-NEXT: v_readlane_b32 s4, v6, 10 -; GCN-O0-NEXT: v_readlane_b32 s5, v6, 11 +; GCN-O0-NEXT: v_readlane_b32 s4, v7, 10 +; GCN-O0-NEXT: v_readlane_b32 s5, v7, 11 ; GCN-O0-NEXT: s_or_b64 exec, exec, s[4:5] ; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload ; GCN-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload @@ -1216,11 +1209,11 @@ define void @scc_liveness(i32 %arg) local_unnamed_addr #0 { ; GCN-O0-NEXT: ; in Loop: Header=BB5_1 Depth=1 ; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1 ; GCN-O0-NEXT: s_waitcnt expcnt(0) -; GCN-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 ; 4-byte Folded Reload +; GCN-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 ; 4-byte Folded Reload ; GCN-O0-NEXT: s_mov_b64 exec, s[14:15] ; GCN-O0-NEXT: s_waitcnt vmcnt(0) -; GCN-O0-NEXT: v_readlane_b32 s4, v6, 12 -; GCN-O0-NEXT: v_readlane_b32 s5, v6, 13 +; GCN-O0-NEXT: v_readlane_b32 s4, v7, 12 +; GCN-O0-NEXT: v_readlane_b32 s5, v7, 13 ; GCN-O0-NEXT: s_or_b64 exec, exec, s[4:5] ; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload ; GCN-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload @@ -1238,19 +1231,19 @@ define void @scc_liveness(i32 %arg) local_unnamed_addr #0 { ; GCN-O0-NEXT: .LBB5_7: ; %bb10 ; GCN-O0-NEXT: ; in Loop: Header=BB5_1 Depth=1 ; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1 -; GCN-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 ; 4-byte Folded Reload +; GCN-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 ; 4-byte Folded Reload ; GCN-O0-NEXT: s_mov_b64 exec, s[14:15] ; GCN-O0-NEXT: s_waitcnt vmcnt(0) -; GCN-O0-NEXT: v_readlane_b32 s6, v6, 8 -; GCN-O0-NEXT: v_readlane_b32 s7, v6, 9 +; GCN-O0-NEXT: v_readlane_b32 s6, v7, 8 +; GCN-O0-NEXT: v_readlane_b32 s7, v7, 9 ; GCN-O0-NEXT: s_mov_b64 s[4:5], -1 -; GCN-O0-NEXT: v_writelane_b32 v6, s4, 14 -; GCN-O0-NEXT: v_writelane_b32 v6, s5, 15 +; GCN-O0-NEXT: v_writelane_b32 v7, s4, 14 +; GCN-O0-NEXT: v_writelane_b32 v7, s5, 15 ; GCN-O0-NEXT: s_mov_b64 s[4:5], exec -; GCN-O0-NEXT: v_writelane_b32 v6, s4, 16 -; GCN-O0-NEXT: v_writelane_b32 v6, s5, 17 +; GCN-O0-NEXT: v_writelane_b32 v7, s4, 16 +; GCN-O0-NEXT: v_writelane_b32 v7, s5, 17 ; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1 -; GCN-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 ; 4-byte Folded Spill +; GCN-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 ; 4-byte Folded Spill ; GCN-O0-NEXT: s_mov_b64 exec, s[14:15] ; GCN-O0-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7] ; GCN-O0-NEXT: s_mov_b64 exec, s[4:5] @@ -1259,30 +1252,30 @@ define void @scc_liveness(i32 %arg) local_unnamed_addr #0 { ; GCN-O0-NEXT: ; in Loop: Header=BB5_1 Depth=1 ; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1 ; GCN-O0-NEXT: s_waitcnt expcnt(0) -; GCN-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 ; 4-byte Folded Reload +; GCN-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 ; 4-byte Folded Reload ; GCN-O0-NEXT: s_mov_b64 exec, s[14:15] ; GCN-O0-NEXT: s_mov_b64 s[4:5], 0 ; GCN-O0-NEXT: s_xor_b64 s[4:5], exec, -1 ; GCN-O0-NEXT: s_waitcnt vmcnt(0) -; GCN-O0-NEXT: v_writelane_b32 v6, s4, 14 -; GCN-O0-NEXT: v_writelane_b32 v6, s5, 15 +; GCN-O0-NEXT: v_writelane_b32 v7, s4, 14 +; GCN-O0-NEXT: v_writelane_b32 v7, s5, 15 ; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1 -; GCN-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 ; 4-byte Folded Spill +; GCN-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 ; 4-byte Folded Spill ; GCN-O0-NEXT: s_mov_b64 exec, s[14:15] ; GCN-O0-NEXT: .LBB5_9: ; %Flow3 ; GCN-O0-NEXT: ; in Loop: Header=BB5_1 Depth=1 ; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1 ; GCN-O0-NEXT: s_waitcnt expcnt(0) -; GCN-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 ; 4-byte Folded Reload +; GCN-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 ; 4-byte Folded Reload ; GCN-O0-NEXT: s_mov_b64 exec, s[14:15] ; GCN-O0-NEXT: s_waitcnt vmcnt(0) -; GCN-O0-NEXT: v_readlane_b32 s8, v6, 16 -; GCN-O0-NEXT: v_readlane_b32 s9, v6, 17 +; GCN-O0-NEXT: v_readlane_b32 s8, v7, 16 +; GCN-O0-NEXT: v_readlane_b32 s9, v7, 17 ; GCN-O0-NEXT: s_or_b64 exec, exec, s[8:9] -; GCN-O0-NEXT: v_readlane_b32 s6, v6, 4 -; GCN-O0-NEXT: v_readlane_b32 s7, v6, 5 -; GCN-O0-NEXT: v_readlane_b32 s4, v6, 14 -; GCN-O0-NEXT: v_readlane_b32 s5, v6, 15 +; GCN-O0-NEXT: v_readlane_b32 s6, v7, 4 +; GCN-O0-NEXT: v_readlane_b32 s7, v7, 5 +; GCN-O0-NEXT: v_readlane_b32 s4, v7, 14 +; GCN-O0-NEXT: v_readlane_b32 s5, v7, 15 ; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload ; GCN-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload ; GCN-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload @@ -1291,15 +1284,15 @@ define void @scc_liveness(i32 %arg) local_unnamed_addr #0 { ; GCN-O0-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] ; GCN-O0-NEXT: s_mov_b64 s[6:7], 0 ; GCN-O0-NEXT: s_mov_b64 s[8:9], s[4:5] -; GCN-O0-NEXT: v_writelane_b32 v6, s8, 0 -; GCN-O0-NEXT: v_writelane_b32 v6, s9, 1 -; GCN-O0-NEXT: v_writelane_b32 v6, s6, 2 -; GCN-O0-NEXT: v_writelane_b32 v6, s7, 3 +; GCN-O0-NEXT: v_writelane_b32 v7, s8, 0 +; GCN-O0-NEXT: v_writelane_b32 v7, s9, 1 +; GCN-O0-NEXT: v_writelane_b32 v7, s6, 2 +; GCN-O0-NEXT: v_writelane_b32 v7, s7, 3 ; GCN-O0-NEXT: s_mov_b64 s[6:7], s[4:5] -; GCN-O0-NEXT: v_writelane_b32 v6, s6, 18 -; GCN-O0-NEXT: v_writelane_b32 v6, s7, 19 +; GCN-O0-NEXT: v_writelane_b32 v7, s6, 18 +; GCN-O0-NEXT: v_writelane_b32 v7, s7, 19 ; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1 -; GCN-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 ; 4-byte Folded Spill +; GCN-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 ; 4-byte Folded Spill ; GCN-O0-NEXT: s_mov_b64 exec, s[14:15] ; GCN-O0-NEXT: s_waitcnt vmcnt(4) ; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill @@ -1314,11 +1307,11 @@ define void @scc_liveness(i32 %arg) local_unnamed_addr #0 { ; GCN-O0-NEXT: ; %bb.10: ; %bb12 ; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1 ; GCN-O0-NEXT: s_waitcnt expcnt(4) -; GCN-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 ; 4-byte Folded Reload +; GCN-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 ; 4-byte Folded Reload ; GCN-O0-NEXT: s_mov_b64 exec, s[14:15] ; GCN-O0-NEXT: s_waitcnt vmcnt(0) -; GCN-O0-NEXT: v_readlane_b32 s4, v6, 18 -; GCN-O0-NEXT: v_readlane_b32 s5, v6, 19 +; GCN-O0-NEXT: v_readlane_b32 s4, v7, 18 +; GCN-O0-NEXT: v_readlane_b32 s5, v7, 19 ; GCN-O0-NEXT: s_or_b64 exec, exec, s[4:5] ; GCN-O0-NEXT: ; %bb.11: ; %bb12 ; GCN-O0-NEXT: s_waitcnt expcnt(3) @@ -1351,7 +1344,7 @@ define void @scc_liveness(i32 %arg) local_unnamed_addr #0 { ; GCN-O0-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen ; GCN-O0-NEXT: s_waitcnt vmcnt(0) ; GCN-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; GCN-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GCN-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload ; GCN-O0-NEXT: s_mov_b64 exec, s[4:5] ; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; GCN-O0-NEXT: s_setpc_b64 s[30:31] diff --git a/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll b/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll index 08644572372c3..d6fb86dbd418e 100644 --- a/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll +++ b/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll @@ -17,7 +17,7 @@ ; Spill load ; GCN: buffer_store_dword [[LOAD0]], off, s[0:3], 0 offset:[[LOAD0_OFFSET:[0-9]+]] ; 4-byte Folded Spill -; GCN: v_cmp_eq_u32_e64 [[CMP0:s\[[0-9]+:[0-9]\]]], v{{[0-9]+}}, s{{[0-9]+}} +; GCN: v_cmp_eq_u32_e64 [[CMP0:s\[[0-9]+:[0-9]\]]], v{{[0-9]+}}, v{{[0-9]+}} ; Spill saved exec ; GCN: s_mov_b64 s[[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]], exec diff --git a/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll b/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll index 8b8e5197a9c61..58f7dd0784db0 100644 --- a/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll +++ b/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll @@ -202,8 +202,8 @@ define amdgpu_kernel void @v3i16_registers(i1 %cond) #0 { ; GCN-NEXT: s_swappc_b64 s[30:31], s[18:19] ; GCN-NEXT: s_branch .LBB4_3 ; GCN-NEXT: .LBB4_2: -; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: .LBB4_3: ; %if.end ; GCN-NEXT: global_store_short v[0:1], v1, off ; GCN-NEXT: global_store_dword v[0:1], v0, off @@ -253,8 +253,8 @@ define amdgpu_kernel void @v3f16_registers(i1 %cond) #0 { ; GCN-NEXT: s_swappc_b64 s[30:31], s[18:19] ; GCN-NEXT: s_branch .LBB5_3 ; GCN-NEXT: .LBB5_2: -; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: .LBB5_3: ; %if.end ; GCN-NEXT: global_store_short v[0:1], v1, off ; GCN-NEXT: global_store_dword v[0:1], v0, off diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll index ddb635cabbab1..29e4bd55c4b90 100644 --- a/llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll @@ -11,7 +11,7 @@ define void @main(float %arg) { ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1 - ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 $exec_lo, [[S_MOV_B32_1]], implicit-def dead $scc ; CHECK-NEXT: $vcc_lo = COPY [[S_AND_B32_]] ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc diff --git a/llvm/test/CodeGen/AMDGPU/div_i128.ll b/llvm/test/CodeGen/AMDGPU/div_i128.ll index 3d9043d30c1ce..c383b90e1cdb1 100644 --- a/llvm/test/CodeGen/AMDGPU/div_i128.ll +++ b/llvm/test/CodeGen/AMDGPU/div_i128.ll @@ -143,12 +143,12 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-NEXT: v_add_co_u32_e32 v26, vcc, -1, v21 ; GFX9-NEXT: v_addc_co_u32_e32 v27, vcc, -1, v20, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v28, vcc, -1, v0, vcc -; GFX9-NEXT: v_mov_b32_e32 v14, 0 ; GFX9-NEXT: v_mov_b32_e32 v12, 0 +; GFX9-NEXT: v_mov_b32_e32 v14, 0 ; GFX9-NEXT: v_addc_co_u32_e32 v29, vcc, -1, v1, vcc -; GFX9-NEXT: s_mov_b64 s[4:5], 0 -; GFX9-NEXT: v_mov_b32_e32 v15, 0 ; GFX9-NEXT: v_mov_b32_e32 v13, 0 +; GFX9-NEXT: v_mov_b32_e32 v15, 0 +; GFX9-NEXT: s_mov_b64 s[4:5], 0 ; GFX9-NEXT: v_mov_b32_e32 v7, 0 ; GFX9-NEXT: .LBB0_3: ; %udiv-do-while ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -910,95 +910,93 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_waitcnt vmcnt(9) ; GFX9-O0-NEXT: v_mov_b32_e32 v4, v10 ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: v_lshrrev_b64 v[6:7], v4, v[20:21] +; GFX9-O0-NEXT: v_lshrrev_b64 v[6:7], v4, v[18:19] ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v7 -; GFX9-O0-NEXT: s_mov_b32 s6, 64 -; GFX9-O0-NEXT: v_sub_u32_e64 v12, s6, v4 -; GFX9-O0-NEXT: v_lshlrev_b64 v[22:23], v12, v[18:19] -; GFX9-O0-NEXT: v_mov_b32_e32 v12, v23 -; GFX9-O0-NEXT: v_or_b32_e64 v5, v5, v12 +; GFX9-O0-NEXT: s_mov_b32 s4, 64 +; GFX9-O0-NEXT: v_sub_u32_e64 v20, s4, v4 +; GFX9-O0-NEXT: v_lshlrev_b64 v[20:21], v20, v[14:15] +; GFX9-O0-NEXT: v_mov_b32_e32 v22, v21 +; GFX9-O0-NEXT: v_or_b32_e64 v5, v5, v22 ; GFX9-O0-NEXT: ; kill: def $vgpr6 killed $vgpr6 killed $vgpr6_vgpr7 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v7, v22 +; GFX9-O0-NEXT: v_mov_b32_e32 v7, v20 ; GFX9-O0-NEXT: v_or_b32_e64 v6, v6, v7 ; GFX9-O0-NEXT: ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v5 -; GFX9-O0-NEXT: v_mov_b32_e32 v12, v7 -; GFX9-O0-NEXT: v_cmp_lt_u32_e64 s[4:5], v4, s6 -; GFX9-O0-NEXT: v_sub_u32_e64 v5, v4, s6 -; GFX9-O0-NEXT: v_lshrrev_b64 v[22:23], v5, v[18:19] -; GFX9-O0-NEXT: v_mov_b32_e32 v5, v23 -; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v12, s[4:5] -; GFX9-O0-NEXT: s_mov_b32 s6, 0 -; GFX9-O0-NEXT: v_cmp_eq_u32_e64 s[6:7], v4, s6 -; GFX9-O0-NEXT: v_mov_b32_e32 v12, v21 -; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v12, s[6:7] +; GFX9-O0-NEXT: v_mov_b32_e32 v22, v7 +; GFX9-O0-NEXT: v_cmp_lt_u32_e64 s[6:7], v4, s4 +; GFX9-O0-NEXT: v_sub_u32_e64 v5, v4, s4 +; GFX9-O0-NEXT: v_lshrrev_b64 v[20:21], v5, v[14:15] +; GFX9-O0-NEXT: v_mov_b32_e32 v5, v21 +; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v22, s[6:7] +; GFX9-O0-NEXT: s_mov_b32 s4, 0 +; GFX9-O0-NEXT: v_cmp_eq_u32_e64 s[4:5], v4, s4 +; GFX9-O0-NEXT: v_mov_b32_e32 v22, v19 +; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v22, s[4:5] ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v6 -; GFX9-O0-NEXT: v_mov_b32_e32 v6, v22 -; GFX9-O0-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[4:5] -; GFX9-O0-NEXT: v_mov_b32_e32 v7, v20 +; GFX9-O0-NEXT: v_mov_b32_e32 v6, v20 ; GFX9-O0-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[6:7] -; GFX9-O0-NEXT: ; implicit-def: $sgpr6 -; GFX9-O0-NEXT: ; implicit-def: $sgpr6 +; GFX9-O0-NEXT: v_mov_b32_e32 v7, v18 +; GFX9-O0-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[4:5] +; GFX9-O0-NEXT: ; implicit-def: $sgpr4 +; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v5 -; GFX9-O0-NEXT: v_lshrrev_b64 v[4:5], v4, v[18:19] +; GFX9-O0-NEXT: v_lshrrev_b64 v[4:5], v4, v[14:15] ; GFX9-O0-NEXT: v_mov_b32_e32 v15, v5 -; GFX9-O0-NEXT: s_mov_b64 s[6:7], 0 -; GFX9-O0-NEXT: s_mov_b32 s8, s7 -; GFX9-O0-NEXT: v_mov_b32_e32 v12, s8 -; GFX9-O0-NEXT: v_cndmask_b32_e64 v12, v12, v15, s[4:5] +; GFX9-O0-NEXT: s_mov_b64 s[4:5], 0 +; GFX9-O0-NEXT: s_mov_b32 s8, s5 +; GFX9-O0-NEXT: v_mov_b32_e32 v14, s8 +; GFX9-O0-NEXT: v_cndmask_b32_e64 v14, v14, v15, s[6:7] ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v4 -; GFX9-O0-NEXT: s_mov_b32 s8, s6 +; GFX9-O0-NEXT: s_mov_b32 s8, s4 ; GFX9-O0-NEXT: v_mov_b32_e32 v4, s8 -; GFX9-O0-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[4:5] -; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; implicit-def: $sgpr4 +; GFX9-O0-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[6:7] +; GFX9-O0-NEXT: ; implicit-def: $sgpr6 +; GFX9-O0-NEXT: ; implicit-def: $sgpr6 ; GFX9-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v5, v12 +; GFX9-O0-NEXT: v_mov_b32_e32 v5, v14 +; GFX9-O0-NEXT: v_mov_b32_e32 v15, v12 ; GFX9-O0-NEXT: v_mov_b32_e32 v12, v13 -; GFX9-O0-NEXT: v_mov_b32_e32 v15, v14 ; GFX9-O0-NEXT: s_mov_b64 s[8:9], -1 -; GFX9-O0-NEXT: s_mov_b32 s5, s8 -; GFX9-O0-NEXT: s_mov_b32 s4, s9 +; GFX9-O0-NEXT: s_mov_b32 s7, s8 +; GFX9-O0-NEXT: s_mov_b32 s6, s9 ; GFX9-O0-NEXT: v_mov_b32_e32 v14, v16 ; GFX9-O0-NEXT: v_mov_b32_e32 v13, v17 -; GFX9-O0-NEXT: v_mov_b32_e32 v16, s5 -; GFX9-O0-NEXT: v_add_co_u32_e32 v12, vcc, v12, v16 -; GFX9-O0-NEXT: v_mov_b32_e32 v16, s4 -; GFX9-O0-NEXT: v_addc_co_u32_e32 v16, vcc, v15, v16, vcc +; GFX9-O0-NEXT: v_mov_b32_e32 v16, s7 +; GFX9-O0-NEXT: v_add_co_u32_e32 v16, vcc, v15, v16 +; GFX9-O0-NEXT: v_mov_b32_e32 v15, s6 +; GFX9-O0-NEXT: v_addc_co_u32_e32 v12, vcc, v12, v15, vcc +; GFX9-O0-NEXT: v_mov_b32_e32 v15, s7 +; GFX9-O0-NEXT: v_addc_co_u32_e32 v18, vcc, v14, v15, vcc +; GFX9-O0-NEXT: v_mov_b32_e32 v14, s6 +; GFX9-O0-NEXT: v_addc_co_u32_e32 v13, vcc, v13, v14, vcc +; GFX9-O0-NEXT: ; implicit-def: $sgpr6 +; GFX9-O0-NEXT: ; implicit-def: $sgpr6 +; GFX9-O0-NEXT: ; kill: def $vgpr18 killed $vgpr18 def $vgpr18_vgpr19 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v19, v13 +; GFX9-O0-NEXT: ; implicit-def: $sgpr6 +; GFX9-O0-NEXT: ; implicit-def: $sgpr6 +; GFX9-O0-NEXT: ; kill: def $vgpr16 killed $vgpr16 def $vgpr16_vgpr17 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v17, v12 +; GFX9-O0-NEXT: v_mov_b32_e32 v13, s5 +; GFX9-O0-NEXT: v_mov_b32_e32 v12, s4 ; GFX9-O0-NEXT: v_mov_b32_e32 v15, s5 -; GFX9-O0-NEXT: v_addc_co_u32_e32 v14, vcc, v14, v15, vcc -; GFX9-O0-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-O0-NEXT: v_addc_co_u32_e32 v13, vcc, v13, v15, vcc -; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr14 killed $vgpr14 def $vgpr14_vgpr15 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v15, v13 -; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v13, v16 -; GFX9-O0-NEXT: s_mov_b64 s[8:9], s[6:7] -; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v14, s4 +; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_nop 0 -; GFX9-O0-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_nop 0 -; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; GFX9-O0-NEXT: s_mov_b64 s[4:5], s[6:7] -; GFX9-O0-NEXT: v_mov_b32_e32 v15, s9 -; GFX9-O0-NEXT: v_mov_b32_e32 v14, s8 -; GFX9-O0-NEXT: v_mov_b32_e32 v13, s7 -; GFX9-O0-NEXT: v_mov_b32_e32 v12, s6 +; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill ; GFX9-O0-NEXT: v_writelane_b32 v30, s4, 10 ; GFX9-O0-NEXT: v_writelane_b32 v30, s5, 11 ; GFX9-O0-NEXT: s_or_saveexec_b64 s[22:23], -1 @@ -1138,11 +1136,10 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v1, v2 ; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[4:5], v[0:1], s[6:7] -; GFX9-O0-NEXT: s_mov_b64 s[8:9], s[6:7] -; GFX9-O0-NEXT: v_mov_b32_e32 v2, s8 -; GFX9-O0-NEXT: v_mov_b32_e32 v3, s9 ; GFX9-O0-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-O0-NEXT: v_mov_b32_e32 v1, s7 +; GFX9-O0-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-O0-NEXT: v_mov_b32_e32 v3, s7 ; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_nop 0 ; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill @@ -2428,14 +2425,14 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-NEXT: v_addc_co_u32_e32 v23, vcc, -1, v5, vcc ; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v18 ; GFX9-NEXT: v_addc_co_u32_e32 v24, vcc, -1, v6, vcc -; GFX9-NEXT: v_mov_b32_e32 v16, 0 ; GFX9-NEXT: v_mov_b32_e32 v14, 0 +; GFX9-NEXT: v_mov_b32_e32 v16, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v1, v13, v1, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e64 v0, v12, v0, s[4:5] ; GFX9-NEXT: v_addc_co_u32_e32 v25, vcc, -1, v7, vcc -; GFX9-NEXT: s_mov_b64 s[4:5], 0 -; GFX9-NEXT: v_mov_b32_e32 v17, 0 ; GFX9-NEXT: v_mov_b32_e32 v15, 0 +; GFX9-NEXT: v_mov_b32_e32 v17, 0 +; GFX9-NEXT: s_mov_b64 s[4:5], 0 ; GFX9-NEXT: v_mov_b32_e32 v13, 0 ; GFX9-NEXT: .LBB1_3: ; %udiv-do-while ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -3102,95 +3099,93 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_waitcnt vmcnt(9) ; GFX9-O0-NEXT: v_mov_b32_e32 v4, v10 ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: v_lshrrev_b64 v[6:7], v4, v[20:21] +; GFX9-O0-NEXT: v_lshrrev_b64 v[6:7], v4, v[18:19] ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v7 -; GFX9-O0-NEXT: s_mov_b32 s6, 64 -; GFX9-O0-NEXT: v_sub_u32_e64 v12, s6, v4 -; GFX9-O0-NEXT: v_lshlrev_b64 v[22:23], v12, v[18:19] -; GFX9-O0-NEXT: v_mov_b32_e32 v12, v23 -; GFX9-O0-NEXT: v_or_b32_e64 v5, v5, v12 +; GFX9-O0-NEXT: s_mov_b32 s4, 64 +; GFX9-O0-NEXT: v_sub_u32_e64 v20, s4, v4 +; GFX9-O0-NEXT: v_lshlrev_b64 v[20:21], v20, v[14:15] +; GFX9-O0-NEXT: v_mov_b32_e32 v22, v21 +; GFX9-O0-NEXT: v_or_b32_e64 v5, v5, v22 ; GFX9-O0-NEXT: ; kill: def $vgpr6 killed $vgpr6 killed $vgpr6_vgpr7 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v7, v22 +; GFX9-O0-NEXT: v_mov_b32_e32 v7, v20 ; GFX9-O0-NEXT: v_or_b32_e64 v6, v6, v7 ; GFX9-O0-NEXT: ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v5 -; GFX9-O0-NEXT: v_mov_b32_e32 v12, v7 -; GFX9-O0-NEXT: v_cmp_lt_u32_e64 s[4:5], v4, s6 -; GFX9-O0-NEXT: v_sub_u32_e64 v5, v4, s6 -; GFX9-O0-NEXT: v_lshrrev_b64 v[22:23], v5, v[18:19] -; GFX9-O0-NEXT: v_mov_b32_e32 v5, v23 -; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v12, s[4:5] -; GFX9-O0-NEXT: s_mov_b32 s6, 0 -; GFX9-O0-NEXT: v_cmp_eq_u32_e64 s[6:7], v4, s6 -; GFX9-O0-NEXT: v_mov_b32_e32 v12, v21 -; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v12, s[6:7] +; GFX9-O0-NEXT: v_mov_b32_e32 v22, v7 +; GFX9-O0-NEXT: v_cmp_lt_u32_e64 s[6:7], v4, s4 +; GFX9-O0-NEXT: v_sub_u32_e64 v5, v4, s4 +; GFX9-O0-NEXT: v_lshrrev_b64 v[20:21], v5, v[14:15] +; GFX9-O0-NEXT: v_mov_b32_e32 v5, v21 +; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v22, s[6:7] +; GFX9-O0-NEXT: s_mov_b32 s4, 0 +; GFX9-O0-NEXT: v_cmp_eq_u32_e64 s[4:5], v4, s4 +; GFX9-O0-NEXT: v_mov_b32_e32 v22, v19 +; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v22, s[4:5] ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v6 -; GFX9-O0-NEXT: v_mov_b32_e32 v6, v22 -; GFX9-O0-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[4:5] -; GFX9-O0-NEXT: v_mov_b32_e32 v7, v20 +; GFX9-O0-NEXT: v_mov_b32_e32 v6, v20 ; GFX9-O0-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[6:7] -; GFX9-O0-NEXT: ; implicit-def: $sgpr6 -; GFX9-O0-NEXT: ; implicit-def: $sgpr6 +; GFX9-O0-NEXT: v_mov_b32_e32 v7, v18 +; GFX9-O0-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[4:5] +; GFX9-O0-NEXT: ; implicit-def: $sgpr4 +; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v5 -; GFX9-O0-NEXT: v_lshrrev_b64 v[4:5], v4, v[18:19] +; GFX9-O0-NEXT: v_lshrrev_b64 v[4:5], v4, v[14:15] ; GFX9-O0-NEXT: v_mov_b32_e32 v15, v5 -; GFX9-O0-NEXT: s_mov_b64 s[6:7], 0 -; GFX9-O0-NEXT: s_mov_b32 s8, s7 -; GFX9-O0-NEXT: v_mov_b32_e32 v12, s8 -; GFX9-O0-NEXT: v_cndmask_b32_e64 v12, v12, v15, s[4:5] +; GFX9-O0-NEXT: s_mov_b64 s[4:5], 0 +; GFX9-O0-NEXT: s_mov_b32 s8, s5 +; GFX9-O0-NEXT: v_mov_b32_e32 v14, s8 +; GFX9-O0-NEXT: v_cndmask_b32_e64 v14, v14, v15, s[6:7] ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v4 -; GFX9-O0-NEXT: s_mov_b32 s8, s6 +; GFX9-O0-NEXT: s_mov_b32 s8, s4 ; GFX9-O0-NEXT: v_mov_b32_e32 v4, s8 -; GFX9-O0-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[4:5] -; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; implicit-def: $sgpr4 +; GFX9-O0-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[6:7] +; GFX9-O0-NEXT: ; implicit-def: $sgpr6 +; GFX9-O0-NEXT: ; implicit-def: $sgpr6 ; GFX9-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v5, v12 +; GFX9-O0-NEXT: v_mov_b32_e32 v5, v14 +; GFX9-O0-NEXT: v_mov_b32_e32 v15, v12 ; GFX9-O0-NEXT: v_mov_b32_e32 v12, v13 -; GFX9-O0-NEXT: v_mov_b32_e32 v15, v14 ; GFX9-O0-NEXT: s_mov_b64 s[8:9], -1 -; GFX9-O0-NEXT: s_mov_b32 s5, s8 -; GFX9-O0-NEXT: s_mov_b32 s4, s9 +; GFX9-O0-NEXT: s_mov_b32 s7, s8 +; GFX9-O0-NEXT: s_mov_b32 s6, s9 ; GFX9-O0-NEXT: v_mov_b32_e32 v14, v16 ; GFX9-O0-NEXT: v_mov_b32_e32 v13, v17 -; GFX9-O0-NEXT: v_mov_b32_e32 v16, s5 -; GFX9-O0-NEXT: v_add_co_u32_e32 v12, vcc, v12, v16 -; GFX9-O0-NEXT: v_mov_b32_e32 v16, s4 -; GFX9-O0-NEXT: v_addc_co_u32_e32 v16, vcc, v15, v16, vcc +; GFX9-O0-NEXT: v_mov_b32_e32 v16, s7 +; GFX9-O0-NEXT: v_add_co_u32_e32 v16, vcc, v15, v16 +; GFX9-O0-NEXT: v_mov_b32_e32 v15, s6 +; GFX9-O0-NEXT: v_addc_co_u32_e32 v12, vcc, v12, v15, vcc +; GFX9-O0-NEXT: v_mov_b32_e32 v15, s7 +; GFX9-O0-NEXT: v_addc_co_u32_e32 v18, vcc, v14, v15, vcc +; GFX9-O0-NEXT: v_mov_b32_e32 v14, s6 +; GFX9-O0-NEXT: v_addc_co_u32_e32 v13, vcc, v13, v14, vcc +; GFX9-O0-NEXT: ; implicit-def: $sgpr6 +; GFX9-O0-NEXT: ; implicit-def: $sgpr6 +; GFX9-O0-NEXT: ; kill: def $vgpr18 killed $vgpr18 def $vgpr18_vgpr19 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v19, v13 +; GFX9-O0-NEXT: ; implicit-def: $sgpr6 +; GFX9-O0-NEXT: ; implicit-def: $sgpr6 +; GFX9-O0-NEXT: ; kill: def $vgpr16 killed $vgpr16 def $vgpr16_vgpr17 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v17, v12 +; GFX9-O0-NEXT: v_mov_b32_e32 v13, s5 +; GFX9-O0-NEXT: v_mov_b32_e32 v12, s4 ; GFX9-O0-NEXT: v_mov_b32_e32 v15, s5 -; GFX9-O0-NEXT: v_addc_co_u32_e32 v14, vcc, v14, v15, vcc -; GFX9-O0-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-O0-NEXT: v_addc_co_u32_e32 v13, vcc, v13, v15, vcc -; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr14 killed $vgpr14 def $vgpr14_vgpr15 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v15, v13 -; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v13, v16 -; GFX9-O0-NEXT: s_mov_b64 s[8:9], s[6:7] -; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v14, s4 +; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_nop 0 -; GFX9-O0-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_nop 0 -; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill -; GFX9-O0-NEXT: s_mov_b64 s[4:5], s[6:7] -; GFX9-O0-NEXT: v_mov_b32_e32 v15, s9 -; GFX9-O0-NEXT: v_mov_b32_e32 v14, s8 -; GFX9-O0-NEXT: v_mov_b32_e32 v13, s7 -; GFX9-O0-NEXT: v_mov_b32_e32 v12, s6 +; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill ; GFX9-O0-NEXT: v_writelane_b32 v30, s4, 8 ; GFX9-O0-NEXT: v_writelane_b32 v30, s5, 9 ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 @@ -3330,11 +3325,10 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v1, v2 ; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[4:5], v[0:1], s[6:7] -; GFX9-O0-NEXT: s_mov_b64 s[8:9], s[6:7] -; GFX9-O0-NEXT: v_mov_b32_e32 v2, s8 -; GFX9-O0-NEXT: v_mov_b32_e32 v3, s9 ; GFX9-O0-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-O0-NEXT: v_mov_b32_e32 v1, s7 +; GFX9-O0-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-O0-NEXT: v_mov_b32_e32 v3, s7 ; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_nop 0 ; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill diff --git a/llvm/test/CodeGen/AMDGPU/div_v2i128.ll b/llvm/test/CodeGen/AMDGPU/div_v2i128.ll index e01e540a8c8aa..77b78f1f8a333 100644 --- a/llvm/test/CodeGen/AMDGPU/div_v2i128.ll +++ b/llvm/test/CodeGen/AMDGPU/div_v2i128.ll @@ -141,11 +141,11 @@ define <2 x i128> @v_sdiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_addc_u32_e32 v35, vcc, -1, v28, vcc ; SDAG-NEXT: v_addc_u32_e32 v36, vcc, -1, v0, vcc ; SDAG-NEXT: v_addc_u32_e32 v37, vcc, -1, v1, vcc -; SDAG-NEXT: s_mov_b64 s[4:5], 0 -; SDAG-NEXT: v_mov_b32_e32 v16, 0 -; SDAG-NEXT: v_mov_b32_e32 v17, 0 ; SDAG-NEXT: v_mov_b32_e32 v10, 0 ; SDAG-NEXT: v_mov_b32_e32 v11, 0 +; SDAG-NEXT: v_mov_b32_e32 v16, 0 +; SDAG-NEXT: v_mov_b32_e32 v17, 0 +; SDAG-NEXT: s_mov_b64 s[4:5], 0 ; SDAG-NEXT: v_mov_b32_e32 v9, 0 ; SDAG-NEXT: .LBB0_3: ; %udiv-do-while3 ; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -323,11 +323,11 @@ define <2 x i128> @v_sdiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_subrev_i32_e32 v36, vcc, 64, v30 ; SDAG-NEXT: v_lshr_b64 v[37:38], v[6:7], v30 ; SDAG-NEXT: v_add_i32_e32 v34, vcc, -1, v29 -; SDAG-NEXT: s_mov_b64 s[10:11], 0 -; SDAG-NEXT: v_mov_b32_e32 v14, 0 -; SDAG-NEXT: v_mov_b32_e32 v15, 0 ; SDAG-NEXT: v_mov_b32_e32 v12, 0 ; SDAG-NEXT: v_mov_b32_e32 v13, 0 +; SDAG-NEXT: v_mov_b32_e32 v14, 0 +; SDAG-NEXT: v_mov_b32_e32 v15, 0 +; SDAG-NEXT: s_mov_b64 s[10:11], 0 ; SDAG-NEXT: v_lshl_b64 v[48:49], v[6:7], v35 ; SDAG-NEXT: v_lshr_b64 v[6:7], v[6:7], v36 ; SDAG-NEXT: v_addc_u32_e32 v35, vcc, -1, v28, vcc @@ -947,11 +947,11 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_addc_u32_e32 v31, vcc, -1, v9, vcc ; SDAG-NEXT: v_addc_u32_e32 v32, vcc, -1, v10, vcc ; SDAG-NEXT: v_addc_u32_e32 v33, vcc, -1, v11, vcc -; SDAG-NEXT: s_mov_b64 s[4:5], 0 -; SDAG-NEXT: v_mov_b32_e32 v24, 0 -; SDAG-NEXT: v_mov_b32_e32 v25, 0 ; SDAG-NEXT: v_mov_b32_e32 v22, 0 ; SDAG-NEXT: v_mov_b32_e32 v23, 0 +; SDAG-NEXT: v_mov_b32_e32 v24, 0 +; SDAG-NEXT: v_mov_b32_e32 v25, 0 +; SDAG-NEXT: s_mov_b64 s[4:5], 0 ; SDAG-NEXT: v_mov_b32_e32 v21, 0 ; SDAG-NEXT: .LBB1_3: ; %udiv-do-while3 ; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -1107,11 +1107,11 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_subrev_i32_e32 v28, vcc, 64, v22 ; SDAG-NEXT: v_lshr_b64 v[29:30], v[6:7], v22 ; SDAG-NEXT: v_add_i32_e32 v26, vcc, -1, v12 -; SDAG-NEXT: s_mov_b64 s[10:11], 0 -; SDAG-NEXT: v_mov_b32_e32 v10, 0 -; SDAG-NEXT: v_mov_b32_e32 v11, 0 ; SDAG-NEXT: v_mov_b32_e32 v20, 0 ; SDAG-NEXT: v_mov_b32_e32 v21, 0 +; SDAG-NEXT: v_mov_b32_e32 v10, 0 +; SDAG-NEXT: v_mov_b32_e32 v11, 0 +; SDAG-NEXT: s_mov_b64 s[10:11], 0 ; SDAG-NEXT: v_lshl_b64 v[31:32], v[6:7], v27 ; SDAG-NEXT: v_lshr_b64 v[6:7], v[6:7], v28 ; SDAG-NEXT: v_addc_u32_e32 v27, vcc, -1, v13, vcc @@ -1679,11 +1679,11 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_subrev_i32_e32 v37, vcc, 64, v32 ; SDAG-NEXT: v_lshr_b64 v[24:25], v[0:1], v32 ; SDAG-NEXT: v_add_i32_e32 v36, vcc, -1, v31 -; SDAG-NEXT: s_mov_b64 s[10:11], 0 -; SDAG-NEXT: v_mov_b32_e32 v22, 0 -; SDAG-NEXT: v_mov_b32_e32 v23, 0 ; SDAG-NEXT: v_mov_b32_e32 v18, 0 ; SDAG-NEXT: v_mov_b32_e32 v19, 0 +; SDAG-NEXT: v_mov_b32_e32 v22, 0 +; SDAG-NEXT: v_mov_b32_e32 v23, 0 +; SDAG-NEXT: s_mov_b64 s[10:11], 0 ; SDAG-NEXT: v_lshl_b64 v[26:27], v[0:1], v26 ; SDAG-NEXT: v_lshr_b64 v[48:49], v[0:1], v37 ; SDAG-NEXT: v_addc_u32_e32 v37, vcc, -1, v30, vcc @@ -1874,11 +1874,11 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_subrev_i32_e32 v51, vcc, 64, v38 ; SDAG-NEXT: v_lshr_b64 v[22:23], v[4:5], v38 ; SDAG-NEXT: v_add_i32_e32 v50, vcc, -1, v37 -; SDAG-NEXT: s_mov_b64 s[10:11], 0 -; SDAG-NEXT: v_mov_b32_e32 v20, 0 -; SDAG-NEXT: v_mov_b32_e32 v21, 0 ; SDAG-NEXT: v_mov_b32_e32 v18, 0 ; SDAG-NEXT: v_mov_b32_e32 v19, 0 +; SDAG-NEXT: v_mov_b32_e32 v20, 0 +; SDAG-NEXT: v_mov_b32_e32 v21, 0 +; SDAG-NEXT: s_mov_b64 s[10:11], 0 ; SDAG-NEXT: v_lshl_b64 v[24:25], v[4:5], v24 ; SDAG-NEXT: v_lshr_b64 v[53:54], v[4:5], v51 ; SDAG-NEXT: v_addc_u32_e32 v51, vcc, -1, v36, vcc @@ -2562,11 +2562,11 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_subrev_i32_e32 v35, vcc, 64, v30 ; SDAG-NEXT: v_lshr_b64 v[26:27], v[2:3], v30 ; SDAG-NEXT: v_add_i32_e32 v34, vcc, -1, v8 -; SDAG-NEXT: s_mov_b64 s[10:11], 0 -; SDAG-NEXT: v_mov_b32_e32 v24, 0 -; SDAG-NEXT: v_mov_b32_e32 v25, 0 ; SDAG-NEXT: v_mov_b32_e32 v20, 0 ; SDAG-NEXT: v_mov_b32_e32 v21, 0 +; SDAG-NEXT: v_mov_b32_e32 v24, 0 +; SDAG-NEXT: v_mov_b32_e32 v25, 0 +; SDAG-NEXT: s_mov_b64 s[10:11], 0 ; SDAG-NEXT: v_lshl_b64 v[28:29], v[2:3], v28 ; SDAG-NEXT: v_lshr_b64 v[37:38], v[2:3], v35 ; SDAG-NEXT: v_addc_u32_e32 v35, vcc, -1, v9, vcc @@ -2737,11 +2737,11 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_subrev_i32_e32 v39, vcc, 64, v34 ; SDAG-NEXT: v_lshr_b64 v[26:27], v[6:7], v34 ; SDAG-NEXT: v_add_i32_e32 v38, vcc, -1, v12 -; SDAG-NEXT: s_mov_b64 s[10:11], 0 -; SDAG-NEXT: v_mov_b32_e32 v24, 0 -; SDAG-NEXT: v_mov_b32_e32 v25, 0 ; SDAG-NEXT: v_mov_b32_e32 v22, 0 ; SDAG-NEXT: v_mov_b32_e32 v23, 0 +; SDAG-NEXT: v_mov_b32_e32 v24, 0 +; SDAG-NEXT: v_mov_b32_e32 v25, 0 +; SDAG-NEXT: s_mov_b64 s[10:11], 0 ; SDAG-NEXT: v_lshl_b64 v[28:29], v[6:7], v28 ; SDAG-NEXT: v_lshr_b64 v[49:50], v[6:7], v39 ; SDAG-NEXT: v_addc_u32_e32 v39, vcc, -1, v13, vcc diff --git a/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll b/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll index 0a420396f52a9..db7897d70fa93 100644 --- a/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll +++ b/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll @@ -20,7 +20,7 @@ define amdgpu_ps void @main(i32 %0, float %1) { ; ISA: ; %bb.0: ; %start ; ISA-NEXT: v_readfirstlane_b32 s0, v0 ; ISA-NEXT: s_mov_b32 m0, s0 -; ISA-NEXT: s_mov_b32 s8, 0 +; ISA-NEXT: s_mov_b32 s10, 0 ; ISA-NEXT: v_interp_p1_f32_e32 v0, v1, attr0.x ; ISA-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v0 ; ISA-NEXT: s_mov_b64 s[0:1], 0 @@ -29,32 +29,33 @@ define amdgpu_ps void @main(i32 %0, float %1) { ; ISA-NEXT: s_branch .LBB0_3 ; ISA-NEXT: .LBB0_1: ; %Flow1 ; ISA-NEXT: ; in Loop: Header=BB0_3 Depth=1 -; ISA-NEXT: s_or_b64 exec, exec, s[6:7] -; ISA-NEXT: s_mov_b64 s[6:7], 0 +; ISA-NEXT: s_or_b64 exec, exec, s[4:5] +; ISA-NEXT: s_mov_b64 s[8:9], 0 +; ISA-NEXT: s_mov_b64 s[4:5], s[6:7] ; ISA-NEXT: .LBB0_2: ; %Flow ; ISA-NEXT: ; in Loop: Header=BB0_3 Depth=1 -; ISA-NEXT: s_and_b64 s[10:11], exec, s[4:5] -; ISA-NEXT: s_or_b64 s[0:1], s[10:11], s[0:1] +; ISA-NEXT: s_and_b64 s[6:7], exec, s[4:5] +; ISA-NEXT: s_or_b64 s[0:1], s[6:7], s[0:1] ; ISA-NEXT: s_andn2_b64 s[2:3], s[2:3], exec -; ISA-NEXT: s_and_b64 s[6:7], s[6:7], exec +; ISA-NEXT: s_and_b64 s[6:7], s[8:9], exec ; ISA-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7] ; ISA-NEXT: s_andn2_b64 exec, exec, s[0:1] ; ISA-NEXT: s_cbranch_execz .LBB0_6 ; ISA-NEXT: .LBB0_3: ; %loop ; ISA-NEXT: ; =>This Inner Loop Header: Depth=1 ; ISA-NEXT: s_or_b64 s[4:5], s[4:5], exec -; ISA-NEXT: s_cmp_lt_u32 s8, 32 ; ISA-NEXT: s_mov_b64 s[6:7], -1 +; ISA-NEXT: s_cmp_lt_u32 s10, 32 +; ISA-NEXT: s_mov_b64 s[8:9], -1 ; ISA-NEXT: s_cbranch_scc0 .LBB0_2 ; ISA-NEXT: ; %bb.4: ; %endif1 ; ISA-NEXT: ; in Loop: Header=BB0_3 Depth=1 -; ISA-NEXT: s_mov_b64 s[4:5], -1 -; ISA-NEXT: s_and_saveexec_b64 s[6:7], vcc +; ISA-NEXT: s_and_saveexec_b64 s[4:5], vcc ; ISA-NEXT: s_cbranch_execz .LBB0_1 ; ISA-NEXT: ; %bb.5: ; %endif2 ; ISA-NEXT: ; in Loop: Header=BB0_3 Depth=1 -; ISA-NEXT: s_add_i32 s8, s8, 1 -; ISA-NEXT: s_xor_b64 s[4:5], exec, -1 +; ISA-NEXT: s_add_i32 s10, s10, 1 +; ISA-NEXT: s_xor_b64 s[6:7], exec, -1 ; ISA-NEXT: s_branch .LBB0_1 ; ISA-NEXT: .LBB0_6: ; %Flow2 ; ISA-NEXT: s_or_b64 exec, exec, s[0:1] diff --git a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-nondeterminism.ll b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-nondeterminism.ll index 67cfe52482542..1e469b1951009 100644 --- a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-nondeterminism.ll +++ b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-nondeterminism.ll @@ -11,8 +11,8 @@ define amdgpu_gs void @f(i32 inreg %arg, i32 %arg1, i32 %arg2) { ; CHECK-NEXT: v_mov_b32_e32 v5, v0 ; CHECK-NEXT: s_branch .LBB0_3 ; CHECK-NEXT: .LBB0_2: -; CHECK-NEXT: v_mov_b32_e32 v5, 1 ; CHECK-NEXT: v_mov_b32_e32 v1, 0 +; CHECK-NEXT: v_mov_b32_e32 v5, 1 ; CHECK-NEXT: .LBB0_3: ; %bb4 ; CHECK-NEXT: v_mov_b32_e32 v6, 0 ; CHECK-NEXT: s_mov_b32 s1, s0 diff --git a/llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll b/llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll index 1564742c36d08..39e9cccec9fac 100644 --- a/llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll +++ b/llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll @@ -46,7 +46,7 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace ; GFX90A-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY1]], %subreg.sub1 ; GFX90A-NEXT: [[COPY3:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[REG_SEQUENCE]] ; GFX90A-NEXT: [[SI_PS_LIVE:%[0-9]+]]:sreg_64 = SI_PS_LIVE - ; GFX90A-NEXT: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; GFX90A-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GFX90A-NEXT: [[SI_IF:%[0-9]+]]:sreg_64 = SI_IF killed [[SI_PS_LIVE]], %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec ; GFX90A-NEXT: S_BRANCH %bb.1 ; GFX90A-NEXT: {{ $}} @@ -81,7 +81,7 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace ; GFX90A-NEXT: early-clobber %2:sgpr_32 = STRICT_WWM killed [[V_READLANE_B32_]], implicit $exec ; GFX90A-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 killed [[V_MBCNT_HI_U32_B32_e64_]], [[S_MOV_B32_]], implicit $exec ; GFX90A-NEXT: [[COPY8:%[0-9]+]]:vreg_1 = COPY [[V_CMP_EQ_U32_e64_]] - ; GFX90A-NEXT: [[DEF2:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; GFX90A-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GFX90A-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64 = SI_IF [[V_CMP_EQ_U32_e64_]], %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec ; GFX90A-NEXT: S_BRANCH %bb.2 ; GFX90A-NEXT: {{ $}} @@ -128,7 +128,7 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace ; GFX942-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY1]], %subreg.sub1 ; GFX942-NEXT: [[COPY3:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[REG_SEQUENCE]] ; GFX942-NEXT: [[SI_PS_LIVE:%[0-9]+]]:sreg_64 = SI_PS_LIVE - ; GFX942-NEXT: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; GFX942-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GFX942-NEXT: [[SI_IF:%[0-9]+]]:sreg_64 = SI_IF killed [[SI_PS_LIVE]], %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec ; GFX942-NEXT: S_BRANCH %bb.1 ; GFX942-NEXT: {{ $}} @@ -163,7 +163,7 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace ; GFX942-NEXT: early-clobber %2:sgpr_32 = STRICT_WWM killed [[V_READLANE_B32_]], implicit $exec ; GFX942-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 killed [[V_MBCNT_HI_U32_B32_e64_]], [[S_MOV_B32_]], implicit $exec ; GFX942-NEXT: [[COPY8:%[0-9]+]]:vreg_1 = COPY [[V_CMP_EQ_U32_e64_]] - ; GFX942-NEXT: [[DEF2:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; GFX942-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GFX942-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64 = SI_IF [[V_CMP_EQ_U32_e64_]], %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec ; GFX942-NEXT: S_BRANCH %bb.2 ; GFX942-NEXT: {{ $}} @@ -210,7 +210,7 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY1]], %subreg.sub1 ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[REG_SEQUENCE]] ; GFX11-NEXT: [[SI_PS_LIVE:%[0-9]+]]:sreg_32 = SI_PS_LIVE - ; GFX11-NEXT: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; GFX11-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GFX11-NEXT: [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF killed [[SI_PS_LIVE]], %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec ; GFX11-NEXT: S_BRANCH %bb.1 ; GFX11-NEXT: {{ $}} @@ -247,7 +247,7 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace ; GFX11-NEXT: early-clobber %2:sgpr_32 = STRICT_WWM killed [[V_READLANE_B32_1]], implicit $exec ; GFX11-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 killed [[V_MBCNT_LO_U32_B32_e64_]], [[S_MOV_B32_]], implicit $exec ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vreg_1 = COPY [[V_CMP_EQ_U32_e64_]] - ; GFX11-NEXT: [[DEF3:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; GFX11-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GFX11-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32 = SI_IF [[V_CMP_EQ_U32_e64_]], %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec ; GFX11-NEXT: S_BRANCH %bb.2 ; GFX11-NEXT: {{ $}} diff --git a/llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll b/llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll index f2858e4ff79c9..aabe4e930f708 100644 --- a/llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll +++ b/llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll @@ -2,9 +2,9 @@ ; RUN: llc -mtriple=amdgcn -stop-after=amdgpu-isel -enable-new-pm -o - %s | FileCheck %s ; CHECK-LABEL: vcopy_i1_undef -; CHECK: [[IMPDEF0:%[0-9]+]]:sreg_64 = IMPLICIT_DEF +; CHECK: [[IMPDEF0:%[0-9]+]]:vreg_1 = IMPLICIT_DEF ; CHECK-NOT: COPY -; CHECK: [[IMPDEF1:%[0-9]+]]:sreg_64 = IMPLICIT_DEF +; CHECK: [[IMPDEF1:%[0-9]+]]:vreg_1 = IMPLICIT_DEF ; CHECK-NOT: COPY [[IMPDEF0]] ; CHECK-NOT: COPY [[IMPDEF1]] ; CHECK: .false: diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i32.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i32.ll index d26f0df49b0a8..e00e1f13b2b77 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i32.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i32.ll @@ -533,9 +533,8 @@ define amdgpu_ps void @non_cst_non_compare_input(ptr addrspace(1) %out, i32 %tid ; GFX10-NEXT: s_and_saveexec_b32 s1, vcc_lo ; GFX10-NEXT: s_xor_b32 s1, exec_lo, s1 ; GFX10-NEXT: ; %bb.1: ; %B -; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 2, v2 +; GFX10-NEXT: v_cmp_gt_u32_e64 s0, 2, v2 ; GFX10-NEXT: ; implicit-def: $vgpr2 -; GFX10-NEXT: s_and_b32 s0, vcc_lo, exec_lo ; GFX10-NEXT: ; %bb.2: ; %Flow ; GFX10-NEXT: s_andn2_saveexec_b32 s1, s1 ; GFX10-NEXT: ; %bb.3: ; %A @@ -558,9 +557,8 @@ define amdgpu_ps void @non_cst_non_compare_input(ptr addrspace(1) %out, i32 %tid ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3 ; GFX11-NEXT: s_xor_b32 s1, exec_lo, s1 ; GFX11-NEXT: ; %bb.1: ; %B -; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 2, v2 +; GFX11-NEXT: v_cmp_gt_u32_e64 s0, 2, v2 ; GFX11-NEXT: ; implicit-def: $vgpr2 -; GFX11-NEXT: s_and_b32 s0, vcc_lo, exec_lo ; GFX11-NEXT: ; %bb.2: ; %Flow ; GFX11-NEXT: s_and_not1_saveexec_b32 s1, s1 ; GFX11-NEXT: ; %bb.3: ; %A diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.ll index c7597e98a6d58..b4adf7f641550 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.ll @@ -522,8 +522,7 @@ define amdgpu_ps void @non_cst_non_compare_input(ptr addrspace(1) %out, i32 %tid ; CHECK-NEXT: s_and_saveexec_b64 s[2:3], vcc ; CHECK-NEXT: s_xor_b64 s[2:3], exec, s[2:3] ; CHECK-NEXT: ; %bb.1: ; %B -; CHECK-NEXT: v_cmp_gt_u32_e32 vcc, 2, v2 -; CHECK-NEXT: s_and_b64 s[0:1], vcc, exec +; CHECK-NEXT: v_cmp_gt_u32_e64 s[0:1], 2, v2 ; CHECK-NEXT: ; implicit-def: $vgpr2 ; CHECK-NEXT: ; %bb.2: ; %Flow ; CHECK-NEXT: s_andn2_saveexec_b64 s[2:3], s[2:3] diff --git a/llvm/test/CodeGen/AMDGPU/loop_break.ll b/llvm/test/CodeGen/AMDGPU/loop_break.ll index 30c8739032c90..6e53d40631086 100644 --- a/llvm/test/CodeGen/AMDGPU/loop_break.ll +++ b/llvm/test/CodeGen/AMDGPU/loop_break.ll @@ -120,26 +120,22 @@ define amdgpu_kernel void @undef_phi_cond_break_loop(i32 %arg) #0 { ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s3, v0 ; GCN-NEXT: s_mov_b32 s3, 0xf000 -; GCN-NEXT: ; implicit-def: $sgpr4_sgpr5 ; GCN-NEXT: ; implicit-def: $sgpr6 ; GCN-NEXT: .LBB1_1: ; %bb1 ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-NEXT: s_andn2_b64 s[4:5], s[4:5], exec ; GCN-NEXT: s_cmp_gt_i32 s6, -1 +; GCN-NEXT: ; implicit-def: $sgpr4_sgpr5 ; GCN-NEXT: s_cbranch_scc1 .LBB1_3 ; GCN-NEXT: ; %bb.2: ; %bb4 ; GCN-NEXT: ; in Loop: Header=BB1_1 Depth=1 ; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1 -; GCN-NEXT: s_andn2_b64 s[4:5], s[4:5], exec -; GCN-NEXT: s_and_b64 s[8:9], vcc, exec -; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9] +; GCN-NEXT: v_cmp_ge_i32_e64 s[4:5], v0, v1 ; GCN-NEXT: .LBB1_3: ; %Flow ; GCN-NEXT: ; in Loop: Header=BB1_1 Depth=1 ; GCN-NEXT: s_add_i32 s6, s6, 1 -; GCN-NEXT: s_and_b64 s[8:9], exec, s[4:5] -; GCN-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1] +; GCN-NEXT: s_and_b64 s[4:5], exec, s[4:5] +; GCN-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1] ; GCN-NEXT: s_andn2_b64 exec, exec, s[0:1] ; GCN-NEXT: s_cbranch_execnz .LBB1_1 ; GCN-NEXT: ; %bb.4: ; %bb9 diff --git a/llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll b/llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll index b8e74bc7db09a..ba0f5cbf0a5f6 100644 --- a/llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll +++ b/llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll @@ -12,7 +12,6 @@ define void @machinesink_loop_variable_out_of_divergent_loop(i32 %arg, i1 %cmp49 ; CHECK-NEXT: v_and_b32_e32 v3, 1, v3 ; CHECK-NEXT: s_mov_b32 s5, 0 ; CHECK-NEXT: v_cmp_eq_u32_e64 s4, 1, v1 -; CHECK-NEXT: v_mov_b32_e32 v1, 0 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3 ; CHECK-NEXT: s_xor_b32 s6, s4, -1 ; CHECK-NEXT: s_inst_prefetch 0x1 @@ -21,11 +20,11 @@ define void @machinesink_loop_variable_out_of_divergent_loop(i32 %arg, i1 %cmp49 ; CHECK-NEXT: .LBB0_1: ; %Flow ; CHECK-NEXT: ; in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s8 -; CHECK-NEXT: v_add_nc_u32_e32 v4, -4, v4 +; CHECK-NEXT: v_add_nc_u32_e32 v3, -4, v3 ; CHECK-NEXT: .LBB0_2: ; %Flow1 ; CHECK-NEXT: ; in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s7 -; CHECK-NEXT: v_cmp_ne_u32_e64 s4, 0, v3 +; CHECK-NEXT: v_cmp_ne_u32_e64 s4, 0, v1 ; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: ; j lastloop entry ; CHECK-NEXT: ;;#ASMEND @@ -35,8 +34,8 @@ define void @machinesink_loop_variable_out_of_divergent_loop(i32 %arg, i1 %cmp49 ; CHECK-NEXT: .LBB0_3: ; %for.body33 ; CHECK-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NEXT: ; Child Loop BB0_6 Depth 2 -; CHECK-NEXT: v_mov_b32_e32 v4, 0 ; CHECK-NEXT: v_mov_b32_e32 v3, 0 +; CHECK-NEXT: v_mov_b32_e32 v1, 0 ; CHECK-NEXT: s_and_saveexec_b32 s7, s6 ; CHECK-NEXT: s_cbranch_execz .LBB0_2 ; CHECK-NEXT: ; %bb.4: ; %for.body51.preheader @@ -52,23 +51,23 @@ define void @machinesink_loop_variable_out_of_divergent_loop(i32 %arg, i1 %cmp49 ; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: ; backedge ; CHECK-NEXT: ;;#ASMEND -; CHECK-NEXT: v_add_nc_u32_e32 v4, s9, v2 -; CHECK-NEXT: v_cmp_ge_u32_e64 s4, v4, v0 +; CHECK-NEXT: v_add_nc_u32_e32 v3, s9, v2 +; CHECK-NEXT: v_cmp_ge_u32_e64 s4, v3, v0 ; CHECK-NEXT: s_or_b32 s8, s4, s8 ; CHECK-NEXT: s_andn2_b32 exec_lo, exec_lo, s8 ; CHECK-NEXT: s_cbranch_execz .LBB0_1 ; CHECK-NEXT: .LBB0_6: ; %for.body51 ; CHECK-NEXT: ; Parent Loop BB0_3 Depth=1 ; CHECK-NEXT: ; => This Inner Loop Header: Depth=2 -; CHECK-NEXT: v_mov_b32_e32 v3, 1 +; CHECK-NEXT: v_mov_b32_e32 v1, 1 ; CHECK-NEXT: s_and_saveexec_b32 s4, vcc_lo ; CHECK-NEXT: s_cbranch_execz .LBB0_5 ; CHECK-NEXT: ; %bb.7: ; %if.then112 ; CHECK-NEXT: ; in Loop: Header=BB0_6 Depth=2 ; CHECK-NEXT: s_add_i32 s10, s9, 4 -; CHECK-NEXT: v_mov_b32_e32 v3, 0 -; CHECK-NEXT: v_mov_b32_e32 v4, s10 -; CHECK-NEXT: ds_write_b32 v1, v4 +; CHECK-NEXT: v_mov_b32_e32 v1, 0 +; CHECK-NEXT: v_mov_b32_e32 v3, s10 +; CHECK-NEXT: ds_write_b32 v1, v3 ; CHECK-NEXT: s_branch .LBB0_5 ; CHECK-NEXT: .LBB0_8: ; %for.body159.preheader ; CHECK-NEXT: s_inst_prefetch 0x2 diff --git a/llvm/test/CodeGen/AMDGPU/mfma-loop.ll b/llvm/test/CodeGen/AMDGPU/mfma-loop.ll index 9d329a2d121ed..4a635d6e7f59f 100644 --- a/llvm/test/CodeGen/AMDGPU/mfma-loop.ll +++ b/llvm/test/CodeGen/AMDGPU/mfma-loop.ll @@ -78,9 +78,8 @@ exit: } ; GCN-LABEL: {{^}}test_mfma_loop_non_splat: - -; GCN-COUNT-31: v_accvgpr_write_b32 a{{[0-9]+}}, 0{{$}} ; GCN: v_accvgpr_write_b32 a{{[0-9]+}}, 1.0{{$}} +; GCN-COUNT-31: v_accvgpr_write_b32 a{{[0-9]+}}, 0{{$}} ; GCN: [[LOOP:.LBB[0-9_]+]]: ; GCN-NOT: v_accvgpr @@ -386,7 +385,8 @@ exit: ; GCN-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v0 ; GFX908-DAG: v_mov_b32_e32 [[TMP:v[0-9]+]], s{{[0-9]+}} ; GFX942_A-DAG: s_load_dword [[TMP:s[0-9]+]], -; GCN-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, [[TMP]] + +; GFX908-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, [[TMP]] ; GFX908-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, 0{{$}} ; GFX908-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, 0{{$}} ; GFX908-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, 0{{$}} @@ -420,6 +420,7 @@ exit: ; GFX90A-DAG: v_accvgpr_write_b32 [[LEAD:a[0-9]+]], 0 ; GFX90A-COUNT-28: v_accvgpr_write_b32 a{{[0-9]+}}, 0 +; GFX90A-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, [[TMP]] ; GCN: [[LOOP:.LBB[0-9_]+]]: ; GCN-NOT: v_accvgpr diff --git a/llvm/test/CodeGen/AMDGPU/mmra.ll b/llvm/test/CodeGen/AMDGPU/mmra.ll index d0696bf329af8..444997858bf7a 100644 --- a/llvm/test/CodeGen/AMDGPU/mmra.ll +++ b/llvm/test/CodeGen/AMDGPU/mmra.ll @@ -145,8 +145,7 @@ define void @cmpxchg(ptr %ptr) { ; CHECK-NEXT: [[FLAT_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_CMPSWAP_RTN [[COPY4]], killed [[COPY6]], 0, 1, implicit $exec, implicit $flat_scr, mmra !1 :: (load store acquire acquire (s32) on %ir.AlignedAddr) ; CHECK-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 [[FLAT_ATOMIC_CMPSWAP_RTN]], [[PHI2]], implicit $exec ; CHECK-NEXT: [[S_MOV_B64_1:%[0-9]+]]:sreg_64 = S_MOV_B64 -1 - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:sreg_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[DEF7]] + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; CHECK-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[PHI]], $exec, implicit-def $scc ; CHECK-NEXT: [[SI_IF:%[0-9]+]]:sreg_64 = SI_IF killed [[V_CMP_NE_U32_e64_]], %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec ; CHECK-NEXT: S_BRANCH %bb.2 @@ -164,10 +163,10 @@ define void @cmpxchg(ptr %ptr) { ; CHECK-NEXT: successors: %bb.4(0x04000000), %bb.1(0x7c000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[PHI3:%[0-9]+]]:sreg_64 = PHI [[S_OR_B64_]], %bb.1, [[S_OR_B64_1]], %bb.2 - ; CHECK-NEXT: [[PHI4:%[0-9]+]]:vgpr_32 = PHI [[COPY7]], %bb.1, [[V_AND_B32_e64_3]], %bb.2 + ; CHECK-NEXT: [[PHI4:%[0-9]+]]:vgpr_32 = PHI [[DEF7]], %bb.1, [[V_AND_B32_e64_3]], %bb.2 ; CHECK-NEXT: SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec - ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sreg_64 = COPY [[PHI3]] - ; CHECK-NEXT: [[SI_IF_BREAK:%[0-9]+]]:sreg_64 = SI_IF_BREAK [[COPY8]], [[PHI1]], implicit-def dead $scc + ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sreg_64 = COPY [[PHI3]] + ; CHECK-NEXT: [[SI_IF_BREAK:%[0-9]+]]:sreg_64 = SI_IF_BREAK [[COPY7]], [[PHI1]], implicit-def dead $scc ; CHECK-NEXT: SI_LOOP [[SI_IF_BREAK]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec ; CHECK-NEXT: S_BRANCH %bb.4 ; CHECK-NEXT: {{ $}} diff --git a/llvm/test/CodeGen/AMDGPU/multilevel-break.ll b/llvm/test/CodeGen/AMDGPU/multilevel-break.ll index 6c62f3f225cd9..056cc9b963423 100644 --- a/llvm/test/CodeGen/AMDGPU/multilevel-break.ll +++ b/llvm/test/CodeGen/AMDGPU/multilevel-break.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: opt -S -mtriple=amdgcn-- -lowerswitch -structurizecfg -si-annotate-control-flow < %s | FileCheck -check-prefix=OPT %s ; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s @@ -44,8 +44,8 @@ define amdgpu_vs void @multi_else_break(<4 x float> %vec, i32 %ub, i32 %cont) { ; ; GCN-LABEL: multi_else_break: ; GCN: ; %bb.0: ; %main_body -; GCN-NEXT: s_mov_b64 s[0:1], 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: s_mov_b64 s[0:1], 0 ; GCN-NEXT: s_branch .LBB0_2 ; GCN-NEXT: .LBB0_1: ; %loop.exit.guard ; GCN-NEXT: ; in Loop: Header=BB0_2 Depth=1 diff --git a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll index a1197aeace86f..33720ea9b28e6 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll @@ -498,11 +498,11 @@ define hidden amdgpu_kernel void @clmem_read(ptr addrspace(1) %buffer) { ; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 ; GFX900-NEXT: v_mov_b32_e32 v4, 0 ; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX900-NEXT: s_movk_i32 s4, 0x7f ; GFX900-NEXT: v_mov_b32_e32 v5, 0 +; GFX900-NEXT: s_movk_i32 s5, 0x7f ; GFX900-NEXT: s_movk_i32 s2, 0xd000 ; GFX900-NEXT: s_movk_i32 s3, 0xe000 -; GFX900-NEXT: s_movk_i32 s5, 0xf000 +; GFX900-NEXT: s_movk_i32 s4, 0xf000 ; GFX900-NEXT: .LBB1_1: ; %for.cond.preheader ; GFX900-NEXT: ; =>This Loop Header: Depth=1 ; GFX900-NEXT: ; Child Loop BB1_2 Depth 2 @@ -537,7 +537,7 @@ define hidden amdgpu_kernel void @clmem_read(ptr addrspace(1) %buffer) { ; GFX900-NEXT: v_addc_co_u32_e64 v24, s[0:1], v18, v5, s[0:1] ; GFX900-NEXT: global_load_dwordx2 v[17:18], v[13:14], off offset:-2048 ; GFX900-NEXT: global_load_dwordx2 v[21:22], v[13:14], off -; GFX900-NEXT: v_add_co_u32_e32 v4, vcc, s5, v2 +; GFX900-NEXT: v_add_co_u32_e32 v4, vcc, s4, v2 ; GFX900-NEXT: v_addc_co_u32_e32 v5, vcc, -1, v3, vcc ; GFX900-NEXT: global_load_dwordx2 v[4:5], v[4:5], off offset:-2048 ; GFX900-NEXT: s_waitcnt vmcnt(5) @@ -571,11 +571,11 @@ define hidden amdgpu_kernel void @clmem_read(ptr addrspace(1) %buffer) { ; GFX900-NEXT: s_cbranch_scc0 .LBB1_2 ; GFX900-NEXT: ; %bb.3: ; %while.cond.loopexit ; GFX900-NEXT: ; in Loop: Header=BB1_1 Depth=1 -; GFX900-NEXT: s_add_i32 s0, s4, -1 -; GFX900-NEXT: s_cmp_eq_u32 s4, 0 +; GFX900-NEXT: s_add_i32 s0, s5, -1 +; GFX900-NEXT: s_cmp_eq_u32 s5, 0 ; GFX900-NEXT: s_cbranch_scc1 .LBB1_5 ; GFX900-NEXT: ; %bb.4: ; in Loop: Header=BB1_1 Depth=1 -; GFX900-NEXT: s_mov_b32 s4, s0 +; GFX900-NEXT: s_mov_b32 s5, s0 ; GFX900-NEXT: s_branch .LBB1_1 ; GFX900-NEXT: .LBB1_5: ; %while.end ; GFX900-NEXT: v_mov_b32_e32 v1, s35 @@ -726,11 +726,11 @@ define hidden amdgpu_kernel void @clmem_read(ptr addrspace(1) %buffer) { ; GFX90A-NEXT: s_movk_i32 s0, 0x5000 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, s0, v1 ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc -; GFX90A-NEXT: s_movk_i32 s2, 0x7f ; GFX90A-NEXT: v_pk_mov_b32 v[4:5], 0, 0 +; GFX90A-NEXT: s_movk_i32 s3, 0x7f ; GFX90A-NEXT: s_movk_i32 s0, 0xd000 ; GFX90A-NEXT: s_movk_i32 s1, 0xe000 -; GFX90A-NEXT: s_movk_i32 s3, 0xf000 +; GFX90A-NEXT: s_movk_i32 s2, 0xf000 ; GFX90A-NEXT: .LBB1_1: ; %for.cond.preheader ; GFX90A-NEXT: ; =>This Loop Header: Depth=1 ; GFX90A-NEXT: ; Child Loop BB1_2 Depth 2 @@ -756,7 +756,7 @@ define hidden amdgpu_kernel void @clmem_read(ptr addrspace(1) %buffer) { ; GFX90A-NEXT: global_load_dwordx2 v[24:25], v[20:21], off offset:-4096 ; GFX90A-NEXT: global_load_dwordx2 v[26:27], v[20:21], off offset:-2048 ; GFX90A-NEXT: global_load_dwordx2 v[28:29], v[20:21], off -; GFX90A-NEXT: v_add_co_u32_e32 v22, vcc, s3, v6 +; GFX90A-NEXT: v_add_co_u32_e32 v22, vcc, s2, v6 ; GFX90A-NEXT: v_addc_co_u32_e32 v23, vcc, -1, v7, vcc ; GFX90A-NEXT: global_load_dwordx2 v[20:21], v[22:23], off offset:-2048 ; GFX90A-NEXT: global_load_dwordx2 v[30:31], v[6:7], off @@ -797,11 +797,11 @@ define hidden amdgpu_kernel void @clmem_read(ptr addrspace(1) %buffer) { ; GFX90A-NEXT: s_cbranch_scc0 .LBB1_2 ; GFX90A-NEXT: ; %bb.3: ; %while.cond.loopexit ; GFX90A-NEXT: ; in Loop: Header=BB1_1 Depth=1 -; GFX90A-NEXT: s_add_i32 s4, s2, -1 -; GFX90A-NEXT: s_cmp_eq_u32 s2, 0 +; GFX90A-NEXT: s_add_i32 s4, s3, -1 +; GFX90A-NEXT: s_cmp_eq_u32 s3, 0 ; GFX90A-NEXT: s_cbranch_scc1 .LBB1_5 ; GFX90A-NEXT: ; %bb.4: ; in Loop: Header=BB1_1 Depth=1 -; GFX90A-NEXT: s_mov_b32 s2, s4 +; GFX90A-NEXT: s_mov_b32 s3, s4 ; GFX90A-NEXT: s_branch .LBB1_1 ; GFX90A-NEXT: .LBB1_5: ; %while.end ; GFX90A-NEXT: v_mov_b32_e32 v1, s35 diff --git a/llvm/test/CodeGen/AMDGPU/rem_i128.ll b/llvm/test/CodeGen/AMDGPU/rem_i128.ll index d25226d15a029..6512bee36e88b 100644 --- a/llvm/test/CodeGen/AMDGPU/rem_i128.ll +++ b/llvm/test/CodeGen/AMDGPU/rem_i128.ll @@ -142,12 +142,12 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-NEXT: v_add_co_u32_e32 v28, vcc, -1, v23 ; GFX9-NEXT: v_addc_co_u32_e32 v29, vcc, -1, v22, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v30, vcc, -1, v4, vcc -; GFX9-NEXT: v_mov_b32_e32 v18, 0 ; GFX9-NEXT: v_mov_b32_e32 v12, 0 +; GFX9-NEXT: v_mov_b32_e32 v18, 0 ; GFX9-NEXT: v_addc_co_u32_e32 v31, vcc, -1, v5, vcc -; GFX9-NEXT: s_mov_b64 s[4:5], 0 -; GFX9-NEXT: v_mov_b32_e32 v19, 0 ; GFX9-NEXT: v_mov_b32_e32 v13, 0 +; GFX9-NEXT: v_mov_b32_e32 v19, 0 +; GFX9-NEXT: s_mov_b64 s[4:5], 0 ; GFX9-NEXT: v_mov_b32_e32 v9, 0 ; GFX9-NEXT: .LBB0_3: ; %udiv-do-while ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -948,95 +948,93 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_waitcnt vmcnt(9) ; GFX9-O0-NEXT: v_mov_b32_e32 v4, v10 ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: v_lshrrev_b64 v[6:7], v4, v[20:21] +; GFX9-O0-NEXT: v_lshrrev_b64 v[6:7], v4, v[18:19] ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v7 -; GFX9-O0-NEXT: s_mov_b32 s6, 64 -; GFX9-O0-NEXT: v_sub_u32_e64 v12, s6, v4 -; GFX9-O0-NEXT: v_lshlrev_b64 v[22:23], v12, v[18:19] -; GFX9-O0-NEXT: v_mov_b32_e32 v12, v23 -; GFX9-O0-NEXT: v_or_b32_e64 v5, v5, v12 +; GFX9-O0-NEXT: s_mov_b32 s4, 64 +; GFX9-O0-NEXT: v_sub_u32_e64 v20, s4, v4 +; GFX9-O0-NEXT: v_lshlrev_b64 v[20:21], v20, v[14:15] +; GFX9-O0-NEXT: v_mov_b32_e32 v22, v21 +; GFX9-O0-NEXT: v_or_b32_e64 v5, v5, v22 ; GFX9-O0-NEXT: ; kill: def $vgpr6 killed $vgpr6 killed $vgpr6_vgpr7 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v7, v22 +; GFX9-O0-NEXT: v_mov_b32_e32 v7, v20 ; GFX9-O0-NEXT: v_or_b32_e64 v6, v6, v7 ; GFX9-O0-NEXT: ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v5 -; GFX9-O0-NEXT: v_mov_b32_e32 v12, v7 -; GFX9-O0-NEXT: v_cmp_lt_u32_e64 s[4:5], v4, s6 -; GFX9-O0-NEXT: v_sub_u32_e64 v5, v4, s6 -; GFX9-O0-NEXT: v_lshrrev_b64 v[22:23], v5, v[18:19] -; GFX9-O0-NEXT: v_mov_b32_e32 v5, v23 -; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v12, s[4:5] -; GFX9-O0-NEXT: s_mov_b32 s6, 0 -; GFX9-O0-NEXT: v_cmp_eq_u32_e64 s[6:7], v4, s6 -; GFX9-O0-NEXT: v_mov_b32_e32 v12, v21 -; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v12, s[6:7] +; GFX9-O0-NEXT: v_mov_b32_e32 v22, v7 +; GFX9-O0-NEXT: v_cmp_lt_u32_e64 s[6:7], v4, s4 +; GFX9-O0-NEXT: v_sub_u32_e64 v5, v4, s4 +; GFX9-O0-NEXT: v_lshrrev_b64 v[20:21], v5, v[14:15] +; GFX9-O0-NEXT: v_mov_b32_e32 v5, v21 +; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v22, s[6:7] +; GFX9-O0-NEXT: s_mov_b32 s4, 0 +; GFX9-O0-NEXT: v_cmp_eq_u32_e64 s[4:5], v4, s4 +; GFX9-O0-NEXT: v_mov_b32_e32 v22, v19 +; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v22, s[4:5] ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v6 -; GFX9-O0-NEXT: v_mov_b32_e32 v6, v22 -; GFX9-O0-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[4:5] -; GFX9-O0-NEXT: v_mov_b32_e32 v7, v20 +; GFX9-O0-NEXT: v_mov_b32_e32 v6, v20 ; GFX9-O0-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[6:7] -; GFX9-O0-NEXT: ; implicit-def: $sgpr6 -; GFX9-O0-NEXT: ; implicit-def: $sgpr6 +; GFX9-O0-NEXT: v_mov_b32_e32 v7, v18 +; GFX9-O0-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[4:5] +; GFX9-O0-NEXT: ; implicit-def: $sgpr4 +; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v5 -; GFX9-O0-NEXT: v_lshrrev_b64 v[4:5], v4, v[18:19] +; GFX9-O0-NEXT: v_lshrrev_b64 v[4:5], v4, v[14:15] ; GFX9-O0-NEXT: v_mov_b32_e32 v15, v5 -; GFX9-O0-NEXT: s_mov_b64 s[6:7], 0 -; GFX9-O0-NEXT: s_mov_b32 s8, s7 -; GFX9-O0-NEXT: v_mov_b32_e32 v12, s8 -; GFX9-O0-NEXT: v_cndmask_b32_e64 v12, v12, v15, s[4:5] +; GFX9-O0-NEXT: s_mov_b64 s[4:5], 0 +; GFX9-O0-NEXT: s_mov_b32 s8, s5 +; GFX9-O0-NEXT: v_mov_b32_e32 v14, s8 +; GFX9-O0-NEXT: v_cndmask_b32_e64 v14, v14, v15, s[6:7] ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v4 -; GFX9-O0-NEXT: s_mov_b32 s8, s6 +; GFX9-O0-NEXT: s_mov_b32 s8, s4 ; GFX9-O0-NEXT: v_mov_b32_e32 v4, s8 -; GFX9-O0-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[4:5] -; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; implicit-def: $sgpr4 +; GFX9-O0-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[6:7] +; GFX9-O0-NEXT: ; implicit-def: $sgpr6 +; GFX9-O0-NEXT: ; implicit-def: $sgpr6 ; GFX9-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v5, v12 +; GFX9-O0-NEXT: v_mov_b32_e32 v5, v14 +; GFX9-O0-NEXT: v_mov_b32_e32 v15, v12 ; GFX9-O0-NEXT: v_mov_b32_e32 v12, v13 -; GFX9-O0-NEXT: v_mov_b32_e32 v15, v14 ; GFX9-O0-NEXT: s_mov_b64 s[8:9], -1 -; GFX9-O0-NEXT: s_mov_b32 s5, s8 -; GFX9-O0-NEXT: s_mov_b32 s4, s9 +; GFX9-O0-NEXT: s_mov_b32 s7, s8 +; GFX9-O0-NEXT: s_mov_b32 s6, s9 ; GFX9-O0-NEXT: v_mov_b32_e32 v14, v16 ; GFX9-O0-NEXT: v_mov_b32_e32 v13, v17 -; GFX9-O0-NEXT: v_mov_b32_e32 v16, s5 -; GFX9-O0-NEXT: v_add_co_u32_e32 v12, vcc, v12, v16 -; GFX9-O0-NEXT: v_mov_b32_e32 v16, s4 -; GFX9-O0-NEXT: v_addc_co_u32_e32 v16, vcc, v15, v16, vcc +; GFX9-O0-NEXT: v_mov_b32_e32 v16, s7 +; GFX9-O0-NEXT: v_add_co_u32_e32 v16, vcc, v15, v16 +; GFX9-O0-NEXT: v_mov_b32_e32 v15, s6 +; GFX9-O0-NEXT: v_addc_co_u32_e32 v12, vcc, v12, v15, vcc +; GFX9-O0-NEXT: v_mov_b32_e32 v15, s7 +; GFX9-O0-NEXT: v_addc_co_u32_e32 v18, vcc, v14, v15, vcc +; GFX9-O0-NEXT: v_mov_b32_e32 v14, s6 +; GFX9-O0-NEXT: v_addc_co_u32_e32 v13, vcc, v13, v14, vcc +; GFX9-O0-NEXT: ; implicit-def: $sgpr6 +; GFX9-O0-NEXT: ; implicit-def: $sgpr6 +; GFX9-O0-NEXT: ; kill: def $vgpr18 killed $vgpr18 def $vgpr18_vgpr19 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v19, v13 +; GFX9-O0-NEXT: ; implicit-def: $sgpr6 +; GFX9-O0-NEXT: ; implicit-def: $sgpr6 +; GFX9-O0-NEXT: ; kill: def $vgpr16 killed $vgpr16 def $vgpr16_vgpr17 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v17, v12 +; GFX9-O0-NEXT: v_mov_b32_e32 v13, s5 +; GFX9-O0-NEXT: v_mov_b32_e32 v12, s4 ; GFX9-O0-NEXT: v_mov_b32_e32 v15, s5 -; GFX9-O0-NEXT: v_addc_co_u32_e32 v14, vcc, v14, v15, vcc -; GFX9-O0-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-O0-NEXT: v_addc_co_u32_e32 v13, vcc, v13, v15, vcc -; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr14 killed $vgpr14 def $vgpr14_vgpr15 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v15, v13 -; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v13, v16 -; GFX9-O0-NEXT: s_mov_b64 s[8:9], s[6:7] -; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v14, s4 +; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_nop 0 -; GFX9-O0-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_nop 0 -; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill -; GFX9-O0-NEXT: s_mov_b64 s[4:5], s[6:7] -; GFX9-O0-NEXT: v_mov_b32_e32 v15, s9 -; GFX9-O0-NEXT: v_mov_b32_e32 v14, s8 -; GFX9-O0-NEXT: v_mov_b32_e32 v13, s7 -; GFX9-O0-NEXT: v_mov_b32_e32 v12, s6 +; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill ; GFX9-O0-NEXT: v_writelane_b32 v30, s4, 10 ; GFX9-O0-NEXT: v_writelane_b32 v30, s5, 11 ; GFX9-O0-NEXT: s_or_saveexec_b64 s[22:23], -1 @@ -1176,11 +1174,10 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v1, v2 ; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[4:5], v[0:1], s[6:7] -; GFX9-O0-NEXT: s_mov_b64 s[8:9], s[6:7] -; GFX9-O0-NEXT: v_mov_b32_e32 v2, s8 -; GFX9-O0-NEXT: v_mov_b32_e32 v3, s9 ; GFX9-O0-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-O0-NEXT: v_mov_b32_e32 v1, s7 +; GFX9-O0-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-O0-NEXT: v_mov_b32_e32 v3, s7 ; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_nop 0 ; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill @@ -1616,12 +1613,12 @@ define i128 @v_urem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-NEXT: v_add_co_u32_e32 v26, vcc, -1, v4 ; GFX9-NEXT: v_addc_co_u32_e32 v27, vcc, -1, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v28, vcc, -1, v6, vcc -; GFX9-NEXT: v_mov_b32_e32 v20, 0 ; GFX9-NEXT: v_mov_b32_e32 v14, 0 +; GFX9-NEXT: v_mov_b32_e32 v20, 0 ; GFX9-NEXT: v_addc_co_u32_e32 v29, vcc, -1, v7, vcc -; GFX9-NEXT: s_mov_b64 s[4:5], 0 -; GFX9-NEXT: v_mov_b32_e32 v21, 0 ; GFX9-NEXT: v_mov_b32_e32 v15, 0 +; GFX9-NEXT: v_mov_b32_e32 v21, 0 +; GFX9-NEXT: s_mov_b64 s[4:5], 0 ; GFX9-NEXT: v_mov_b32_e32 v13, 0 ; GFX9-NEXT: .LBB1_3: ; %udiv-do-while ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -2327,95 +2324,93 @@ define i128 @v_urem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_waitcnt vmcnt(9) ; GFX9-O0-NEXT: v_mov_b32_e32 v4, v10 ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: v_lshrrev_b64 v[6:7], v4, v[20:21] +; GFX9-O0-NEXT: v_lshrrev_b64 v[6:7], v4, v[18:19] ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v7 -; GFX9-O0-NEXT: s_mov_b32 s6, 64 -; GFX9-O0-NEXT: v_sub_u32_e64 v12, s6, v4 -; GFX9-O0-NEXT: v_lshlrev_b64 v[22:23], v12, v[18:19] -; GFX9-O0-NEXT: v_mov_b32_e32 v12, v23 -; GFX9-O0-NEXT: v_or_b32_e64 v5, v5, v12 +; GFX9-O0-NEXT: s_mov_b32 s4, 64 +; GFX9-O0-NEXT: v_sub_u32_e64 v20, s4, v4 +; GFX9-O0-NEXT: v_lshlrev_b64 v[20:21], v20, v[14:15] +; GFX9-O0-NEXT: v_mov_b32_e32 v22, v21 +; GFX9-O0-NEXT: v_or_b32_e64 v5, v5, v22 ; GFX9-O0-NEXT: ; kill: def $vgpr6 killed $vgpr6 killed $vgpr6_vgpr7 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v7, v22 +; GFX9-O0-NEXT: v_mov_b32_e32 v7, v20 ; GFX9-O0-NEXT: v_or_b32_e64 v6, v6, v7 ; GFX9-O0-NEXT: ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v5 -; GFX9-O0-NEXT: v_mov_b32_e32 v12, v7 -; GFX9-O0-NEXT: v_cmp_lt_u32_e64 s[4:5], v4, s6 -; GFX9-O0-NEXT: v_sub_u32_e64 v5, v4, s6 -; GFX9-O0-NEXT: v_lshrrev_b64 v[22:23], v5, v[18:19] -; GFX9-O0-NEXT: v_mov_b32_e32 v5, v23 -; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v12, s[4:5] -; GFX9-O0-NEXT: s_mov_b32 s6, 0 -; GFX9-O0-NEXT: v_cmp_eq_u32_e64 s[6:7], v4, s6 -; GFX9-O0-NEXT: v_mov_b32_e32 v12, v21 -; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v12, s[6:7] +; GFX9-O0-NEXT: v_mov_b32_e32 v22, v7 +; GFX9-O0-NEXT: v_cmp_lt_u32_e64 s[6:7], v4, s4 +; GFX9-O0-NEXT: v_sub_u32_e64 v5, v4, s4 +; GFX9-O0-NEXT: v_lshrrev_b64 v[20:21], v5, v[14:15] +; GFX9-O0-NEXT: v_mov_b32_e32 v5, v21 +; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v22, s[6:7] +; GFX9-O0-NEXT: s_mov_b32 s4, 0 +; GFX9-O0-NEXT: v_cmp_eq_u32_e64 s[4:5], v4, s4 +; GFX9-O0-NEXT: v_mov_b32_e32 v22, v19 +; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v22, s[4:5] ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v6 -; GFX9-O0-NEXT: v_mov_b32_e32 v6, v22 -; GFX9-O0-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[4:5] -; GFX9-O0-NEXT: v_mov_b32_e32 v7, v20 +; GFX9-O0-NEXT: v_mov_b32_e32 v6, v20 ; GFX9-O0-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[6:7] -; GFX9-O0-NEXT: ; implicit-def: $sgpr6 -; GFX9-O0-NEXT: ; implicit-def: $sgpr6 +; GFX9-O0-NEXT: v_mov_b32_e32 v7, v18 +; GFX9-O0-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[4:5] +; GFX9-O0-NEXT: ; implicit-def: $sgpr4 +; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v5 -; GFX9-O0-NEXT: v_lshrrev_b64 v[4:5], v4, v[18:19] +; GFX9-O0-NEXT: v_lshrrev_b64 v[4:5], v4, v[14:15] ; GFX9-O0-NEXT: v_mov_b32_e32 v15, v5 -; GFX9-O0-NEXT: s_mov_b64 s[6:7], 0 -; GFX9-O0-NEXT: s_mov_b32 s8, s7 -; GFX9-O0-NEXT: v_mov_b32_e32 v12, s8 -; GFX9-O0-NEXT: v_cndmask_b32_e64 v12, v12, v15, s[4:5] +; GFX9-O0-NEXT: s_mov_b64 s[4:5], 0 +; GFX9-O0-NEXT: s_mov_b32 s8, s5 +; GFX9-O0-NEXT: v_mov_b32_e32 v14, s8 +; GFX9-O0-NEXT: v_cndmask_b32_e64 v14, v14, v15, s[6:7] ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v4 -; GFX9-O0-NEXT: s_mov_b32 s8, s6 +; GFX9-O0-NEXT: s_mov_b32 s8, s4 ; GFX9-O0-NEXT: v_mov_b32_e32 v4, s8 -; GFX9-O0-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[4:5] -; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; implicit-def: $sgpr4 +; GFX9-O0-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[6:7] +; GFX9-O0-NEXT: ; implicit-def: $sgpr6 +; GFX9-O0-NEXT: ; implicit-def: $sgpr6 ; GFX9-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v5, v12 +; GFX9-O0-NEXT: v_mov_b32_e32 v5, v14 +; GFX9-O0-NEXT: v_mov_b32_e32 v15, v12 ; GFX9-O0-NEXT: v_mov_b32_e32 v12, v13 -; GFX9-O0-NEXT: v_mov_b32_e32 v15, v14 ; GFX9-O0-NEXT: s_mov_b64 s[8:9], -1 -; GFX9-O0-NEXT: s_mov_b32 s5, s8 -; GFX9-O0-NEXT: s_mov_b32 s4, s9 +; GFX9-O0-NEXT: s_mov_b32 s7, s8 +; GFX9-O0-NEXT: s_mov_b32 s6, s9 ; GFX9-O0-NEXT: v_mov_b32_e32 v14, v16 ; GFX9-O0-NEXT: v_mov_b32_e32 v13, v17 -; GFX9-O0-NEXT: v_mov_b32_e32 v16, s5 -; GFX9-O0-NEXT: v_add_co_u32_e32 v12, vcc, v12, v16 -; GFX9-O0-NEXT: v_mov_b32_e32 v16, s4 -; GFX9-O0-NEXT: v_addc_co_u32_e32 v16, vcc, v15, v16, vcc +; GFX9-O0-NEXT: v_mov_b32_e32 v16, s7 +; GFX9-O0-NEXT: v_add_co_u32_e32 v16, vcc, v15, v16 +; GFX9-O0-NEXT: v_mov_b32_e32 v15, s6 +; GFX9-O0-NEXT: v_addc_co_u32_e32 v12, vcc, v12, v15, vcc +; GFX9-O0-NEXT: v_mov_b32_e32 v15, s7 +; GFX9-O0-NEXT: v_addc_co_u32_e32 v18, vcc, v14, v15, vcc +; GFX9-O0-NEXT: v_mov_b32_e32 v14, s6 +; GFX9-O0-NEXT: v_addc_co_u32_e32 v13, vcc, v13, v14, vcc +; GFX9-O0-NEXT: ; implicit-def: $sgpr6 +; GFX9-O0-NEXT: ; implicit-def: $sgpr6 +; GFX9-O0-NEXT: ; kill: def $vgpr18 killed $vgpr18 def $vgpr18_vgpr19 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v19, v13 +; GFX9-O0-NEXT: ; implicit-def: $sgpr6 +; GFX9-O0-NEXT: ; implicit-def: $sgpr6 +; GFX9-O0-NEXT: ; kill: def $vgpr16 killed $vgpr16 def $vgpr16_vgpr17 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v17, v12 +; GFX9-O0-NEXT: v_mov_b32_e32 v13, s5 +; GFX9-O0-NEXT: v_mov_b32_e32 v12, s4 ; GFX9-O0-NEXT: v_mov_b32_e32 v15, s5 -; GFX9-O0-NEXT: v_addc_co_u32_e32 v14, vcc, v14, v15, vcc -; GFX9-O0-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-O0-NEXT: v_addc_co_u32_e32 v13, vcc, v13, v15, vcc -; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr14 killed $vgpr14 def $vgpr14_vgpr15 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v15, v13 -; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v13, v16 -; GFX9-O0-NEXT: s_mov_b64 s[8:9], s[6:7] -; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v14, s4 +; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_nop 0 -; GFX9-O0-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_nop 0 -; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill -; GFX9-O0-NEXT: s_mov_b64 s[4:5], s[6:7] -; GFX9-O0-NEXT: v_mov_b32_e32 v15, s9 -; GFX9-O0-NEXT: v_mov_b32_e32 v14, s8 -; GFX9-O0-NEXT: v_mov_b32_e32 v13, s7 -; GFX9-O0-NEXT: v_mov_b32_e32 v12, s6 +; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill ; GFX9-O0-NEXT: v_writelane_b32 v30, s4, 8 ; GFX9-O0-NEXT: v_writelane_b32 v30, s5, 9 ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 @@ -2555,11 +2550,10 @@ define i128 @v_urem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v1, v2 ; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[4:5], v[0:1], s[6:7] -; GFX9-O0-NEXT: s_mov_b64 s[8:9], s[6:7] -; GFX9-O0-NEXT: v_mov_b32_e32 v2, s8 -; GFX9-O0-NEXT: v_mov_b32_e32 v3, s9 ; GFX9-O0-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-O0-NEXT: v_mov_b32_e32 v1, s7 +; GFX9-O0-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-O0-NEXT: v_mov_b32_e32 v3, s7 ; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_nop 0 ; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill diff --git a/llvm/test/CodeGen/AMDGPU/scheduler-rp-calc-one-successor-two-predecessors-bug.ll b/llvm/test/CodeGen/AMDGPU/scheduler-rp-calc-one-successor-two-predecessors-bug.ll index 8cb1d250a6fa7..1718002a222c9 100644 --- a/llvm/test/CodeGen/AMDGPU/scheduler-rp-calc-one-successor-two-predecessors-bug.ll +++ b/llvm/test/CodeGen/AMDGPU/scheduler-rp-calc-one-successor-two-predecessors-bug.ll @@ -15,9 +15,9 @@ define amdgpu_ps void @_amdgpu_ps_main(float %arg) { ; GFX900-NEXT: s_mov_b32 s0, 0 ; GFX900-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v1 ; GFX900-NEXT: ; implicit-def: $vgpr0 -; GFX900-NEXT: ; implicit-def: $sgpr2 -; GFX900-NEXT: s_and_saveexec_b64 s[6:7], vcc -; GFX900-NEXT: s_xor_b64 s[6:7], exec, s[6:7] +; GFX900-NEXT: ; implicit-def: $vgpr2 +; GFX900-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX900-NEXT: s_xor_b64 s[6:7], exec, s[2:3] ; GFX900-NEXT: s_cbranch_execz .LBB0_2 ; GFX900-NEXT: ; %bb.1: ; %bb1 ; GFX900-NEXT: v_mov_b32_e32 v0, 0 @@ -33,12 +33,11 @@ define amdgpu_ps void @_amdgpu_ps_main(float %arg) { ; GFX900-NEXT: s_mov_b32 s14, s0 ; GFX900-NEXT: s_mov_b32 s15, s0 ; GFX900-NEXT: image_sample v[0:1], v[0:1], s[8:15], s[0:3] dmask:0x3 -; GFX900-NEXT: s_mov_b32 s2, 1.0 +; GFX900-NEXT: v_mov_b32_e32 v2, 1.0 ; GFX900-NEXT: .LBB0_2: ; %Flow ; GFX900-NEXT: s_or_saveexec_b64 s[0:1], s[6:7] ; GFX900-NEXT: s_and_b64 exec, exec, s[4:5] ; GFX900-NEXT: s_and_b64 s[0:1], exec, s[0:1] -; GFX900-NEXT: v_mov_b32_e32 v2, s2 ; GFX900-NEXT: s_xor_b64 exec, exec, s[0:1] ; GFX900-NEXT: s_cbranch_execz .LBB0_5 ; GFX900-NEXT: ; %bb.3: ; %bb5 diff --git a/llvm/test/CodeGen/AMDGPU/sdiv64.ll b/llvm/test/CodeGen/AMDGPU/sdiv64.ll index 96dd6276f7e38..a166c4f93462d 100644 --- a/llvm/test/CodeGen/AMDGPU/sdiv64.ll +++ b/llvm/test/CodeGen/AMDGPU/sdiv64.ll @@ -394,9 +394,9 @@ define i64 @v_test_sdiv(i64 %x, i64 %y) { ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v2 ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2 +; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[6:7], v2 -; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] @@ -1436,9 +1436,9 @@ define i64 @v_test_sdiv_k_num_i64(i64 %x) { ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v2 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2 +; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7] ; GCN-IR-NEXT: v_lshl_b64 v[2:3], 24, v2 -; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] @@ -1631,9 +1631,9 @@ define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) { ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000 +; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7] ; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[4:5], v2 -; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[8:9], vcc ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[8:9] @@ -1730,9 +1730,9 @@ define i64 @v_test_sdiv_pow2_k_den_i64(i64 %x) { ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v0 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc ; GCN-IR-NEXT: v_sub_i32_e64 v0, s[4:5], 63, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7] ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], v0 -; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] diff --git a/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll b/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll index 7b82a6b6dcaa2..168128a82b7ec 100644 --- a/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll +++ b/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll @@ -2016,7 +2016,6 @@ define amdgpu_kernel void @sdwa_crash_inlineasm_def() #0 { ; NOSDWA: ; %bb.0: ; %bb ; NOSDWA-NEXT: s_mov_b32 s0, 0xffff ; NOSDWA-NEXT: s_and_b64 vcc, exec, -1 -; NOSDWA-NEXT: ; implicit-def: $vgpr0_vgpr1 ; NOSDWA-NEXT: .LBB21_1: ; %bb1 ; NOSDWA-NEXT: ; =>This Inner Loop Header: Depth=1 ; NOSDWA-NEXT: ;;#ASMSTART @@ -2034,7 +2033,6 @@ define amdgpu_kernel void @sdwa_crash_inlineasm_def() #0 { ; GFX89: ; %bb.0: ; %bb ; GFX89-NEXT: s_mov_b32 s0, 0xffff ; GFX89-NEXT: s_and_b64 vcc, exec, -1 -; GFX89-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX89-NEXT: .LBB21_1: ; %bb1 ; GFX89-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX89-NEXT: ;;#ASMSTART @@ -2052,7 +2050,6 @@ define amdgpu_kernel void @sdwa_crash_inlineasm_def() #0 { ; GFX9: ; %bb.0: ; %bb ; GFX9-NEXT: s_mov_b32 s0, 0xffff ; GFX9-NEXT: s_and_b64 vcc, exec, -1 -; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX9-NEXT: .LBB21_1: ; %bb1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ;;#ASMSTART @@ -2070,7 +2067,6 @@ define amdgpu_kernel void @sdwa_crash_inlineasm_def() #0 { ; GFX10: ; %bb.0: ; %bb ; GFX10-NEXT: s_mov_b32 s0, 0xffff ; GFX10-NEXT: s_mov_b32 vcc_lo, exec_lo -; GFX10-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX10-NEXT: .LBB21_1: ; %bb1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ;;#ASMSTART diff --git a/llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll b/llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll index f60786c1bacbf..6f841c88a6d8b 100644 --- a/llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll +++ b/llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll @@ -4,8 +4,8 @@ define amdgpu_cs void @if_then(ptr addrspace(8) inreg %input, ptr addrspace(8) inreg %output, <3 x i32> %LocalInvocationId) { ; GCN-LABEL: if_then: ; GCN: ; %bb.0: ; %.entry -; GCN-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GCN-NEXT: v_mov_b32_e32 v3, 0 +; GCN-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GCN-NEXT: s_and_saveexec_b32 s0, vcc_lo ; GCN-NEXT: ; %bb.1: ; %.bb0 ; GCN-NEXT: v_mov_b32_e32 v3, 1 @@ -60,8 +60,8 @@ define amdgpu_cs void @if_then(ptr addrspace(8) inreg %input, ptr addrspace(8) i define amdgpu_cs void @if_else_vgpr_opt(ptr addrspace(8) inreg %input, ptr addrspace(8) inreg %output, <3 x i32> %LocalInvocationId) { ; GCN-LABEL: if_else_vgpr_opt: ; GCN: ; %bb.0: ; %.entry -; GCN-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GCN-NEXT: v_mov_b32_e32 v3, 0 +; GCN-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GCN-NEXT: s_and_saveexec_b32 s0, vcc_lo ; GCN-NEXT: ; %bb.1: ; %.bb0 ; GCN-NEXT: v_mov_b32_e32 v3, 1 diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll b/llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll index be31078d86860..220e8705af252 100644 --- a/llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll +++ b/llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll @@ -172,8 +172,7 @@ define amdgpu_kernel void @sgpr_if_else_valu_cmp_phi_br(ptr addrspace(1) %out, p ; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v0 -; SI-NEXT: s_and_b64 s[8:9], vcc, exec +; SI-NEXT: v_cmp_gt_i32_e64 s[8:9], 0, v0 ; SI-NEXT: ; implicit-def: $vgpr0 ; SI-NEXT: .LBB3_2: ; %Flow ; SI-NEXT: s_waitcnt lgkmcnt(0) diff --git a/llvm/test/CodeGen/AMDGPU/srem64.ll b/llvm/test/CodeGen/AMDGPU/srem64.ll index 23364e860d154..c9e5ff444f715 100644 --- a/llvm/test/CodeGen/AMDGPU/srem64.ll +++ b/llvm/test/CodeGen/AMDGPU/srem64.ll @@ -370,9 +370,9 @@ define i64 @v_test_srem(i64 %x, i64 %y) { ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v4 +; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4 -; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] @@ -1553,9 +1553,9 @@ define i64 @v_test_srem_k_num_i64(i64 %x) { ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v2 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2 +; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7] ; GCN-IR-NEXT: v_lshl_b64 v[2:3], 24, v2 -; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] @@ -1746,9 +1746,9 @@ define i64 @v_test_srem_pow2_k_num_i64(i64 %x) { ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000 +; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7] ; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[4:5], v2 -; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[8:9], vcc ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[8:9] @@ -1851,9 +1851,9 @@ define i64 @v_test_srem_pow2_k_den_i64(i64 %x) { ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v2 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2 +; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7] ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 -; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] diff --git a/llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll b/llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll index a6e6341914ed0..54b1d1e6f3f43 100644 --- a/llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll +++ b/llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll @@ -99,17 +99,17 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i ; GLOBALNESS1-NEXT: .LBB1_1: ; %bb70.i ; GLOBALNESS1-NEXT: ; in Loop: Header=BB1_4 Depth=1 ; GLOBALNESS1-NEXT: s_and_b64 vcc, exec, s[60:61] -; GLOBALNESS1-NEXT: s_cbranch_vccz .LBB1_29 +; GLOBALNESS1-NEXT: s_cbranch_vccz .LBB1_28 ; GLOBALNESS1-NEXT: .LBB1_2: ; %Flow15 ; GLOBALNESS1-NEXT: ; in Loop: Header=BB1_4 Depth=1 ; GLOBALNESS1-NEXT: s_or_b64 exec, exec, s[4:5] -; GLOBALNESS1-NEXT: s_mov_b64 s[6:7], 0 +; GLOBALNESS1-NEXT: s_mov_b64 s[8:9], 0 ; GLOBALNESS1-NEXT: ; implicit-def: $sgpr4_sgpr5 ; GLOBALNESS1-NEXT: .LBB1_3: ; %Flow28 ; GLOBALNESS1-NEXT: ; in Loop: Header=BB1_4 Depth=1 -; GLOBALNESS1-NEXT: s_and_b64 vcc, exec, s[6:7] +; GLOBALNESS1-NEXT: s_and_b64 vcc, exec, s[8:9] ; GLOBALNESS1-NEXT: v_pk_mov_b32 v[56:57], v[0:1], v[0:1] op_sel:[0,1] -; GLOBALNESS1-NEXT: s_cbranch_vccnz .LBB1_30 +; GLOBALNESS1-NEXT: s_cbranch_vccnz .LBB1_29 ; GLOBALNESS1-NEXT: .LBB1_4: ; %bb5 ; GLOBALNESS1-NEXT: ; =>This Loop Header: Depth=1 ; GLOBALNESS1-NEXT: ; Child Loop BB1_16 Depth 2 @@ -156,8 +156,10 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i ; GLOBALNESS1-NEXT: s_cselect_b64 s[6:7], -1, 0 ; GLOBALNESS1-NEXT: .LBB1_9: ; %Flow25 ; GLOBALNESS1-NEXT: ; in Loop: Header=BB1_4 Depth=1 +; GLOBALNESS1-NEXT: s_mov_b64 s[8:9], -1 ; GLOBALNESS1-NEXT: s_and_b64 vcc, exec, s[6:7] -; GLOBALNESS1-NEXT: s_cbranch_vccz .LBB1_24 +; GLOBALNESS1-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GLOBALNESS1-NEXT: s_cbranch_vccz .LBB1_3 ; GLOBALNESS1-NEXT: ; %bb.10: ; %baz.exit.i ; GLOBALNESS1-NEXT: ; in Loop: Header=BB1_4 Depth=1 ; GLOBALNESS1-NEXT: flat_load_dword v0, v[44:45] @@ -166,7 +168,7 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i ; GLOBALNESS1-NEXT: v_mov_b32_e32 v0, 0 ; GLOBALNESS1-NEXT: v_mov_b32_e32 v1, 0x3ff00000 ; GLOBALNESS1-NEXT: s_and_saveexec_b64 s[74:75], s[62:63] -; GLOBALNESS1-NEXT: s_cbranch_execz .LBB1_26 +; GLOBALNESS1-NEXT: s_cbranch_execz .LBB1_25 ; GLOBALNESS1-NEXT: ; %bb.11: ; %bb33.i ; GLOBALNESS1-NEXT: ; in Loop: Header=BB1_4 Depth=1 ; GLOBALNESS1-NEXT: global_load_dwordx2 v[0:1], v[44:45], off @@ -192,7 +194,7 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i ; GLOBALNESS1-NEXT: .LBB1_15: ; %bb63.i ; GLOBALNESS1-NEXT: ; in Loop: Header=BB1_16 Depth=2 ; GLOBALNESS1-NEXT: s_and_b64 vcc, exec, s[52:53] -; GLOBALNESS1-NEXT: s_cbranch_vccz .LBB1_25 +; GLOBALNESS1-NEXT: s_cbranch_vccz .LBB1_24 ; GLOBALNESS1-NEXT: .LBB1_16: ; %bb44.i ; GLOBALNESS1-NEXT: ; Parent Loop BB1_4 Depth=1 ; GLOBALNESS1-NEXT: ; => This Inner Loop Header: Depth=2 @@ -252,37 +254,33 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i ; GLOBALNESS1-NEXT: v_mov_b32_e32 v43, v42 ; GLOBALNESS1-NEXT: global_store_dwordx2 v[44:45], v[42:43], off ; GLOBALNESS1-NEXT: s_branch .LBB1_14 -; GLOBALNESS1-NEXT: .LBB1_24: ; in Loop: Header=BB1_4 Depth=1 -; GLOBALNESS1-NEXT: s_mov_b64 s[6:7], -1 -; GLOBALNESS1-NEXT: ; implicit-def: $vgpr0_vgpr1 -; GLOBALNESS1-NEXT: s_branch .LBB1_3 -; GLOBALNESS1-NEXT: .LBB1_25: ; %Flow23 +; GLOBALNESS1-NEXT: .LBB1_24: ; %Flow23 ; GLOBALNESS1-NEXT: ; in Loop: Header=BB1_4 Depth=1 ; GLOBALNESS1-NEXT: v_pk_mov_b32 v[0:1], 0, 0 -; GLOBALNESS1-NEXT: .LBB1_26: ; %Flow24 +; GLOBALNESS1-NEXT: .LBB1_25: ; %Flow24 ; GLOBALNESS1-NEXT: ; in Loop: Header=BB1_4 Depth=1 ; GLOBALNESS1-NEXT: s_or_b64 exec, exec, s[74:75] ; GLOBALNESS1-NEXT: s_and_saveexec_b64 s[4:5], s[62:63] ; GLOBALNESS1-NEXT: s_cbranch_execz .LBB1_2 -; GLOBALNESS1-NEXT: ; %bb.27: ; %bb67.i +; GLOBALNESS1-NEXT: ; %bb.26: ; %bb67.i ; GLOBALNESS1-NEXT: ; in Loop: Header=BB1_4 Depth=1 ; GLOBALNESS1-NEXT: s_and_b64 vcc, exec, s[58:59] ; GLOBALNESS1-NEXT: s_cbranch_vccnz .LBB1_1 -; GLOBALNESS1-NEXT: ; %bb.28: ; %bb69.i +; GLOBALNESS1-NEXT: ; %bb.27: ; %bb69.i ; GLOBALNESS1-NEXT: ; in Loop: Header=BB1_4 Depth=1 ; GLOBALNESS1-NEXT: v_mov_b32_e32 v43, v42 ; GLOBALNESS1-NEXT: global_store_dwordx2 v[44:45], v[42:43], off ; GLOBALNESS1-NEXT: s_branch .LBB1_1 -; GLOBALNESS1-NEXT: .LBB1_29: ; %bb73.i +; GLOBALNESS1-NEXT: .LBB1_28: ; %bb73.i ; GLOBALNESS1-NEXT: ; in Loop: Header=BB1_4 Depth=1 ; GLOBALNESS1-NEXT: v_mov_b32_e32 v43, v42 ; GLOBALNESS1-NEXT: global_store_dwordx2 v[44:45], v[42:43], off ; GLOBALNESS1-NEXT: s_branch .LBB1_2 -; GLOBALNESS1-NEXT: .LBB1_30: ; %loop.exit.guard +; GLOBALNESS1-NEXT: .LBB1_29: ; %loop.exit.guard ; GLOBALNESS1-NEXT: s_andn2_b64 vcc, exec, s[4:5] ; GLOBALNESS1-NEXT: s_mov_b64 s[4:5], -1 -; GLOBALNESS1-NEXT: s_cbranch_vccz .LBB1_32 -; GLOBALNESS1-NEXT: ; %bb.31: ; %bb7.i.i +; GLOBALNESS1-NEXT: s_cbranch_vccz .LBB1_31 +; GLOBALNESS1-NEXT: ; %bb.30: ; %bb7.i.i ; GLOBALNESS1-NEXT: s_add_u32 s8, s38, 40 ; GLOBALNESS1-NEXT: s_addc_u32 s9, s39, 0 ; GLOBALNESS1-NEXT: s_getpc_b64 s[16:17] @@ -297,10 +295,10 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i ; GLOBALNESS1-NEXT: v_mov_b32_e32 v31, v41 ; GLOBALNESS1-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GLOBALNESS1-NEXT: s_mov_b64 s[4:5], 0 -; GLOBALNESS1-NEXT: .LBB1_32: ; %Flow +; GLOBALNESS1-NEXT: .LBB1_31: ; %Flow ; GLOBALNESS1-NEXT: s_andn2_b64 vcc, exec, s[4:5] -; GLOBALNESS1-NEXT: s_cbranch_vccnz .LBB1_34 -; GLOBALNESS1-NEXT: ; %bb.33: ; %bb11.i.i +; GLOBALNESS1-NEXT: s_cbranch_vccnz .LBB1_33 +; GLOBALNESS1-NEXT: ; %bb.32: ; %bb11.i.i ; GLOBALNESS1-NEXT: s_add_u32 s8, s38, 40 ; GLOBALNESS1-NEXT: s_addc_u32 s9, s39, 0 ; GLOBALNESS1-NEXT: s_getpc_b64 s[16:17] @@ -314,7 +312,7 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i ; GLOBALNESS1-NEXT: s_mov_b32 s14, s70 ; GLOBALNESS1-NEXT: v_mov_b32_e32 v31, v41 ; GLOBALNESS1-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GLOBALNESS1-NEXT: .LBB1_34: ; %UnifiedUnreachableBlock +; GLOBALNESS1-NEXT: .LBB1_33: ; %UnifiedUnreachableBlock ; ; GLOBALNESS0-LABEL: kernel: ; GLOBALNESS0: ; %bb.0: ; %bb @@ -386,17 +384,17 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i ; GLOBALNESS0-NEXT: .LBB1_1: ; %bb70.i ; GLOBALNESS0-NEXT: ; in Loop: Header=BB1_4 Depth=1 ; GLOBALNESS0-NEXT: s_and_b64 vcc, exec, s[60:61] -; GLOBALNESS0-NEXT: s_cbranch_vccz .LBB1_29 +; GLOBALNESS0-NEXT: s_cbranch_vccz .LBB1_28 ; GLOBALNESS0-NEXT: .LBB1_2: ; %Flow15 ; GLOBALNESS0-NEXT: ; in Loop: Header=BB1_4 Depth=1 ; GLOBALNESS0-NEXT: s_or_b64 exec, exec, s[4:5] -; GLOBALNESS0-NEXT: s_mov_b64 s[6:7], 0 +; GLOBALNESS0-NEXT: s_mov_b64 s[8:9], 0 ; GLOBALNESS0-NEXT: ; implicit-def: $sgpr4_sgpr5 ; GLOBALNESS0-NEXT: .LBB1_3: ; %Flow28 ; GLOBALNESS0-NEXT: ; in Loop: Header=BB1_4 Depth=1 -; GLOBALNESS0-NEXT: s_and_b64 vcc, exec, s[6:7] +; GLOBALNESS0-NEXT: s_and_b64 vcc, exec, s[8:9] ; GLOBALNESS0-NEXT: v_pk_mov_b32 v[56:57], v[0:1], v[0:1] op_sel:[0,1] -; GLOBALNESS0-NEXT: s_cbranch_vccnz .LBB1_30 +; GLOBALNESS0-NEXT: s_cbranch_vccnz .LBB1_29 ; GLOBALNESS0-NEXT: .LBB1_4: ; %bb5 ; GLOBALNESS0-NEXT: ; =>This Loop Header: Depth=1 ; GLOBALNESS0-NEXT: ; Child Loop BB1_16 Depth 2 @@ -443,8 +441,10 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i ; GLOBALNESS0-NEXT: s_cselect_b64 s[6:7], -1, 0 ; GLOBALNESS0-NEXT: .LBB1_9: ; %Flow25 ; GLOBALNESS0-NEXT: ; in Loop: Header=BB1_4 Depth=1 +; GLOBALNESS0-NEXT: s_mov_b64 s[8:9], -1 ; GLOBALNESS0-NEXT: s_and_b64 vcc, exec, s[6:7] -; GLOBALNESS0-NEXT: s_cbranch_vccz .LBB1_24 +; GLOBALNESS0-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GLOBALNESS0-NEXT: s_cbranch_vccz .LBB1_3 ; GLOBALNESS0-NEXT: ; %bb.10: ; %baz.exit.i ; GLOBALNESS0-NEXT: ; in Loop: Header=BB1_4 Depth=1 ; GLOBALNESS0-NEXT: flat_load_dword v0, v[44:45] @@ -453,7 +453,7 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i ; GLOBALNESS0-NEXT: v_mov_b32_e32 v0, 0 ; GLOBALNESS0-NEXT: v_mov_b32_e32 v1, 0x3ff00000 ; GLOBALNESS0-NEXT: s_and_saveexec_b64 s[76:77], s[62:63] -; GLOBALNESS0-NEXT: s_cbranch_execz .LBB1_26 +; GLOBALNESS0-NEXT: s_cbranch_execz .LBB1_25 ; GLOBALNESS0-NEXT: ; %bb.11: ; %bb33.i ; GLOBALNESS0-NEXT: ; in Loop: Header=BB1_4 Depth=1 ; GLOBALNESS0-NEXT: global_load_dwordx2 v[0:1], v[44:45], off @@ -479,7 +479,7 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i ; GLOBALNESS0-NEXT: .LBB1_15: ; %bb63.i ; GLOBALNESS0-NEXT: ; in Loop: Header=BB1_16 Depth=2 ; GLOBALNESS0-NEXT: s_and_b64 vcc, exec, s[52:53] -; GLOBALNESS0-NEXT: s_cbranch_vccz .LBB1_25 +; GLOBALNESS0-NEXT: s_cbranch_vccz .LBB1_24 ; GLOBALNESS0-NEXT: .LBB1_16: ; %bb44.i ; GLOBALNESS0-NEXT: ; Parent Loop BB1_4 Depth=1 ; GLOBALNESS0-NEXT: ; => This Inner Loop Header: Depth=2 @@ -539,37 +539,33 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i ; GLOBALNESS0-NEXT: v_mov_b32_e32 v43, v42 ; GLOBALNESS0-NEXT: global_store_dwordx2 v[44:45], v[42:43], off ; GLOBALNESS0-NEXT: s_branch .LBB1_14 -; GLOBALNESS0-NEXT: .LBB1_24: ; in Loop: Header=BB1_4 Depth=1 -; GLOBALNESS0-NEXT: s_mov_b64 s[6:7], -1 -; GLOBALNESS0-NEXT: ; implicit-def: $vgpr0_vgpr1 -; GLOBALNESS0-NEXT: s_branch .LBB1_3 -; GLOBALNESS0-NEXT: .LBB1_25: ; %Flow23 +; GLOBALNESS0-NEXT: .LBB1_24: ; %Flow23 ; GLOBALNESS0-NEXT: ; in Loop: Header=BB1_4 Depth=1 ; GLOBALNESS0-NEXT: v_pk_mov_b32 v[0:1], 0, 0 -; GLOBALNESS0-NEXT: .LBB1_26: ; %Flow24 +; GLOBALNESS0-NEXT: .LBB1_25: ; %Flow24 ; GLOBALNESS0-NEXT: ; in Loop: Header=BB1_4 Depth=1 ; GLOBALNESS0-NEXT: s_or_b64 exec, exec, s[76:77] ; GLOBALNESS0-NEXT: s_and_saveexec_b64 s[4:5], s[62:63] ; GLOBALNESS0-NEXT: s_cbranch_execz .LBB1_2 -; GLOBALNESS0-NEXT: ; %bb.27: ; %bb67.i +; GLOBALNESS0-NEXT: ; %bb.26: ; %bb67.i ; GLOBALNESS0-NEXT: ; in Loop: Header=BB1_4 Depth=1 ; GLOBALNESS0-NEXT: s_and_b64 vcc, exec, s[58:59] ; GLOBALNESS0-NEXT: s_cbranch_vccnz .LBB1_1 -; GLOBALNESS0-NEXT: ; %bb.28: ; %bb69.i +; GLOBALNESS0-NEXT: ; %bb.27: ; %bb69.i ; GLOBALNESS0-NEXT: ; in Loop: Header=BB1_4 Depth=1 ; GLOBALNESS0-NEXT: v_mov_b32_e32 v43, v42 ; GLOBALNESS0-NEXT: global_store_dwordx2 v[44:45], v[42:43], off ; GLOBALNESS0-NEXT: s_branch .LBB1_1 -; GLOBALNESS0-NEXT: .LBB1_29: ; %bb73.i +; GLOBALNESS0-NEXT: .LBB1_28: ; %bb73.i ; GLOBALNESS0-NEXT: ; in Loop: Header=BB1_4 Depth=1 ; GLOBALNESS0-NEXT: v_mov_b32_e32 v43, v42 ; GLOBALNESS0-NEXT: global_store_dwordx2 v[44:45], v[42:43], off ; GLOBALNESS0-NEXT: s_branch .LBB1_2 -; GLOBALNESS0-NEXT: .LBB1_30: ; %loop.exit.guard +; GLOBALNESS0-NEXT: .LBB1_29: ; %loop.exit.guard ; GLOBALNESS0-NEXT: s_andn2_b64 vcc, exec, s[4:5] ; GLOBALNESS0-NEXT: s_mov_b64 s[4:5], -1 -; GLOBALNESS0-NEXT: s_cbranch_vccz .LBB1_32 -; GLOBALNESS0-NEXT: ; %bb.31: ; %bb7.i.i +; GLOBALNESS0-NEXT: s_cbranch_vccz .LBB1_31 +; GLOBALNESS0-NEXT: ; %bb.30: ; %bb7.i.i ; GLOBALNESS0-NEXT: s_add_u32 s8, s38, 40 ; GLOBALNESS0-NEXT: s_addc_u32 s9, s39, 0 ; GLOBALNESS0-NEXT: s_getpc_b64 s[16:17] @@ -584,10 +580,10 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i ; GLOBALNESS0-NEXT: v_mov_b32_e32 v31, v41 ; GLOBALNESS0-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GLOBALNESS0-NEXT: s_mov_b64 s[4:5], 0 -; GLOBALNESS0-NEXT: .LBB1_32: ; %Flow +; GLOBALNESS0-NEXT: .LBB1_31: ; %Flow ; GLOBALNESS0-NEXT: s_andn2_b64 vcc, exec, s[4:5] -; GLOBALNESS0-NEXT: s_cbranch_vccnz .LBB1_34 -; GLOBALNESS0-NEXT: ; %bb.33: ; %bb11.i.i +; GLOBALNESS0-NEXT: s_cbranch_vccnz .LBB1_33 +; GLOBALNESS0-NEXT: ; %bb.32: ; %bb11.i.i ; GLOBALNESS0-NEXT: s_add_u32 s8, s38, 40 ; GLOBALNESS0-NEXT: s_addc_u32 s9, s39, 0 ; GLOBALNESS0-NEXT: s_getpc_b64 s[16:17] @@ -601,7 +597,7 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i ; GLOBALNESS0-NEXT: s_mov_b32 s14, s68 ; GLOBALNESS0-NEXT: v_mov_b32_e32 v31, v41 ; GLOBALNESS0-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GLOBALNESS0-NEXT: .LBB1_34: ; %UnifiedUnreachableBlock +; GLOBALNESS0-NEXT: .LBB1_33: ; %UnifiedUnreachableBlock bb: store i32 0, ptr addrspace(1) null, align 4 %tmp4 = load i32, ptr addrspace(1) %arg1.global, align 4 diff --git a/llvm/test/CodeGen/AMDGPU/udiv64.ll b/llvm/test/CodeGen/AMDGPU/udiv64.ll index db7d816386a70..5acbb044c1057 100644 --- a/llvm/test/CodeGen/AMDGPU/udiv64.ll +++ b/llvm/test/CodeGen/AMDGPU/udiv64.ll @@ -313,19 +313,19 @@ define i64 @v_test_udiv_i64(i64 %x, i64 %y) { ; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v2 ; GCN-IR-NEXT: v_add_i32_e64 v4, s[6:7], 32, v4 ; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v3 -; GCN-IR-NEXT: v_min_u32_e32 v10, v4, v5 +; GCN-IR-NEXT: v_min_u32_e32 v14, v4, v5 ; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v0 ; GCN-IR-NEXT: v_add_i32_e64 v4, s[6:7], 32, v4 ; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1 -; GCN-IR-NEXT: v_min_u32_e32 v11, v4, v5 -; GCN-IR-NEXT: v_sub_i32_e64 v6, s[6:7], v10, v11 +; GCN-IR-NEXT: v_min_u32_e32 v15, v4, v5 +; GCN-IR-NEXT: v_sub_i32_e64 v8, s[6:7], v14, v15 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3] ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] -; GCN-IR-NEXT: v_subb_u32_e64 v7, s[6:7], 0, 0, s[6:7] -; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[6:7], 63, v[6:7] +; GCN-IR-NEXT: v_subb_u32_e64 v9, s[6:7], 0, 0, s[6:7] +; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[6:7], 63, v[8:9] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] -; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[6:7] +; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[8:9] ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v1, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v0, 0, s[4:5] @@ -333,23 +333,23 @@ define i64 @v_test_udiv_i64(i64 %x, i64 %y) { ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_cbranch_execz .LBB1_6 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 -; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v6 -; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v7, vcc -; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v6 -; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] -; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4 +; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v8 +; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v9, vcc +; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v8 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 +; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11] +; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_cbranch_execz .LBB1_5 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v2 -; GCN-IR-NEXT: v_lshr_b64 v[8:9], v[0:1], v8 +; GCN-IR-NEXT: v_lshr_b64 v[8:9], v[0:1], v10 ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v3, vcc -; GCN-IR-NEXT: v_not_b32_e32 v0, v10 +; GCN-IR-NEXT: v_not_b32_e32 v0, v14 ; GCN-IR-NEXT: v_not_b32_e32 v1, 0 -; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v11 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v15 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 @@ -1067,11 +1067,11 @@ define i64 @v_test_udiv_pow2_k_num_i64(i64 %x) { ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 ; GCN-IR-NEXT: v_min_u32_e32 v10, v2, v3 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 0xffffffd0, v10 -; GCN-IR-NEXT: v_addc_u32_e64 v5, s[6:7], 0, -1, vcc +; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 0xffffffd0, v10 +; GCN-IR-NEXT: v_addc_u32_e64 v7, s[6:7], 0, -1, vcc ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[4:5] -; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[6:7], 63, v[4:5] +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[6:7] +; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[6:7], 63, v[6:7] ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0x8000 ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[4:5] @@ -1081,13 +1081,13 @@ define i64 @v_test_udiv_pow2_k_num_i64(i64 %x) { ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_cbranch_execz .LBB9_6 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 -; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v4 -; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4 -; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc +; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v6 +; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v6 +; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v7, vcc ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000 -; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7] -; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[4:5], v2 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 +; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] +; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[4:5], v2 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[8:9], vcc ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[8:9] @@ -1095,7 +1095,7 @@ define i64 @v_test_udiv_pow2_k_num_i64(i64 %x) { ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0 ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc -; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[4:5], v6 +; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[4:5], v8 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 47, v10 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_subb_u32_e64 v7, s[4:5], 0, 0, vcc @@ -1156,13 +1156,13 @@ define i64 @v_test_udiv_pow2_k_den_i64(i64 %x) { ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0 ; GCN-IR-NEXT: v_add_i32_e64 v2, s[4:5], 32, v2 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 -; GCN-IR-NEXT: v_min_u32_e32 v8, v2, v3 -; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 48, v8 -; GCN-IR-NEXT: v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5] +; GCN-IR-NEXT: v_min_u32_e32 v10, v2, v3 +; GCN-IR-NEXT: v_sub_i32_e64 v6, s[4:5], 48, v10 +; GCN-IR-NEXT: v_subb_u32_e64 v7, s[4:5], 0, 0, s[4:5] ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] -; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5] +; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[6:7] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] -; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] +; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[6:7] ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v1, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5] @@ -1170,19 +1170,19 @@ define i64 @v_test_udiv_pow2_k_den_i64(i64 %x) { ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_cbranch_execz .LBB10_6 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 -; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v4 -; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc -; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4 -; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7] -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 +; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v6 +; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v7, vcc +; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v6 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 +; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] +; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_cbranch_execz .LBB10_5 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader -; GCN-IR-NEXT: v_lshr_b64 v[6:7], v[0:1], v6 -; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffcf, v8 +; GCN-IR-NEXT: v_lshr_b64 v[6:7], v[0:1], v8 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffcf, v10 ; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: v_addc_u32_e64 v1, s[4:5], 0, -1, vcc ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 @@ -1356,13 +1356,13 @@ define i64 @v_test_udiv_k_den_i64(i64 %x) { ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0 ; GCN-IR-NEXT: v_add_i32_e64 v2, s[4:5], 32, v2 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 -; GCN-IR-NEXT: v_min_u32_e32 v8, v2, v3 -; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 59, v8 -; GCN-IR-NEXT: v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5] +; GCN-IR-NEXT: v_min_u32_e32 v10, v2, v3 +; GCN-IR-NEXT: v_sub_i32_e64 v6, s[4:5], 59, v10 +; GCN-IR-NEXT: v_subb_u32_e64 v7, s[4:5], 0, 0, s[4:5] ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] -; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5] +; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[6:7] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] -; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] +; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[6:7] ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v1, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5] @@ -1370,19 +1370,19 @@ define i64 @v_test_udiv_k_den_i64(i64 %x) { ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_cbranch_execz .LBB12_6 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 -; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v4 -; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc -; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4 -; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7] -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 +; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v6 +; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v7, vcc +; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v6 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 +; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] +; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_cbranch_execz .LBB12_5 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader -; GCN-IR-NEXT: v_lshr_b64 v[6:7], v[0:1], v6 -; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc4, v8 +; GCN-IR-NEXT: v_lshr_b64 v[6:7], v[0:1], v8 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc4, v10 ; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: v_addc_u32_e64 v1, s[4:5], 0, -1, vcc ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 diff --git a/llvm/test/CodeGen/AMDGPU/urem64.ll b/llvm/test/CodeGen/AMDGPU/urem64.ll index a794d139063d5..94f1b83ea2765 100644 --- a/llvm/test/CodeGen/AMDGPU/urem64.ll +++ b/llvm/test/CodeGen/AMDGPU/urem64.ll @@ -345,9 +345,9 @@ define i64 @v_test_urem_i64(i64 %x, i64 %y) { ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v4 +; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4 -; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] @@ -1186,9 +1186,9 @@ define i64 @v_test_urem_pow2_k_num_i64(i64 %x) { ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000 +; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7] ; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[4:5], v2 -; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[8:9], vcc ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[8:9] @@ -1280,9 +1280,9 @@ define i64 @v_test_urem_pow2_k_den_i64(i64 %x) { ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v2 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2 +; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7] ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 -; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll b/llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll index ec0933c30e576..b0b5850084697 100644 --- a/llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll +++ b/llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll @@ -17,8 +17,8 @@ define amdgpu_ps float @else1(i32 %z, float %v) #0 { ; SI-NEXT: bb.1.Flow: ; SI-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000) ; SI-NEXT: {{ $}} - ; SI-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI undef %13:vgpr_32, %bb.0, %4, %bb.3 - ; SI-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, undef %15:vgpr_32, %bb.3 + ; SI-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI undef %9:vgpr_32, %bb.0, %4, %bb.3 + ; SI-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, undef %14:vgpr_32, %bb.3 ; SI-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_32 = SI_ELSE killed [[SI_IF]], %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec ; SI-NEXT: S_BRANCH %bb.2 ; SI-NEXT: {{ $}} @@ -73,8 +73,8 @@ define amdgpu_ps float @else2(i32 %z, float %v) #0 { ; SI-NEXT: bb.1.Flow: ; SI-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000) ; SI-NEXT: {{ $}} - ; SI-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI undef %16:vgpr_32, %bb.0, %5, %bb.3 - ; SI-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI undef %16:vgpr_32, %bb.0, [[COPY]], %bb.3 + ; SI-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI undef %11:vgpr_32, %bb.0, %5, %bb.3 + ; SI-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI undef %11:vgpr_32, %bb.0, [[COPY]], %bb.3 ; SI-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_32 = SI_ELSE killed [[SI_IF]], %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec ; SI-NEXT: S_BRANCH %bb.2 ; SI-NEXT: {{ $}} @@ -141,9 +141,9 @@ define amdgpu_ps float @else3(i32 %z, float %v, i32 inreg %bound, i32 %x0) #0 { ; SI-NEXT: bb.2.Flow: ; SI-NEXT: successors: %bb.3(0x40000000), %bb.5(0x40000000) ; SI-NEXT: {{ $}} - ; SI-NEXT: [[PHI2:%[0-9]+]]:vgpr_32 = PHI undef %31:vgpr_32, %bb.1, %10, %bb.4 - ; SI-NEXT: [[PHI3:%[0-9]+]]:vgpr_32 = PHI undef %32:vgpr_32, %bb.1, %9, %bb.4 - ; SI-NEXT: [[PHI4:%[0-9]+]]:vgpr_32 = PHI [[PHI1]], %bb.1, undef %34:vgpr_32, %bb.4 + ; SI-NEXT: [[PHI2:%[0-9]+]]:vgpr_32 = PHI undef %25:vgpr_32, %bb.1, %10, %bb.4 + ; SI-NEXT: [[PHI3:%[0-9]+]]:vgpr_32 = PHI undef %26:vgpr_32, %bb.1, %9, %bb.4 + ; SI-NEXT: [[PHI4:%[0-9]+]]:vgpr_32 = PHI [[PHI1]], %bb.1, undef %32:vgpr_32, %bb.4 ; SI-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_32 = SI_ELSE killed [[SI_IF]], %bb.5, implicit-def dead $exec, implicit-def dead $scc, implicit $exec ; SI-NEXT: S_BRANCH %bb.3 ; SI-NEXT: {{ $}} @@ -233,10 +233,10 @@ define amdgpu_ps float @loop(i32 %z, float %v, i32 inreg %bound, ptr %extern_fun ; SI-NEXT: bb.1.Flow: ; SI-NEXT: successors: %bb.2(0x40000000), %bb.10(0x40000000) ; SI-NEXT: {{ $}} - ; SI-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI undef %47:vgpr_32, %bb.0, %4, %bb.9 - ; SI-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY4]], %bb.0, undef %49:vgpr_32, %bb.9 - ; SI-NEXT: [[PHI2:%[0-9]+]]:vgpr_32 = PHI [[COPY3]], %bb.0, undef %51:vgpr_32, %bb.9 - ; SI-NEXT: [[PHI3:%[0-9]+]]:vgpr_32 = PHI [[COPY2]], %bb.0, undef %53:vgpr_32, %bb.9 + ; SI-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI undef %16:vgpr_32, %bb.0, %4, %bb.9 + ; SI-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY4]], %bb.0, undef %48:vgpr_32, %bb.9 + ; SI-NEXT: [[PHI2:%[0-9]+]]:vgpr_32 = PHI [[COPY3]], %bb.0, undef %50:vgpr_32, %bb.9 + ; SI-NEXT: [[PHI3:%[0-9]+]]:vgpr_32 = PHI [[COPY2]], %bb.0, undef %52:vgpr_32, %bb.9 ; SI-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_32 = SI_ELSE killed [[SI_IF]], %bb.10, implicit-def dead $exec, implicit-def dead $scc, implicit $exec ; SI-NEXT: S_BRANCH %bb.2 ; SI-NEXT: {{ $}} @@ -250,8 +250,8 @@ define amdgpu_ps float @loop(i32 %z, float %v, i32 inreg %bound, ptr %extern_fun ; SI-NEXT: bb.3: ; SI-NEXT: successors: %bb.4(0x80000000) ; SI-NEXT: {{ $}} - ; SI-NEXT: [[PHI4:%[0-9]+]]:vreg_64 = PHI undef %55:vreg_64, %bb.4, [[REG_SEQUENCE]], %bb.2 - ; SI-NEXT: [[PHI5:%[0-9]+]]:vgpr_32 = PHI undef %57:vgpr_32, %bb.4, [[PHI1]], %bb.2 + ; SI-NEXT: [[PHI4:%[0-9]+]]:vreg_64 = PHI undef %54:vreg_64, %bb.4, [[REG_SEQUENCE]], %bb.2 + ; SI-NEXT: [[PHI5:%[0-9]+]]:vgpr_32 = PHI undef %56:vgpr_32, %bb.4, [[PHI1]], %bb.2 ; SI-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[PHI4]].sub0, implicit $exec ; SI-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[PHI4]].sub1, implicit $exec ; SI-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_64 = REG_SEQUENCE killed [[V_READFIRSTLANE_B32_]], %subreg.sub0, killed [[V_READFIRSTLANE_B32_1]], %subreg.sub1 @@ -287,8 +287,8 @@ define amdgpu_ps float @loop(i32 %z, float %v, i32 inreg %bound, ptr %extern_fun ; SI-NEXT: bb.7: ; SI-NEXT: successors: %bb.8(0x80000000) ; SI-NEXT: {{ $}} - ; SI-NEXT: [[PHI6:%[0-9]+]]:vreg_64 = PHI undef %59:vreg_64, %bb.8, [[REG_SEQUENCE2]], %bb.6 - ; SI-NEXT: [[PHI7:%[0-9]+]]:vgpr_32 = PHI undef %61:vgpr_32, %bb.8, [[COPY4]], %bb.6 + ; SI-NEXT: [[PHI6:%[0-9]+]]:vreg_64 = PHI undef %58:vreg_64, %bb.8, [[REG_SEQUENCE2]], %bb.6 + ; SI-NEXT: [[PHI7:%[0-9]+]]:vgpr_32 = PHI undef %60:vgpr_32, %bb.8, [[COPY4]], %bb.6 ; SI-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[PHI6]].sub0, implicit $exec ; SI-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[PHI6]].sub1, implicit $exec ; SI-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_64 = REG_SEQUENCE killed [[V_READFIRSTLANE_B32_2]], %subreg.sub0, killed [[V_READFIRSTLANE_B32_3]], %subreg.sub1 @@ -356,9 +356,9 @@ define amdgpu_ps float @loop_with_use(i32 %z, float %v, i32 inreg %bound, ptr %e ; SI-NEXT: bb.1.Flow: ; SI-NEXT: successors: %bb.2(0x40000000), %bb.10(0x40000000) ; SI-NEXT: {{ $}} - ; SI-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI undef %48:vgpr_32, %bb.0, %4, %bb.9 - ; SI-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY3]], %bb.0, undef %50:vgpr_32, %bb.9 - ; SI-NEXT: [[PHI2:%[0-9]+]]:vgpr_32 = PHI [[COPY2]], %bb.0, undef %52:vgpr_32, %bb.9 + ; SI-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI undef %16:vgpr_32, %bb.0, %4, %bb.9 + ; SI-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY3]], %bb.0, undef %49:vgpr_32, %bb.9 + ; SI-NEXT: [[PHI2:%[0-9]+]]:vgpr_32 = PHI [[COPY2]], %bb.0, undef %51:vgpr_32, %bb.9 ; SI-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_32 = SI_ELSE killed [[SI_IF]], %bb.10, implicit-def dead $exec, implicit-def dead $scc, implicit $exec ; SI-NEXT: S_BRANCH %bb.2 ; SI-NEXT: {{ $}} @@ -372,7 +372,7 @@ define amdgpu_ps float @loop_with_use(i32 %z, float %v, i32 inreg %bound, ptr %e ; SI-NEXT: bb.3: ; SI-NEXT: successors: %bb.4(0x80000000) ; SI-NEXT: {{ $}} - ; SI-NEXT: [[PHI3:%[0-9]+]]:vreg_64 = PHI undef %54:vreg_64, %bb.4, [[REG_SEQUENCE]], %bb.2 + ; SI-NEXT: [[PHI3:%[0-9]+]]:vreg_64 = PHI undef %53:vreg_64, %bb.4, [[REG_SEQUENCE]], %bb.2 ; SI-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[PHI3]].sub0, implicit $exec ; SI-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[PHI3]].sub1, implicit $exec ; SI-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_64 = REG_SEQUENCE killed [[V_READFIRSTLANE_B32_]], %subreg.sub0, killed [[V_READFIRSTLANE_B32_1]], %subreg.sub1 @@ -408,7 +408,7 @@ define amdgpu_ps float @loop_with_use(i32 %z, float %v, i32 inreg %bound, ptr %e ; SI-NEXT: bb.7: ; SI-NEXT: successors: %bb.8(0x80000000) ; SI-NEXT: {{ $}} - ; SI-NEXT: [[PHI4:%[0-9]+]]:vreg_64 = PHI undef %56:vreg_64, %bb.8, [[REG_SEQUENCE2]], %bb.6 + ; SI-NEXT: [[PHI4:%[0-9]+]]:vreg_64 = PHI undef %55:vreg_64, %bb.8, [[REG_SEQUENCE2]], %bb.6 ; SI-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[PHI4]].sub0, implicit $exec ; SI-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[PHI4]].sub1, implicit $exec ; SI-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_64 = REG_SEQUENCE killed [[V_READFIRSTLANE_B32_2]], %subreg.sub0, killed [[V_READFIRSTLANE_B32_3]], %subreg.sub1 diff --git a/llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll b/llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll index 0d19f4fca8880..ee6a63fc1f7e1 100644 --- a/llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll +++ b/llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll @@ -464,21 +464,19 @@ define amdgpu_kernel void @v8i8_phi_zeroinit(ptr addrspace(1) %src1, ptr addrspa ; GFX906-NEXT: v_lshlrev_b32_e32 v5, 3, v0 ; GFX906-NEXT: v_cmp_lt_u32_e64 s[0:1], 14, v0 ; GFX906-NEXT: v_cmp_gt_u32_e32 vcc, 15, v0 -; GFX906-NEXT: ; implicit-def: $vgpr1_vgpr2 +; GFX906-NEXT: ; implicit-def: $vgpr3_vgpr4 ; GFX906-NEXT: s_waitcnt lgkmcnt(0) -; GFX906-NEXT: global_load_dwordx2 v[3:4], v5, s[8:9] +; GFX906-NEXT: global_load_dwordx2 v[1:2], v5, s[8:9] ; GFX906-NEXT: s_and_saveexec_b64 s[2:3], vcc ; GFX906-NEXT: s_cbranch_execz .LBB9_2 ; GFX906-NEXT: ; %bb.1: ; %bb.1 -; GFX906-NEXT: global_load_dwordx2 v[1:2], v5, s[10:11] -; GFX906-NEXT: s_mov_b32 s4, 0 +; GFX906-NEXT: global_load_dwordx2 v[3:4], v5, s[10:11] ; GFX906-NEXT: v_cmp_gt_u32_e32 vcc, 7, v0 -; GFX906-NEXT: s_mov_b32 s5, s4 ; GFX906-NEXT: s_waitcnt vmcnt(1) -; GFX906-NEXT: v_mov_b32_e32 v3, s4 -; GFX906-NEXT: v_mov_b32_e32 v4, s5 +; GFX906-NEXT: v_mov_b32_e32 v1, 0 ; GFX906-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; GFX906-NEXT: s_and_b64 s[4:5], vcc, exec +; GFX906-NEXT: v_mov_b32_e32 v2, v1 ; GFX906-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5] ; GFX906-NEXT: .LBB9_2: ; %Flow ; GFX906-NEXT: s_or_b64 exec, exec, s[2:3] @@ -486,15 +484,15 @@ define amdgpu_kernel void @v8i8_phi_zeroinit(ptr addrspace(1) %src1, ptr addrspa ; GFX906-NEXT: s_cbranch_execz .LBB9_4 ; GFX906-NEXT: ; %bb.3: ; %bb.2 ; GFX906-NEXT: s_waitcnt vmcnt(0) -; GFX906-NEXT: v_mov_b32_e32 v1, v3 +; GFX906-NEXT: v_mov_b32_e32 v4, v2 ; GFX906-NEXT: v_mov_b32_e32 v0, 0 -; GFX906-NEXT: v_mov_b32_e32 v2, v4 -; GFX906-NEXT: global_store_dwordx2 v0, v[3:4], s[12:13] +; GFX906-NEXT: v_mov_b32_e32 v3, v1 +; GFX906-NEXT: global_store_dwordx2 v0, v[1:2], s[12:13] ; GFX906-NEXT: .LBB9_4: ; %bb.3 ; GFX906-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX906-NEXT: v_mov_b32_e32 v0, 0 ; GFX906-NEXT: s_waitcnt vmcnt(0) -; GFX906-NEXT: global_store_dwordx2 v0, v[1:2], s[14:15] +; GFX906-NEXT: global_store_dwordx2 v0, v[3:4], s[14:15] ; GFX906-NEXT: s_endpgm entry: %idx = call i32 @llvm.amdgcn.workitem.id.x() @@ -549,14 +547,14 @@ define amdgpu_kernel void @v8i8_phi_const(ptr addrspace(1) %src1, ptr addrspace( ; GFX906-NEXT: v_cmp_gt_u32_e32 vcc, 7, v0 ; GFX906-NEXT: s_andn2_b64 s[0:1], s[0:1], exec ; GFX906-NEXT: s_and_b64 s[4:5], vcc, exec -; GFX906-NEXT: v_mov_b32_e32 v1, 1 -; GFX906-NEXT: v_mov_b32_e32 v10, 2 -; GFX906-NEXT: v_mov_b32_e32 v9, 3 -; GFX906-NEXT: v_mov_b32_e32 v8, 4 -; GFX906-NEXT: v_mov_b32_e32 v2, 5 -; GFX906-NEXT: v_mov_b32_e32 v7, 6 -; GFX906-NEXT: v_mov_b32_e32 v6, 7 ; GFX906-NEXT: v_mov_b32_e32 v5, 8 +; GFX906-NEXT: v_mov_b32_e32 v6, 7 +; GFX906-NEXT: v_mov_b32_e32 v7, 6 +; GFX906-NEXT: v_mov_b32_e32 v2, 5 +; GFX906-NEXT: v_mov_b32_e32 v8, 4 +; GFX906-NEXT: v_mov_b32_e32 v9, 3 +; GFX906-NEXT: v_mov_b32_e32 v10, 2 +; GFX906-NEXT: v_mov_b32_e32 v1, 1 ; GFX906-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5] ; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: v_lshrrev_b32_e32 v16, 24, v4