From 335b337f366875ebe112b4442c099f18c1f29132 Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Tue, 5 Dec 2023 22:17:16 -0800 Subject: [PATCH 01/10] base impl --- llvm/lib/Target/X86/X86InstrMisc.td | 22 ++++++++++++++++++-- llvm/utils/TableGen/X86RecognizableInstr.cpp | 8 +++++-- 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td index 82c079fe2ea82..f3897c1119c8b 100644 --- a/llvm/lib/Target/X86/X86InstrMisc.td +++ b/llvm/lib/Target/X86/X86InstrMisc.td @@ -1497,11 +1497,21 @@ let SchedRW = [WriteStore] in { def MOVDIRI32 : I<0xF9, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), "movdiri\t{$src, $dst|$dst, $src}", [(int_x86_directstore32 addr:$dst, GR32:$src)]>, - T8PS, Requires<[HasMOVDIRI]>; + T8PS, Requires<[HasMOVDIRI, NoEGPR]>; def MOVDIRI64 : RI<0xF9, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), "movdiri\t{$src, $dst|$dst, $src}", [(int_x86_directstore64 addr:$dst, GR64:$src)]>, - T8PS, Requires<[In64BitMode, HasMOVDIRI]>; + T8PS, Requires<[In64BitMode, HasMOVDIRI, NoEGPR]>; +let CD8_Scale = 0 in { +def MOVDIRI32_EVEX : I<0xF9, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + "movdiri\t{$src, $dst|$dst, $src}", + [(int_x86_directstore32 addr:$dst, GR32:$src)]>, + EVEX, T_MAP4PS, Requires<[HasMOVDIRI, HasEGPR]>; +def MOVDIRI64_EVEX : RI<0xF9, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + "movdiri\t{$src, $dst|$dst, $src}", + [(int_x86_directstore64 addr:$dst, GR64:$src)]>, + EVEX, T_MAP4PS, Requires<[In64BitMode, HasMOVDIRI, HasEGPR]>; +} } // SchedRW //===----------------------------------------------------------------------===// @@ -1519,6 +1529,14 @@ def MOVDIR64B64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src), "movdir64b\t{$src, $dst|$dst, $src}", [(int_x86_movdir64b GR64:$dst, addr:$src)]>, T8PD, AdSize64, Requires<[HasMOVDIR64B, In64BitMode]>; +def MOVDIR64B32_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src), + "movdir64b\t{$src, $dst|$dst, $src}", + [(int_x86_movdir64b GR32:$dst, addr:$src)]>, + EVEX_NoCD8, T_MAP4PD, AdSize32, Requires<[HasMOVDIR64B, NoEGPR]>; +def MOVDIR64B64_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src), + "movdir64b\t{$src, $dst|$dst, $src}", + [(int_x86_movdir64b GR64:$dst, addr:$src)]>, + EVEX_NoCD8, T_MAP4PD, AdSize64, Requires<[HasMOVDIR64B, HasEGPR, In64BitMode]>; } // SchedRW //===----------------------------------------------------------------------===// diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp index 6e03fc11d6d9d..8cdf4aa01f721 100644 --- a/llvm/utils/TableGen/X86RecognizableInstr.cpp +++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp @@ -265,8 +265,12 @@ InstructionContext RecognizableInstr::insnContext() const { } } // No L, no W - else if (OpPrefix == X86Local::PD) - insnContext = EVEX_KB(IC_EVEX_OPSIZE); + else if (OpPrefix == X86Local::PD) { + if(AdSize == X86Local::AdSize32) + insnContext = IC_64BIT_OPSIZE_ADSIZE; + else + insnContext = EVEX_KB(IC_EVEX_OPSIZE); + } else if (OpPrefix == X86Local::XD) insnContext = EVEX_KB(IC_EVEX_XD); else if (OpPrefix == X86Local::XS) From 99d5246586db7ae3ea62dda7b28046c38a171543 Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Thu, 7 Dec 2023 04:11:53 -0800 Subject: [PATCH 02/10] [X86][MC] Support Enc/Dec for EGPR for promoted MOVDIR instruction --- .../llvm/Support/X86DisassemblerDecoderCommon.h | 2 ++ llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp | 2 ++ llvm/lib/Target/X86/X86InstrMisc.td | 6 +++--- llvm/test/MC/Disassembler/X86/apx/movdir64b.txt | 10 ++++++++++ llvm/test/MC/Disassembler/X86/apx/movdiri.txt | 10 ++++++++++ llvm/test/MC/X86/apx/movdir64b-att.s | 12 ++++++++++++ llvm/test/MC/X86/apx/movdir64b-intel.s | 9 +++++++++ llvm/test/MC/X86/apx/movdiri-att.s | 12 ++++++++++++ llvm/test/MC/X86/apx/movdiri-intel.s | 9 +++++++++ llvm/utils/TableGen/X86DisassemblerTables.cpp | 10 +++++++--- llvm/utils/TableGen/X86RecognizableInstr.cpp | 2 +- 11 files changed, 77 insertions(+), 7 deletions(-) create mode 100644 llvm/test/MC/Disassembler/X86/apx/movdir64b.txt create mode 100644 llvm/test/MC/Disassembler/X86/apx/movdiri.txt create mode 100644 llvm/test/MC/X86/apx/movdir64b-att.s create mode 100644 llvm/test/MC/X86/apx/movdir64b-intel.s create mode 100644 llvm/test/MC/X86/apx/movdiri-att.s create mode 100644 llvm/test/MC/X86/apx/movdiri-intel.s diff --git a/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h b/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h index b3d8580e5e56f..58f93199040d6 100644 --- a/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h +++ b/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h @@ -140,6 +140,8 @@ enum attributeBits { ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \ ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \ ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \ + ENUM_ENTRY(IC_EVEX_OPSIZE_ADSIZE, 3, \ + "requires EVEX and the OPSIZE prefix and the ADSIZE prefix") \ ENUM_ENTRY(IC_EVEX_W, 3, "requires EVEX and the W prefix") \ ENUM_ENTRY(IC_EVEX_W_XS, 4, "requires EVEX, W, and XS prefix") \ ENUM_ENTRY(IC_EVEX_W_XD, 4, "requires EVEX, W, and XD prefix") \ diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp index d50e6514b86d8..b97b1402bd005 100644 --- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -1175,6 +1175,8 @@ static int getInstructionID(struct InternalInstruction *insn, attrMask |= ATTR_VEXL; if (l2FromEVEX4of4(insn->vectorExtensionPrefix[3])) attrMask |= ATTR_EVEXL2; + if (insn->hasAdSize) + attrMask |= ATTR_ADSIZE; } else if (insn->vectorExtensionType == TYPE_VEX_3B) { switch (ppFromVEX3of3(insn->vectorExtensionPrefix[2])) { case VEX_PREFIX_66: diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td index f3897c1119c8b..7b78aa26d1689 100644 --- a/llvm/lib/Target/X86/X86InstrMisc.td +++ b/llvm/lib/Target/X86/X86InstrMisc.td @@ -1524,15 +1524,15 @@ def MOVDIR64B16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem_GR16:$src), def MOVDIR64B32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src), "movdir64b\t{$src, $dst|$dst, $src}", [(int_x86_movdir64b GR32:$dst, addr:$src)]>, - T8PD, AdSize32, Requires<[HasMOVDIR64B]>; + T8PD, AdSize32, Requires<[HasMOVDIR64B, NoEGPR]>; def MOVDIR64B64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src), "movdir64b\t{$src, $dst|$dst, $src}", [(int_x86_movdir64b GR64:$dst, addr:$src)]>, - T8PD, AdSize64, Requires<[HasMOVDIR64B, In64BitMode]>; + T8PD, AdSize64, Requires<[HasMOVDIR64B, NoEGPR, In64BitMode]>; def MOVDIR64B32_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src), "movdir64b\t{$src, $dst|$dst, $src}", [(int_x86_movdir64b GR32:$dst, addr:$src)]>, - EVEX_NoCD8, T_MAP4PD, AdSize32, Requires<[HasMOVDIR64B, NoEGPR]>; + EVEX_NoCD8, T_MAP4PD, AdSize32, Requires<[HasMOVDIR64B, HasEGPR, In64BitMode]>; def MOVDIR64B64_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src), "movdir64b\t{$src, $dst|$dst, $src}", [(int_x86_movdir64b GR64:$dst, addr:$src)]>, diff --git a/llvm/test/MC/Disassembler/X86/apx/movdir64b.txt b/llvm/test/MC/Disassembler/X86/apx/movdir64b.txt new file mode 100644 index 0000000000000..81d8f49dbf69d --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/movdir64b.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: movdir64b 291(%r28d,%r29d,4), %r18d +# INTEL: movdir64b r18d, zmmword ptr [r28d + 4*r29d + 291] +0x67,0x62,0x8c,0x79,0x08,0xf8,0x94,0xac,0x23,0x01,0x00,0x00 + +# ATT: movdir64b 291(%r28,%r29,4), %r19 +# INTEL: movdir64b r19, zmmword ptr [r28 + 4*r29 + 291] +0x62,0x8c,0x79,0x08,0xf8,0x9c,0xac,0x23,0x01,0x00,0x00 diff --git a/llvm/test/MC/Disassembler/X86/apx/movdiri.txt b/llvm/test/MC/Disassembler/X86/apx/movdiri.txt new file mode 100644 index 0000000000000..997d016f0d222 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/movdiri.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: movdiri %r18d, 291(%r28,%r29,4) +# INTEL: movdiri dword ptr [r28 + 4*r29 + 291], r18d +0x62,0x8c,0x78,0x08,0xf9,0x94,0xac,0x23,0x01,0x00,0x00 + +# ATT: movdiri %r19, 291(%r28,%r29,4) +# INTEL: movdiri qword ptr [r28 + 4*r29 + 291], r19 +0x62,0x8c,0xf8,0x08,0xf9,0x9c,0xac,0x23,0x01,0x00,0x00 diff --git a/llvm/test/MC/X86/apx/movdir64b-att.s b/llvm/test/MC/X86/apx/movdir64b-att.s new file mode 100644 index 0000000000000..bc8f1a90c9ed6 --- /dev/null +++ b/llvm/test/MC/X86/apx/movdir64b-att.s @@ -0,0 +1,12 @@ +# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s +# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR + +# ERROR-COUNT-2: error: +# ERROR-NOT: error: +# CHECK: movdir64b 291(%r28d,%r29d,4), %r18d +# CHECK: encoding: [0x67,0x62,0x8c,0x79,0x08,0xf8,0x94,0xac,0x23,0x01,0x00,0x00] + movdir64b 291(%r28d,%r29d,4), %r18d + +# CHECK: movdir64b 291(%r28,%r29,4), %r19 +# CHECK: encoding: [0x62,0x8c,0x79,0x08,0xf8,0x9c,0xac,0x23,0x01,0x00,0x00] + movdir64b 291(%r28,%r29,4), %r19 diff --git a/llvm/test/MC/X86/apx/movdir64b-intel.s b/llvm/test/MC/X86/apx/movdir64b-intel.s new file mode 100644 index 0000000000000..b34efefeba2da --- /dev/null +++ b/llvm/test/MC/X86/apx/movdir64b-intel.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +# CHECK: movdir64b r18d, zmmword ptr [r28d + 4*r29d + 291] +# CHECK: encoding: [0x67,0x62,0x8c,0x79,0x08,0xf8,0x94,0xac,0x23,0x01,0x00,0x00] + movdir64b r18d, zmmword ptr [r28d + 4*r29d + 291] + +# CHECK: movdir64b r19, zmmword ptr [r28 + 4*r29 + 291] +# CHECK: encoding: [0x62,0x8c,0x79,0x08,0xf8,0x9c,0xac,0x23,0x01,0x00,0x00] + movdir64b r19, zmmword ptr [r28 + 4*r29 + 291] diff --git a/llvm/test/MC/X86/apx/movdiri-att.s b/llvm/test/MC/X86/apx/movdiri-att.s new file mode 100644 index 0000000000000..8bdabf232f5de --- /dev/null +++ b/llvm/test/MC/X86/apx/movdiri-att.s @@ -0,0 +1,12 @@ +# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s +# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR + +# ERROR-COUNT-2: error: +# ERROR-NOT: error: +# CHECK: movdiri %r18d, 291(%r28,%r29,4) +# CHECK: encoding: [0x62,0x8c,0x78,0x08,0xf9,0x94,0xac,0x23,0x01,0x00,0x00] + movdiri %r18d, 291(%r28,%r29,4) + +# CHECK: movdiri %r19, 291(%r28,%r29,4) +# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf9,0x9c,0xac,0x23,0x01,0x00,0x00] + movdiri %r19, 291(%r28,%r29,4) diff --git a/llvm/test/MC/X86/apx/movdiri-intel.s b/llvm/test/MC/X86/apx/movdiri-intel.s new file mode 100644 index 0000000000000..1a38384f9f96e --- /dev/null +++ b/llvm/test/MC/X86/apx/movdiri-intel.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +# CHECK: movdiri dword ptr [r28 + 4*r29 + 291], r18d +# CHECK: encoding: [0x62,0x8c,0x78,0x08,0xf9,0x94,0xac,0x23,0x01,0x00,0x00] + movdiri dword ptr [r28 + 4*r29 + 291], r18d + +# CHECK: movdiri qword ptr [r28 + 4*r29 + 291], r19 +# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf9,0x9c,0xac,0x23,0x01,0x00,0x00] + movdiri qword ptr [r28 + 4*r29 + 291], r19 diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp index 959e0fda50b81..c3ec2621423fe 100644 --- a/llvm/utils/TableGen/X86DisassemblerTables.cpp +++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp @@ -112,6 +112,7 @@ static inline bool inheritsFrom(InstructionContext child, case IC_64BIT_ADSIZE: return (noPrefix && inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE, noPrefix)); case IC_64BIT_OPSIZE_ADSIZE: + case IC_EVEX_OPSIZE_ADSIZE: return false; case IC_XD: return inheritsFrom(child, IC_64BIT_XD); @@ -885,7 +886,10 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const { for (unsigned index = 0; index < ATTR_max; ++index) { o.indent(i * 2); - if ((index & ATTR_EVEX) || (index & ATTR_VEX) || (index & ATTR_VEXL)) { + if ((index & ATTR_EVEX) && (index & ATTR_64BIT) && + (index & ATTR_OPSIZE) && (index & ATTR_ADSIZE)) + o << "IC_EVEX_OPSIZE_ADSIZE"; + else if ((index & ATTR_EVEX) || (index & ATTR_VEX) || (index & ATTR_VEXL)) { if (index & ATTR_EVEX) o << "IC_EVEX"; else @@ -905,8 +909,8 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const { o << "_XD"; else if (index & ATTR_XS) o << "_XS"; - - if ((index & ATTR_EVEX)) { + + if (index & ATTR_EVEX) { if (index & ATTR_EVEXKZ) o << "_KZ"; else if (index & ATTR_EVEXK) diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp index 8cdf4aa01f721..06f2c63f4cd58 100644 --- a/llvm/utils/TableGen/X86RecognizableInstr.cpp +++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp @@ -267,7 +267,7 @@ InstructionContext RecognizableInstr::insnContext() const { // No L, no W else if (OpPrefix == X86Local::PD) { if(AdSize == X86Local::AdSize32) - insnContext = IC_64BIT_OPSIZE_ADSIZE; + insnContext = IC_EVEX_OPSIZE_ADSIZE; else insnContext = EVEX_KB(IC_EVEX_OPSIZE); } From 638773baba846eb868c66e3178f8580a712fabf6 Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Thu, 7 Dec 2023 04:15:56 -0800 Subject: [PATCH 03/10] Use EVEX_NoCD8 --- llvm/lib/Target/X86/X86InstrMisc.td | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td index 7b78aa26d1689..bfef2aae794f3 100644 --- a/llvm/lib/Target/X86/X86InstrMisc.td +++ b/llvm/lib/Target/X86/X86InstrMisc.td @@ -1502,16 +1502,14 @@ def MOVDIRI64 : RI<0xF9, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), "movdiri\t{$src, $dst|$dst, $src}", [(int_x86_directstore64 addr:$dst, GR64:$src)]>, T8PS, Requires<[In64BitMode, HasMOVDIRI, NoEGPR]>; -let CD8_Scale = 0 in { def MOVDIRI32_EVEX : I<0xF9, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), "movdiri\t{$src, $dst|$dst, $src}", [(int_x86_directstore32 addr:$dst, GR32:$src)]>, - EVEX, T_MAP4PS, Requires<[HasMOVDIRI, HasEGPR]>; + EVEX_NoCD8, T_MAP4PS, Requires<[HasMOVDIRI, HasEGPR]>; def MOVDIRI64_EVEX : RI<0xF9, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), "movdiri\t{$src, $dst|$dst, $src}", [(int_x86_directstore64 addr:$dst, GR64:$src)]>, - EVEX, T_MAP4PS, Requires<[In64BitMode, HasMOVDIRI, HasEGPR]>; -} + EVEX_NoCD8, T_MAP4PS, Requires<[In64BitMode, HasMOVDIRI, HasEGPR]>; } // SchedRW //===----------------------------------------------------------------------===// From dd2b3029133b1c861a240630fcea30b9c3262baa Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Thu, 7 Dec 2023 04:16:45 -0800 Subject: [PATCH 04/10] Fix --- llvm/lib/Target/X86/X86InstrMisc.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td index bfef2aae794f3..2ea10e317e12b 100644 --- a/llvm/lib/Target/X86/X86InstrMisc.td +++ b/llvm/lib/Target/X86/X86InstrMisc.td @@ -1505,7 +1505,7 @@ def MOVDIRI64 : RI<0xF9, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), def MOVDIRI32_EVEX : I<0xF9, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), "movdiri\t{$src, $dst|$dst, $src}", [(int_x86_directstore32 addr:$dst, GR32:$src)]>, - EVEX_NoCD8, T_MAP4PS, Requires<[HasMOVDIRI, HasEGPR]>; + EVEX_NoCD8, T_MAP4PS, Requires<[In64BitMode, HasMOVDIRI, HasEGPR]>; def MOVDIRI64_EVEX : RI<0xF9, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), "movdiri\t{$src, $dst|$dst, $src}", [(int_x86_directstore64 addr:$dst, GR64:$src)]>, From 855af269602c266cdb5688bec5615e28e7d47b13 Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Thu, 7 Dec 2023 04:17:47 -0800 Subject: [PATCH 05/10] remove redundant tab --- llvm/utils/TableGen/X86DisassemblerTables.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp index c3ec2621423fe..87f0ffb82b7db 100644 --- a/llvm/utils/TableGen/X86DisassemblerTables.cpp +++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp @@ -909,7 +909,7 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const { o << "_XD"; else if (index & ATTR_XS) o << "_XS"; - + if (index & ATTR_EVEX) { if (index & ATTR_EVEXKZ) o << "_KZ"; From 3c27968b920adfcd3c7dbaaf9c7c96c7a59f5391 Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Fri, 8 Dec 2023 01:36:44 -0800 Subject: [PATCH 06/10] update comment --- llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h b/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h index 58f93199040d6..b0683ac2e32c0 100644 --- a/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h +++ b/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h @@ -141,7 +141,7 @@ enum attributeBits { ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \ ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \ ENUM_ENTRY(IC_EVEX_OPSIZE_ADSIZE, 3, \ - "requires EVEX and the OPSIZE prefix and the ADSIZE prefix") \ + "requires EVEX, OPSIZE and the ADSIZE prefix") \ ENUM_ENTRY(IC_EVEX_W, 3, "requires EVEX and the W prefix") \ ENUM_ENTRY(IC_EVEX_W_XS, 4, "requires EVEX, W, and XS prefix") \ ENUM_ENTRY(IC_EVEX_W_XD, 4, "requires EVEX, W, and XD prefix") \ From 6304ca0b1a50beccbc63293b6aafdd6e1ce0b422 Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Fri, 8 Dec 2023 01:43:55 -0800 Subject: [PATCH 07/10] resolve comments --- llvm/utils/TableGen/X86DisassemblerTables.cpp | 3 ++- llvm/utils/TableGen/X86RecognizableInstr.cpp | 5 ++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp index 87f0ffb82b7db..03963ebcbce1c 100644 --- a/llvm/utils/TableGen/X86DisassemblerTables.cpp +++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp @@ -112,7 +112,6 @@ static inline bool inheritsFrom(InstructionContext child, case IC_64BIT_ADSIZE: return (noPrefix && inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE, noPrefix)); case IC_64BIT_OPSIZE_ADSIZE: - case IC_EVEX_OPSIZE_ADSIZE: return false; case IC_XD: return inheritsFrom(child, IC_64BIT_XD); @@ -214,6 +213,8 @@ static inline bool inheritsFrom(InstructionContext child, (WIG && inheritsFrom(child, IC_EVEX_W_OPSIZE)) || (VEX_LIG && inheritsFrom(child, IC_EVEX_L_OPSIZE)) || (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE)); + case IC_EVEX_OPSIZE_ADSIZE: + return false; case IC_EVEX_K: return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_K)) || (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_K)) || diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp index 06f2c63f4cd58..47ee9544f3233 100644 --- a/llvm/utils/TableGen/X86RecognizableInstr.cpp +++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp @@ -266,12 +266,11 @@ InstructionContext RecognizableInstr::insnContext() const { } // No L, no W else if (OpPrefix == X86Local::PD) { - if(AdSize == X86Local::AdSize32) + if (AdSize == X86Local::AdSize32) insnContext = IC_EVEX_OPSIZE_ADSIZE; else insnContext = EVEX_KB(IC_EVEX_OPSIZE); - } - else if (OpPrefix == X86Local::XD) + } else if (OpPrefix == X86Local::XD) insnContext = EVEX_KB(IC_EVEX_XD); else if (OpPrefix == X86Local::XS) insnContext = EVEX_KB(IC_EVEX_XS); From db9c6c0995ef3998761b8a21ff68f57d10099cfa Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Fri, 8 Dec 2023 02:14:50 -0800 Subject: [PATCH 08/10] clang format --- llvm/utils/TableGen/X86DisassemblerTables.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp index 03963ebcbce1c..cbd2a57412758 100644 --- a/llvm/utils/TableGen/X86DisassemblerTables.cpp +++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp @@ -887,8 +887,8 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const { for (unsigned index = 0; index < ATTR_max; ++index) { o.indent(i * 2); - if ((index & ATTR_EVEX) && (index & ATTR_64BIT) && - (index & ATTR_OPSIZE) && (index & ATTR_ADSIZE)) + if ((index & ATTR_EVEX) && (index & ATTR_64BIT) && (index & ATTR_OPSIZE) && + (index & ATTR_ADSIZE)) o << "IC_EVEX_OPSIZE_ADSIZE"; else if ((index & ATTR_EVEX) || (index & ATTR_VEX) || (index & ATTR_VEXL)) { if (index & ATTR_EVEX) From af9a423b307e5620619419d0e914f58eb8855956 Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Tue, 12 Dec 2023 19:22:41 -0800 Subject: [PATCH 09/10] Mov ADSIZE special for evex movdir64b --- llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp index b97b1402bd005..a3b9c6e706b51 100644 --- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -1175,8 +1175,6 @@ static int getInstructionID(struct InternalInstruction *insn, attrMask |= ATTR_VEXL; if (l2FromEVEX4of4(insn->vectorExtensionPrefix[3])) attrMask |= ATTR_EVEXL2; - if (insn->hasAdSize) - attrMask |= ATTR_ADSIZE; } else if (insn->vectorExtensionType == TYPE_VEX_3B) { switch (ppFromVEX3of3(insn->vectorExtensionPrefix[2])) { case VEX_PREFIX_66: @@ -1332,7 +1330,8 @@ static int getInstructionID(struct InternalInstruction *insn, // any position. if ((insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0)) || (insn->opcodeType == TWOBYTE && (insn->opcode == 0xAE)) || - (insn->opcodeType == THREEBYTE_38 && insn->opcode == 0xF8)) { + (insn->opcodeType == THREEBYTE_38 && insn->opcode == 0xF8) || + (insn->vectorExtensionType == TYPE_EVEX && insn->opcode == 0xF8)) { // Make sure we observed the prefixes in any position. if (insn->hasAdSize) attrMask |= ATTR_ADSIZE; From cac38ebfc67e4e34351605309023bf4c8f95af5a Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Thu, 14 Dec 2023 22:56:44 -0800 Subject: [PATCH 10/10] resolve comments --- llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp | 2 +- llvm/utils/TableGen/X86DisassemblerTables.cpp | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp index a3b9c6e706b51..59e2008f56321 100644 --- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -1331,7 +1331,7 @@ static int getInstructionID(struct InternalInstruction *insn, if ((insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0)) || (insn->opcodeType == TWOBYTE && (insn->opcode == 0xAE)) || (insn->opcodeType == THREEBYTE_38 && insn->opcode == 0xF8) || - (insn->vectorExtensionType == TYPE_EVEX && insn->opcode == 0xF8)) { + (insn->opcodeType == MAP4 && insn->opcode == 0xF8)) { // Make sure we observed the prefixes in any position. if (insn->hasAdSize) attrMask |= ATTR_ADSIZE; diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp index cbd2a57412758..06e7ec3b92307 100644 --- a/llvm/utils/TableGen/X86DisassemblerTables.cpp +++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp @@ -887,8 +887,7 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const { for (unsigned index = 0; index < ATTR_max; ++index) { o.indent(i * 2); - if ((index & ATTR_EVEX) && (index & ATTR_64BIT) && (index & ATTR_OPSIZE) && - (index & ATTR_ADSIZE)) + if ((index & ATTR_EVEX) && (index & ATTR_OPSIZE) && (index & ATTR_ADSIZE)) o << "IC_EVEX_OPSIZE_ADSIZE"; else if ((index & ATTR_EVEX) || (index & ATTR_VEX) || (index & ATTR_VEXL)) { if (index & ATTR_EVEX)