From 452f812dedbfb8f417a61b07f88a66785398171c Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Fri, 15 Dec 2023 02:01:12 -0800 Subject: [PATCH 1/5] [X86][MC] Support Enc/Dec for EGPR for promoted SHA instruction --- llvm/lib/Target/X86/X86InstrSSE.td | 95 ++++++++++++++----- .../test/MC/Disassembler/X86/apx/sha1msg1.txt | 10 ++ .../test/MC/Disassembler/X86/apx/sha1msg2.txt | 10 ++ .../MC/Disassembler/X86/apx/sha1nexte.txt | 10 ++ .../MC/Disassembler/X86/apx/sha1rnds4.txt | 10 ++ .../MC/Disassembler/X86/apx/sha256msg1.txt | 10 ++ .../MC/Disassembler/X86/apx/sha256msg2.txt | 10 ++ .../MC/Disassembler/X86/apx/sha256rnds2.txt | 10 ++ llvm/test/MC/X86/apx/sha1msg1-att.s | 9 ++ llvm/test/MC/X86/apx/sha1msg1-intel.s | 10 ++ llvm/test/MC/X86/apx/sha1msg2-att.s | 9 ++ llvm/test/MC/X86/apx/sha1msg2-intel.s | 9 ++ llvm/test/MC/X86/apx/sha1nexte-att.s | 9 ++ llvm/test/MC/X86/apx/sha1nexte-intel.s | 9 ++ llvm/test/MC/X86/apx/sha1rnds4-att.s | 9 ++ llvm/test/MC/X86/apx/sha1rnds4-intel.s | 9 ++ llvm/test/MC/X86/apx/sha256msg1-att.s | 9 ++ llvm/test/MC/X86/apx/sha256msg1-intel.s | 9 ++ llvm/test/MC/X86/apx/sha256msg2-att.s | 9 ++ llvm/test/MC/X86/apx/sha256msg2-intel.s | 9 ++ llvm/test/MC/X86/apx/sha256rnds2-att.s | 9 ++ llvm/test/MC/X86/apx/sha256rnds2-intel.s | 10 ++ llvm/test/TableGen/x86-fold-tables.inc | 7 ++ 23 files changed, 276 insertions(+), 24 deletions(-) create mode 100644 llvm/test/MC/Disassembler/X86/apx/sha1msg1.txt create mode 100644 llvm/test/MC/Disassembler/X86/apx/sha1msg2.txt create mode 100644 llvm/test/MC/Disassembler/X86/apx/sha1nexte.txt create mode 100644 llvm/test/MC/Disassembler/X86/apx/sha1rnds4.txt create mode 100644 llvm/test/MC/Disassembler/X86/apx/sha256msg1.txt create mode 100644 llvm/test/MC/Disassembler/X86/apx/sha256msg2.txt create mode 100644 llvm/test/MC/Disassembler/X86/apx/sha256rnds2.txt create mode 100644 llvm/test/MC/X86/apx/sha1msg1-att.s create mode 100644 llvm/test/MC/X86/apx/sha1msg1-intel.s create mode 100644 llvm/test/MC/X86/apx/sha1msg2-att.s create mode 100644 llvm/test/MC/X86/apx/sha1msg2-intel.s create mode 100644 llvm/test/MC/X86/apx/sha1nexte-att.s create mode 100644 llvm/test/MC/X86/apx/sha1nexte-intel.s create mode 100644 llvm/test/MC/X86/apx/sha1rnds4-att.s create mode 100644 llvm/test/MC/X86/apx/sha1rnds4-intel.s create mode 100644 llvm/test/MC/X86/apx/sha256msg1-att.s create mode 100644 llvm/test/MC/X86/apx/sha256msg1-intel.s create mode 100644 llvm/test/MC/X86/apx/sha256msg2-att.s create mode 100644 llvm/test/MC/X86/apx/sha256msg2-intel.s create mode 100644 llvm/test/MC/X86/apx/sha256rnds2-att.s create mode 100644 llvm/test/MC/X86/apx/sha256rnds2-intel.s diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index cf57fe562ed5c..acf068d38b5de 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -6706,31 +6706,31 @@ let Constraints = "$src1 = $dst" in { // FIXME: Is there a better scheduler class for SHA than WriteVecIMul? multiclass SHAI_binop Opc, string OpcodeStr, Intrinsic IntId, - X86FoldableSchedWrite sched, bit UsesXMM0 = 0> { - def rr : I, - T8PS, Sched<[sched]>; - - def rm : I, T8PS, - Sched<[sched.Folded, sched.ReadAfterFold]>; + X86FoldableSchedWrite sched, string Suffix = "", bit UsesXMM0 = 0> { + def rr#Suffix : I, + T8PS, Sched<[sched]>; + + def rm#Suffix : I, T8PS, + Sched<[sched.Folded, sched.ReadAfterFold]>; } -let Constraints = "$src1 = $dst", Predicates = [HasSHA] in { +let Constraints = "$src1 = $dst", Predicates = [HasSHA, NoEGPR] in { def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, u8imm:$src3), "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}", @@ -6757,7 +6757,7 @@ let Constraints = "$src1 = $dst", Predicates = [HasSHA] in { let Uses=[XMM0] in defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, - SchedWriteVecIMul.XMM, 1>; + SchedWriteVecIMul.XMM, "", 1>; defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1, SchedWriteVecIMul.XMM>; @@ -6765,12 +6765,59 @@ let Constraints = "$src1 = $dst", Predicates = [HasSHA] in { SchedWriteVecIMul.XMM>; } +let Constraints = "$src1 = $dst", Predicates = [HasSHA, HasEGPR, In64BitMode]in { + def SHA1RNDS4rri_EVEX: Ii8<0xD4, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src2, u8imm:$src3), + "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set VR128:$dst, + (int_x86_sha1rnds4 VR128:$src1, VR128:$src2, + (i8 timm:$src3)))]>, + EVEX_NoCD8, T_MAP4PS, Sched<[SchedWriteVecIMul.XMM]>; + def SHA1RNDS4rmi_EVEX: Ii8<0xD4, MRMSrcMem, (outs VR128:$dst), + (ins VR128:$src1, i128mem:$src2, u8imm:$src3), + "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set VR128:$dst, + (int_x86_sha1rnds4 VR128:$src1, + (memop addr:$src2), + (i8 timm:$src3)))]>, + EVEX_NoCD8, T_MAP4PS, + Sched<[SchedWriteVecIMul.XMM.Folded, + SchedWriteVecIMul.XMM.ReadAfterFold]>; + + defm SHA1NEXTE : SHAI_binop<0xD8, "sha1nexte", int_x86_sha1nexte, + SchedWriteVecIMul.XMM, "_EVEX">, + EVEX_NoCD8, T_MAP4PS; + defm SHA1MSG1 : SHAI_binop<0xD9, "sha1msg1", int_x86_sha1msg1, + SchedWriteVecIMul.XMM, "_EVEX">, + EVEX_NoCD8, T_MAP4PS; + defm SHA1MSG2 : SHAI_binop<0xDA, "sha1msg2", int_x86_sha1msg2, + SchedWriteVecIMul.XMM, "_EVEX">, + EVEX_NoCD8, T_MAP4PS; + + let Uses=[XMM0] in + defm SHA256RNDS2 : SHAI_binop<0xDB, "sha256rnds2", int_x86_sha256rnds2, + SchedWriteVecIMul.XMM, "_EVEX", 1>, + EVEX_NoCD8, T_MAP4PS; + + defm SHA256MSG1 : SHAI_binop<0xDC, "sha256msg1", int_x86_sha256msg1, + SchedWriteVecIMul.XMM, "_EVEX">, + EVEX_NoCD8, T_MAP4PS; + defm SHA256MSG2 : SHAI_binop<0xDD, "sha256msg2", int_x86_sha256msg2, + SchedWriteVecIMul.XMM, "_EVEX">, + EVEX_NoCD8, T_MAP4PS; +} + // Aliases with explicit %xmm0 def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}", (SHA256RNDS2rr VR128:$dst, VR128:$src2), 0>; def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}", (SHA256RNDS2rm VR128:$dst, i128mem:$src2), 0>; +def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}", + (SHA256RNDS2rr_EVEX VR128:$dst, VR128:$src2), 0>; +def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}", + (SHA256RNDS2rm_EVEX VR128:$dst, i128mem:$src2), 0>; + //===----------------------------------------------------------------------===// // AES-NI Instructions //===----------------------------------------------------------------------===// diff --git a/llvm/test/MC/Disassembler/X86/apx/sha1msg1.txt b/llvm/test/MC/Disassembler/X86/apx/sha1msg1.txt new file mode 100644 index 0000000000000..1c94fa88a3d3c --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/sha1msg1.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: sha1msg1 %xmm13, %xmm12 +# INTEL: sha1msg1 xmm12, xmm13 +0x45,0x0f,0x38,0xc9,0xe5 + +# ATT: sha1msg1 291(%r28,%r29,4), %xmm12 +# INTEL: sha1msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291] +0x62,0x1c,0x78,0x08,0xd9,0xa4,0xac,0x23,0x01,0x00,0x00 diff --git a/llvm/test/MC/Disassembler/X86/apx/sha1msg2.txt b/llvm/test/MC/Disassembler/X86/apx/sha1msg2.txt new file mode 100644 index 0000000000000..5fd17d9f32600 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/sha1msg2.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: sha1msg2 %xmm13, %xmm12 +# INTEL: sha1msg2 xmm12, xmm13 +0x45,0x0f,0x38,0xca,0xe5 + +# ATT: sha1msg2 291(%r28,%r29,4), %xmm12 +# INTEL: sha1msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291] +0x62,0x1c,0x78,0x08,0xda,0xa4,0xac,0x23,0x01,0x00,0x00 diff --git a/llvm/test/MC/Disassembler/X86/apx/sha1nexte.txt b/llvm/test/MC/Disassembler/X86/apx/sha1nexte.txt new file mode 100644 index 0000000000000..3c5eae3d7177f --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/sha1nexte.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: sha1nexte %xmm13, %xmm12 +# INTEL: sha1nexte xmm12, xmm13 +0x45,0x0f,0x38,0xc8,0xe5 + +# ATT: sha1nexte 291(%r28,%r29,4), %xmm12 +# INTEL: sha1nexte xmm12, xmmword ptr [r28 + 4*r29 + 291] +0x62,0x1c,0x78,0x08,0xd8,0xa4,0xac,0x23,0x01,0x00,0x00 diff --git a/llvm/test/MC/Disassembler/X86/apx/sha1rnds4.txt b/llvm/test/MC/Disassembler/X86/apx/sha1rnds4.txt new file mode 100644 index 0000000000000..a05f17739606a --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/sha1rnds4.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: sha1rnds4 $123, %xmm13, %xmm12 +# INTEL: sha1rnds4 xmm12, xmm13, 123 +0x45,0x0f,0x3a,0xcc,0xe5,0x7b + +# ATT: sha1rnds4 $123, 291(%r28,%r29,4), %xmm12 +# INTEL: sha1rnds4 xmm12, xmmword ptr [r28 + 4*r29 + 291], 123 +0x62,0x1c,0x78,0x08,0xd4,0xa4,0xac,0x23,0x01,0x00,0x00,0x7b diff --git a/llvm/test/MC/Disassembler/X86/apx/sha256msg1.txt b/llvm/test/MC/Disassembler/X86/apx/sha256msg1.txt new file mode 100644 index 0000000000000..b4c14866647dd --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/sha256msg1.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: sha256msg1 %xmm13, %xmm12 +# INTEL: sha256msg1 xmm12, xmm13 +0x45,0x0f,0x38,0xcc,0xe5 + +# ATT: sha256msg1 291(%r28,%r29,4), %xmm12 +# INTEL: sha256msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291] +0x62,0x1c,0x78,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00 diff --git a/llvm/test/MC/Disassembler/X86/apx/sha256msg2.txt b/llvm/test/MC/Disassembler/X86/apx/sha256msg2.txt new file mode 100644 index 0000000000000..75099b428e2b6 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/sha256msg2.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: sha256msg2 %xmm13, %xmm12 +# INTEL: sha256msg2 xmm12, xmm13 +0x45,0x0f,0x38,0xcd,0xe5 + +# ATT: sha256msg2 291(%r28,%r29,4), %xmm12 +# INTEL: sha256msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291] +0x62,0x1c,0x78,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00 diff --git a/llvm/test/MC/Disassembler/X86/apx/sha256rnds2.txt b/llvm/test/MC/Disassembler/X86/apx/sha256rnds2.txt new file mode 100644 index 0000000000000..1ca60aa9e9b1a --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/sha256rnds2.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: sha256rnds2 %xmm0, %xmm13, %xmm12 +# INTEL: sha256rnds2 xmm12, xmm13, xmm0 +0x45,0x0f,0x38,0xcb,0xe5 + +# ATT: sha256rnds2 %xmm0, 291(%r28,%r29,4), %xmm12 +# INTEL: sha256rnds2 xmm12, xmmword ptr [r28 + 4*r29 + 291], xmm0 +0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00 diff --git a/llvm/test/MC/X86/apx/sha1msg1-att.s b/llvm/test/MC/X86/apx/sha1msg1-att.s new file mode 100644 index 0000000000000..900b1b703c48b --- /dev/null +++ b/llvm/test/MC/X86/apx/sha1msg1-att.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s + +# CHECK: sha1msg1 %xmm13, %xmm12 +# CHECK: encoding: [0x45,0x0f,0x38,0xc9,0xe5] + sha1msg1 %xmm13, %xmm12 + +# CHECK: sha1msg1 291(%r28,%r29,4), %xmm12 +# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd9,0xa4,0xac,0x23,0x01,0x00,0x00] + sha1msg1 291(%r28,%r29,4), %xmm12 diff --git a/llvm/test/MC/X86/apx/sha1msg1-intel.s b/llvm/test/MC/X86/apx/sha1msg1-intel.s new file mode 100644 index 0000000000000..bd57463344524 --- /dev/null +++ b/llvm/test/MC/X86/apx/sha1msg1-intel.s @@ -0,0 +1,10 @@ +# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +# CHECK: sha1msg1 xmm12, xmm13 +# CHECK: encoding: [0x45,0x0f,0x38,0xc9,0xe5] + sha1msg1 xmm12, xmm13 + +# CHECK: sha1msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291] +# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd9,0xa4,0xac,0x23,0x01,0x00,0x00] + sha1msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291] + \ No newline at end of file diff --git a/llvm/test/MC/X86/apx/sha1msg2-att.s b/llvm/test/MC/X86/apx/sha1msg2-att.s new file mode 100644 index 0000000000000..62557e46f8b9d --- /dev/null +++ b/llvm/test/MC/X86/apx/sha1msg2-att.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s + +# CHECK: sha1msg2 %xmm13, %xmm12 +# CHECK: encoding: [0x45,0x0f,0x38,0xca,0xe5] + sha1msg2 %xmm13, %xmm12 + +# CHECK: sha1msg2 291(%r28,%r29,4), %xmm12 +# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xda,0xa4,0xac,0x23,0x01,0x00,0x00] + sha1msg2 291(%r28,%r29,4), %xmm12 diff --git a/llvm/test/MC/X86/apx/sha1msg2-intel.s b/llvm/test/MC/X86/apx/sha1msg2-intel.s new file mode 100644 index 0000000000000..546a56263bbe2 --- /dev/null +++ b/llvm/test/MC/X86/apx/sha1msg2-intel.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +# CHECK: sha1msg2 xmm12, xmm13 +# CHECK: encoding: [0x45,0x0f,0x38,0xca,0xe5] + sha1msg2 xmm12, xmm13 + +# CHECK: sha1msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291] +# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xda,0xa4,0xac,0x23,0x01,0x00,0x00] + sha1msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291] diff --git a/llvm/test/MC/X86/apx/sha1nexte-att.s b/llvm/test/MC/X86/apx/sha1nexte-att.s new file mode 100644 index 0000000000000..70e8300cb70a7 --- /dev/null +++ b/llvm/test/MC/X86/apx/sha1nexte-att.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s + +# CHECK: sha1nexte %xmm13, %xmm12 +# CHECK: encoding: [0x45,0x0f,0x38,0xc8,0xe5] + sha1nexte %xmm13, %xmm12 + +# CHECK: sha1nexte 291(%r28,%r29,4), %xmm12 +# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd8,0xa4,0xac,0x23,0x01,0x00,0x00] + sha1nexte 291(%r28,%r29,4), %xmm12 diff --git a/llvm/test/MC/X86/apx/sha1nexte-intel.s b/llvm/test/MC/X86/apx/sha1nexte-intel.s new file mode 100644 index 0000000000000..1c890c3cda44a --- /dev/null +++ b/llvm/test/MC/X86/apx/sha1nexte-intel.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +# CHECK: sha1nexte xmm12, xmm13 +# CHECK: encoding: [0x45,0x0f,0x38,0xc8,0xe5] + sha1nexte xmm12, xmm13 + +# CHECK: sha1nexte xmm12, xmmword ptr [r28 + 4*r29 + 291] +# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd8,0xa4,0xac,0x23,0x01,0x00,0x00] + sha1nexte xmm12, xmmword ptr [r28 + 4*r29 + 291] diff --git a/llvm/test/MC/X86/apx/sha1rnds4-att.s b/llvm/test/MC/X86/apx/sha1rnds4-att.s new file mode 100644 index 0000000000000..1d24c83a0b30e --- /dev/null +++ b/llvm/test/MC/X86/apx/sha1rnds4-att.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s + +# CHECK: sha1rnds4 $123, %xmm13, %xmm12 +# CHECK: encoding: [0x45,0x0f,0x3a,0xcc,0xe5,0x7b] + sha1rnds4 $123, %xmm13, %xmm12 + +# CHECK: sha1rnds4 $123, 291(%r28,%r29,4), %xmm12 +# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd4,0xa4,0xac,0x23,0x01,0x00,0x00,0x7b] + sha1rnds4 $123, 291(%r28,%r29,4), %xmm12 diff --git a/llvm/test/MC/X86/apx/sha1rnds4-intel.s b/llvm/test/MC/X86/apx/sha1rnds4-intel.s new file mode 100644 index 0000000000000..53620856bbf0f --- /dev/null +++ b/llvm/test/MC/X86/apx/sha1rnds4-intel.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +# CHECK: sha1rnds4 xmm12, xmm13, 123 +# CHECK: encoding: [0x45,0x0f,0x3a,0xcc,0xe5,0x7b] + sha1rnds4 xmm12, xmm13, 123 + +# CHECK: sha1rnds4 xmm12, xmmword ptr [r28 + 4*r29 + 291], 123 +# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd4,0xa4,0xac,0x23,0x01,0x00,0x00,0x7b] + sha1rnds4 xmm12, xmmword ptr [r28 + 4*r29 + 291], 123 diff --git a/llvm/test/MC/X86/apx/sha256msg1-att.s b/llvm/test/MC/X86/apx/sha256msg1-att.s new file mode 100644 index 0000000000000..c6d833dc78039 --- /dev/null +++ b/llvm/test/MC/X86/apx/sha256msg1-att.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s + +# CHECK: sha256msg1 %xmm13, %xmm12 +# CHECK: encoding: [0x45,0x0f,0x38,0xcc,0xe5] + sha256msg1 %xmm13, %xmm12 + +# CHECK: sha256msg1 291(%r28,%r29,4), %xmm12 +# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00] + sha256msg1 291(%r28,%r29,4), %xmm12 diff --git a/llvm/test/MC/X86/apx/sha256msg1-intel.s b/llvm/test/MC/X86/apx/sha256msg1-intel.s new file mode 100644 index 0000000000000..e3e96f9e2f7d5 --- /dev/null +++ b/llvm/test/MC/X86/apx/sha256msg1-intel.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +# CHECK: sha256msg1 xmm12, xmm13 +# CHECK: encoding: [0x45,0x0f,0x38,0xcc,0xe5] + sha256msg1 xmm12, xmm13 + +# CHECK: sha256msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291] +# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00] + sha256msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291] diff --git a/llvm/test/MC/X86/apx/sha256msg2-att.s b/llvm/test/MC/X86/apx/sha256msg2-att.s new file mode 100644 index 0000000000000..979ee88633b67 --- /dev/null +++ b/llvm/test/MC/X86/apx/sha256msg2-att.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s + +# CHECK: sha256msg2 %xmm13, %xmm12 +# CHECK: encoding: [0x45,0x0f,0x38,0xcd,0xe5] + sha256msg2 %xmm13, %xmm12 + +# CHECK: sha256msg2 291(%r28,%r29,4), %xmm12 +# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00] + sha256msg2 291(%r28,%r29,4), %xmm12 \ No newline at end of file diff --git a/llvm/test/MC/X86/apx/sha256msg2-intel.s b/llvm/test/MC/X86/apx/sha256msg2-intel.s new file mode 100644 index 0000000000000..043633de1c041 --- /dev/null +++ b/llvm/test/MC/X86/apx/sha256msg2-intel.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +# CHECK: sha256msg2 xmm12, xmm13 +# CHECK: encoding: [0x45,0x0f,0x38,0xcd,0xe5] + sha256msg2 xmm12, xmm13 + +# CHECK: sha256msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291] +# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00] + sha256msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291] diff --git a/llvm/test/MC/X86/apx/sha256rnds2-att.s b/llvm/test/MC/X86/apx/sha256rnds2-att.s new file mode 100644 index 0000000000000..56ae30a2e3a9e --- /dev/null +++ b/llvm/test/MC/X86/apx/sha256rnds2-att.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s + +# CHECK: sha256rnds2 %xmm0, %xmm13, %xmm12 +# CHECK: encoding: [0x45,0x0f,0x38,0xcb,0xe5] + sha256rnds2 %xmm0, %xmm13, %xmm12 + +# CHECK: sha256rnds2 %xmm0, 291(%r28,%r29,4), %xmm12 +# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00] + sha256rnds2 %xmm0, 291(%r28,%r29,4), %xmm12 diff --git a/llvm/test/MC/X86/apx/sha256rnds2-intel.s b/llvm/test/MC/X86/apx/sha256rnds2-intel.s new file mode 100644 index 0000000000000..4ae727de80b91 --- /dev/null +++ b/llvm/test/MC/X86/apx/sha256rnds2-intel.s @@ -0,0 +1,10 @@ + +# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +# CHECK: sha256rnds2 xmm12, xmm13, xmm0 +# CHECK: encoding: [0x45,0x0f,0x38,0xcb,0xe5] + sha256rnds2 xmm12, xmm13, xmm0 + +# CHECK: sha256rnds2 xmm12, xmmword ptr [r28 + 4*r29 + 291], xmm0 +# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00] + sha256rnds2 xmm12, xmmword ptr [r28 + 4*r29 + 291], xmm0 diff --git a/llvm/test/TableGen/x86-fold-tables.inc b/llvm/test/TableGen/x86-fold-tables.inc index 67b5c6cc28891..8d9ca6c39dc4d 100644 --- a/llvm/test/TableGen/x86-fold-tables.inc +++ b/llvm/test/TableGen/x86-fold-tables.inc @@ -1632,12 +1632,19 @@ static const X86FoldTableEntry Table2[] = { {X86::SBB64rr, X86::SBB64rm, 0}, {X86::SBB8rr, X86::SBB8rm, 0}, {X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16}, + {X86::SHA1MSG1rr_EVEX, X86::SHA1MSG1rm_EVEX, 0}, {X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16}, + {X86::SHA1MSG2rr_EVEX, X86::SHA1MSG2rm_EVEX, 0}, {X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16}, + {X86::SHA1NEXTErr_EVEX, X86::SHA1NEXTErm_EVEX, 0}, {X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16}, + {X86::SHA1RNDS4rri_EVEX, X86::SHA1RNDS4rmi_EVEX, 0}, {X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16}, + {X86::SHA256MSG1rr_EVEX, X86::SHA256MSG1rm_EVEX, 0}, {X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16}, + {X86::SHA256MSG2rr_EVEX, X86::SHA256MSG2rm_EVEX, 0}, {X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16}, + {X86::SHA256RNDS2rr_EVEX, X86::SHA256RNDS2rm_EVEX, 0}, {X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16}, {X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16}, {X86::SQRTSDr_Int, X86::SQRTSDm_Int, TB_NO_REVERSE}, From 6fb9e335261bbf6049edac773dc9a6651d648176 Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Sun, 17 Dec 2023 23:08:58 -0800 Subject: [PATCH 2/5] resolve comments --- llvm/lib/Target/X86/X86InstrSSE.td | 4 +--- llvm/test/MC/X86/apx/sha1msg1-intel.s | 1 - llvm/test/MC/X86/apx/sha256msg2-att.s | 2 +- llvm/test/MC/X86/apx/sha256rnds2-att.s | 4 ++++ llvm/test/MC/X86/apx/sha256rnds2-intel.s | 4 ++++ llvm/test/TableGen/x86-fold-tables.inc | 14 +++++++------- llvm/utils/TableGen/X86FoldTablesEmitter.cpp | 4 +++- 7 files changed, 20 insertions(+), 13 deletions(-) diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index acf068d38b5de..a8631df640f56 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -6765,7 +6765,7 @@ let Constraints = "$src1 = $dst", Predicates = [HasSHA, NoEGPR] in { SchedWriteVecIMul.XMM>; } -let Constraints = "$src1 = $dst", Predicates = [HasSHA, HasEGPR, In64BitMode]in { +let Constraints = "$src1 = $dst", Predicates = [HasSHA, HasEGPR, In64BitMode] in { def SHA1RNDS4rri_EVEX: Ii8<0xD4, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, u8imm:$src3), "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}", @@ -6813,8 +6813,6 @@ def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}", def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}", (SHA256RNDS2rm VR128:$dst, i128mem:$src2), 0>; -def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}", - (SHA256RNDS2rr_EVEX VR128:$dst, VR128:$src2), 0>; def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}", (SHA256RNDS2rm_EVEX VR128:$dst, i128mem:$src2), 0>; diff --git a/llvm/test/MC/X86/apx/sha1msg1-intel.s b/llvm/test/MC/X86/apx/sha1msg1-intel.s index bd57463344524..d347a671069f5 100644 --- a/llvm/test/MC/X86/apx/sha1msg1-intel.s +++ b/llvm/test/MC/X86/apx/sha1msg1-intel.s @@ -7,4 +7,3 @@ # CHECK: sha1msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291] # CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd9,0xa4,0xac,0x23,0x01,0x00,0x00] sha1msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291] - \ No newline at end of file diff --git a/llvm/test/MC/X86/apx/sha256msg2-att.s b/llvm/test/MC/X86/apx/sha256msg2-att.s index 979ee88633b67..96528d90c3f4a 100644 --- a/llvm/test/MC/X86/apx/sha256msg2-att.s +++ b/llvm/test/MC/X86/apx/sha256msg2-att.s @@ -6,4 +6,4 @@ # CHECK: sha256msg2 291(%r28,%r29,4), %xmm12 # CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00] - sha256msg2 291(%r28,%r29,4), %xmm12 \ No newline at end of file + sha256msg2 291(%r28,%r29,4), %xmm12 diff --git a/llvm/test/MC/X86/apx/sha256rnds2-att.s b/llvm/test/MC/X86/apx/sha256rnds2-att.s index 56ae30a2e3a9e..498907c51810f 100644 --- a/llvm/test/MC/X86/apx/sha256rnds2-att.s +++ b/llvm/test/MC/X86/apx/sha256rnds2-att.s @@ -7,3 +7,7 @@ # CHECK: sha256rnds2 %xmm0, 291(%r28,%r29,4), %xmm12 # CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00] sha256rnds2 %xmm0, 291(%r28,%r29,4), %xmm12 + +# CHECK: sha256rnds2 %xmm0, 291(%r28,%r29,4), %xmm12 +# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00] + sha256rnds2 291(%r28,%r29,4), %xmm12 \ No newline at end of file diff --git a/llvm/test/MC/X86/apx/sha256rnds2-intel.s b/llvm/test/MC/X86/apx/sha256rnds2-intel.s index 4ae727de80b91..7630f3c2cd22f 100644 --- a/llvm/test/MC/X86/apx/sha256rnds2-intel.s +++ b/llvm/test/MC/X86/apx/sha256rnds2-intel.s @@ -8,3 +8,7 @@ # CHECK: sha256rnds2 xmm12, xmmword ptr [r28 + 4*r29 + 291], xmm0 # CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00] sha256rnds2 xmm12, xmmword ptr [r28 + 4*r29 + 291], xmm0 + +# CHECK: sha256rnds2 xmm12, xmmword ptr [r28 + 4*r29 + 291], xmm0 +# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00] + sha256rnds2 xmm12, xmmword ptr [r28 + 4*r29 + 291] diff --git a/llvm/test/TableGen/x86-fold-tables.inc b/llvm/test/TableGen/x86-fold-tables.inc index 8d9ca6c39dc4d..4f957d104d8dd 100644 --- a/llvm/test/TableGen/x86-fold-tables.inc +++ b/llvm/test/TableGen/x86-fold-tables.inc @@ -1632,19 +1632,19 @@ static const X86FoldTableEntry Table2[] = { {X86::SBB64rr, X86::SBB64rm, 0}, {X86::SBB8rr, X86::SBB8rm, 0}, {X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16}, - {X86::SHA1MSG1rr_EVEX, X86::SHA1MSG1rm_EVEX, 0}, + {X86::SHA1MSG1rr_EVEX, X86::SHA1MSG1rm_EVEX, TB_ALIGN_16}, {X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16}, - {X86::SHA1MSG2rr_EVEX, X86::SHA1MSG2rm_EVEX, 0}, + {X86::SHA1MSG2rr_EVEX, X86::SHA1MSG2rm_EVEX, TB_ALIGN_16}, {X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16}, - {X86::SHA1NEXTErr_EVEX, X86::SHA1NEXTErm_EVEX, 0}, + {X86::SHA1NEXTErr_EVEX, X86::SHA1NEXTErm_EVEX, TB_ALIGN_16}, {X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16}, - {X86::SHA1RNDS4rri_EVEX, X86::SHA1RNDS4rmi_EVEX, 0}, + {X86::SHA1RNDS4rri_EVEX, X86::SHA1RNDS4rmi_EVEX, TB_ALIGN_16}, {X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16}, - {X86::SHA256MSG1rr_EVEX, X86::SHA256MSG1rm_EVEX, 0}, + {X86::SHA256MSG1rr_EVEX, X86::SHA256MSG1rm_EVEX, TB_ALIGN_16}, {X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16}, - {X86::SHA256MSG2rr_EVEX, X86::SHA256MSG2rm_EVEX, 0}, + {X86::SHA256MSG2rr_EVEX, X86::SHA256MSG2rm_EVEX, TB_ALIGN_16}, {X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16}, - {X86::SHA256RNDS2rr_EVEX, X86::SHA256RNDS2rm_EVEX, 0}, + {X86::SHA256RNDS2rr_EVEX, X86::SHA256RNDS2rm_EVEX, TB_ALIGN_16}, {X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16}, {X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16}, {X86::SQRTSDr_Int, X86::SQRTSDm_Int, TB_NO_REVERSE}, diff --git a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp index 83025205310e8..5b2d0d68c26e0 100644 --- a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp +++ b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp @@ -33,7 +33,9 @@ struct ManualMapEntry { // List of instructions requiring explicitly aligned memory. const char *ExplicitAlign[] = {"MOVDQA", "MOVAPS", "MOVAPD", "MOVNTPS", - "MOVNTPD", "MOVNTDQ", "MOVNTDQA"}; + "MOVNTPD", "MOVNTDQ", "MOVNTDQA", "SHA1MSG1", + "SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4", + "SHA256MSG1", "SHA256MSG2", "SHA256RNDS2"}; // List of instructions NOT requiring explicit memory alignment. const char *ExplicitUnalign[] = {"MOVDQU", "MOVUPS", "MOVUPD", From ed823552103360adeababfb76f7ea96fd7d25709 Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Sun, 17 Dec 2023 23:10:46 -0800 Subject: [PATCH 3/5] Add 1 blank line end of file --- llvm/test/MC/X86/apx/sha256rnds2-att.s | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/test/MC/X86/apx/sha256rnds2-att.s b/llvm/test/MC/X86/apx/sha256rnds2-att.s index 498907c51810f..3071d40babf5b 100644 --- a/llvm/test/MC/X86/apx/sha256rnds2-att.s +++ b/llvm/test/MC/X86/apx/sha256rnds2-att.s @@ -10,4 +10,4 @@ # CHECK: sha256rnds2 %xmm0, 291(%r28,%r29,4), %xmm12 # CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00] - sha256rnds2 291(%r28,%r29,4), %xmm12 \ No newline at end of file + sha256rnds2 291(%r28,%r29,4), %xmm12 From 4939541d699b61d4763289012bc8ae0b4259bbe8 Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Mon, 18 Dec 2023 18:26:16 -0800 Subject: [PATCH 4/5] resolve comment and fix 1 test --- llvm/lib/Target/X86/X86InstrAsmAlias.td | 8 ++++++++ llvm/lib/Target/X86/X86InstrSSE.td | 9 --------- llvm/test/MC/X86/x86_64-asm-match.s | 2 +- 3 files changed, 9 insertions(+), 10 deletions(-) diff --git a/llvm/lib/Target/X86/X86InstrAsmAlias.td b/llvm/lib/Target/X86/X86InstrAsmAlias.td index 9d0735c9cbba4..f1a90d9c59c3d 100644 --- a/llvm/lib/Target/X86/X86InstrAsmAlias.td +++ b/llvm/lib/Target/X86/X86InstrAsmAlias.td @@ -686,3 +686,11 @@ def : InstAlias<"vmsave\t{%rax|rax}", (VMSAVE64), 0>, Requires<[In64BitMode]>; def : InstAlias<"invlpga\t{%eax, %ecx|eax, ecx}", (INVLPGA32), 0>, Requires<[Not64BitMode]>; def : InstAlias<"invlpga\t{%rax, %ecx|rax, ecx}", (INVLPGA64), 0>, Requires<[In64BitMode]>; +// Aliases with explicit %xmm0 +def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}", + (SHA256RNDS2rr VR128:$dst, VR128:$src2), 0>; +def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}", + (SHA256RNDS2rm VR128:$dst, i128mem:$src2), 0>; + +def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}", + (SHA256RNDS2rm_EVEX VR128:$dst, i128mem:$src2), 0>; diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index a8631df640f56..be6962ebbb4fb 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -6807,15 +6807,6 @@ let Constraints = "$src1 = $dst", Predicates = [HasSHA, HasEGPR, In64BitMode] in EVEX_NoCD8, T_MAP4PS; } -// Aliases with explicit %xmm0 -def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}", - (SHA256RNDS2rr VR128:$dst, VR128:$src2), 0>; -def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}", - (SHA256RNDS2rm VR128:$dst, i128mem:$src2), 0>; - -def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}", - (SHA256RNDS2rm_EVEX VR128:$dst, i128mem:$src2), 0>; - //===----------------------------------------------------------------------===// // AES-NI Instructions //===----------------------------------------------------------------------===// diff --git a/llvm/test/MC/X86/x86_64-asm-match.s b/llvm/test/MC/X86/x86_64-asm-match.s index 50f25e59f49f4..736b0d968fc6f 100644 --- a/llvm/test/MC/X86/x86_64-asm-match.s +++ b/llvm/test/MC/X86/x86_64-asm-match.s @@ -11,7 +11,7 @@ // CHECK: Matching formal operand class MCK_FR16 against actual operand at index 2 (Reg:xmm1): match success using generic matcher // CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range // CHECK: Opcode result: complete match, selecting this opcode -// CHECK: AsmMatcher: found 2 encodings with mnemonic 'sha1rnds4' +// CHECK: AsmMatcher: found 4 encodings with mnemonic 'sha1rnds4' // CHECK: Trying to match opcode SHA1RNDS4rri // CHECK: Matching formal operand class MCK_ImmUnsignedi8 against actual operand at index 1 (Imm:1): match success using generic matcher // CHECK: Matching formal operand class MCK_FR16 against actual operand at index 2 (Reg:xmm1): match success using generic matcher From c0bb6be657b1548a5748800070cd2fe23f8af46f Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Mon, 18 Dec 2023 18:44:00 -0800 Subject: [PATCH 5/5] clang format --- llvm/utils/TableGen/X86FoldTablesEmitter.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp index 5b2d0d68c26e0..d3299e2810316 100644 --- a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp +++ b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp @@ -32,10 +32,10 @@ struct ManualMapEntry { }; // List of instructions requiring explicitly aligned memory. -const char *ExplicitAlign[] = {"MOVDQA", "MOVAPS", "MOVAPD", "MOVNTPS", - "MOVNTPD", "MOVNTDQ", "MOVNTDQA", "SHA1MSG1", - "SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4", - "SHA256MSG1", "SHA256MSG2", "SHA256RNDS2"}; +const char *ExplicitAlign[] = { + "MOVDQA", "MOVAPS", "MOVAPD", "MOVNTPS", "MOVNTPD", + "MOVNTDQ", "MOVNTDQA", "SHA1MSG1", "SHA1MSG2", "SHA1NEXTE", + "SHA1RNDS4", "SHA256MSG1", "SHA256MSG2", "SHA256RNDS2"}; // List of instructions NOT requiring explicit memory alignment. const char *ExplicitUnalign[] = {"MOVDQU", "MOVUPS", "MOVUPD",