From 8dd38272b5ff609ee3d69e040bb14acc72635010 Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Mon, 1 Jan 2024 23:47:12 -0800 Subject: [PATCH 01/12] nf support --- llvm/lib/Target/X86/X86InstrArithmetic.td | 4 ++++ llvm/lib/Target/X86/X86InstrMisc.td | 16 ++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td index 560a4097a9c01..7fe18f1ab0e9e 100644 --- a/llvm/lib/Target/X86/X86InstrArithmetic.td +++ b/llvm/lib/Target/X86/X86InstrArithmetic.td @@ -1336,6 +1336,10 @@ defm ANDN32 : AndN, VEX, Requires<[HasBMI, NoEGPR]>; defm ANDN64 : AndN, VEX, REX_W, Requires<[HasBMI, NoEGPR]>; defm ANDN32 : AndN, EVEX, Requires<[HasBMI, HasEGPR, In64BitMode]>; defm ANDN64 : AndN, EVEX, REX_W, Requires<[HasBMI, HasEGPR, In64BitMode]>; +let Pattern = [(null_frag)] in { +defm ANDN32 : AndN, EVEX, EVEX_NF, Requires<[In64BitMode]>; +defm ANDN64 : AndN, EVEX, EVEX_NF, REX_W, Requires<[In64BitMode]>; +} } multiclass Andn_Pats { diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td index 229aa3c6f1f20..9aa487bb36cde 100644 --- a/llvm/lib/Target/X86/X86InstrMisc.td +++ b/llvm/lib/Target/X86/X86InstrMisc.td @@ -1241,6 +1241,15 @@ let Predicates = [HasBMI, In64BitMode], Defs = [EFLAGS] in { defm BLSI64 : Bls<"blsi", MRM3r, MRM3m, Xi64, "_EVEX">, EVEX; } +let Predicates = [In64BitMode] in { + defm BLSR32 : Bls<"blsr", MRM1r, MRM1m, Xi32, "_NF">, EVEX, EVEX_NF; + defm BLSR64 : Bls<"blsr", MRM1r, MRM1m, Xi64, "_NF">, EVEX, EVEX_NF; + defm BLSMSK32 : Bls<"blsmsk", MRM2r, MRM2m, Xi32, "_NF">, EVEX, EVEX_NF; + defm BLSMSK64 : Bls<"blsmsk", MRM2r, MRM2m, Xi64, "_NF">, EVEX, EVEX_NF; + defm BLSI32 : Bls<"blsi", MRM3r, MRM3m, Xi32, "_NF">, EVEX, EVEX_NF; + defm BLSI64 : Bls<"blsi", MRM3r, MRM3m, Xi64, "_NF">, EVEX, EVEX_NF; +} + multiclass Bls_Pats { // FIXME(1): patterns for the load versions are not implemented // FIXME(2): By only matching `add_su` and `ineg_su` we may emit @@ -1315,6 +1324,13 @@ let Predicates = [HasBMI2, HasEGPR, In64BitMode], Defs = [EFLAGS] in { defm BZHI64 : Bmi4VOp3<0xF5, "bzhi", Xi64, X86bzhi, WriteBZHI, "_EVEX">, EVEX; } +let Predicates = [In64BitMode], Pattern = [(null_frag)] in { + defm BEXTR32 : Bmi4VOp3<0xF7, "bextr", Xi32, X86bextr, WriteBEXTR, "_NF">, EVEX, EVEX_NF; + defm BEXTR64 : Bmi4VOp3<0xF7, "bextr", Xi64, X86bextr, WriteBEXTR, "_NF">, EVEX, EVEX_NF; + defm BZHI32 : Bmi4VOp3<0xF5, "bzhi", Xi32, X86bzhi, WriteBZHI, "_NF">, EVEX, EVEX_NF; + defm BZHI64 : Bmi4VOp3<0xF5, "bzhi", Xi64, X86bzhi, WriteBZHI, "_NF">, EVEX, EVEX_NF; +} + def CountTrailingOnes : SDNodeXFormgetZExtValue()), SDLoc(N)); From 9fe9404c6e184d355b671b024d4a97fec36da5f7 Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Tue, 2 Jan 2024 01:39:40 -0800 Subject: [PATCH 02/12] add tests --- .../X86/Disassembler/X86Disassembler.cpp | 17 +++++++++- llvm/test/MC/Disassembler/X86/apx/andn.txt | 32 +++++++++++++++++ llvm/test/MC/Disassembler/X86/apx/bextr.txt | 33 ++++++++++++++++++ llvm/test/MC/Disassembler/X86/apx/blsi.txt | 32 +++++++++++++++++ llvm/test/MC/Disassembler/X86/apx/blsr.txt | 32 +++++++++++++++++ llvm/test/MC/Disassembler/X86/apx/bzhi.txt | 32 +++++++++++++++++ llvm/test/MC/X86/apx/andn-att.s | 34 ++++++++++++++++++- llvm/test/MC/X86/apx/andn-intel.s | 32 +++++++++++++++++ llvm/test/MC/X86/apx/bextr-att.s | 34 ++++++++++++++++++- llvm/test/MC/X86/apx/bextr-intel.s | 32 +++++++++++++++++ llvm/test/MC/X86/apx/blsi-att.s | 34 ++++++++++++++++++- llvm/test/MC/X86/apx/blsi-intel.s | 32 +++++++++++++++++ llvm/test/MC/X86/apx/blsmsk-att.s | 34 ++++++++++++++++++- llvm/test/MC/X86/apx/blsmsk-intel.s | 32 +++++++++++++++++ llvm/test/MC/X86/apx/blsr-att.s | 34 ++++++++++++++++++- llvm/test/MC/X86/apx/blsr-intel.s | 32 +++++++++++++++++ llvm/test/MC/X86/apx/bzhi-att.s | 34 ++++++++++++++++++- llvm/test/MC/X86/apx/bzhi-intel.s | 32 +++++++++++++++++ llvm/test/TableGen/x86-fold-tables.inc | 12 +++++++ 19 files changed, 579 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp index 347dc0d4ed43a..e6697e98faaa9 100644 --- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -1134,6 +1134,21 @@ static int getInstructionIDWithAttrMask(uint16_t *instructionID, return 0; } +static bool isNFnotMap4(InternalInstruction *insn){ +// Promoted BMI instrs below has nf version. +if (insn->opcodeType == THREEBYTE_38 && + ppFromXOP3of3(insn->vectorExtensionPrefix[2]) == VEX_PREFIX_NONE) { + switch (insn->opcode) { + case 0xf2: // ANDN + case 0xf3: // BLSI, BLSR, BLSMSK + case 0xf5: // BZHI + case 0xf7: // BEXTR + return true; + } +} + return false; +} + // Determine the ID of an instruction, consuming the ModR/M byte as appropriate // for extended and escape opcodes. Determines the attributes and context for // the instruction before doing so. @@ -1171,7 +1186,7 @@ static int getInstructionID(struct InternalInstruction *insn, attrMask |= ATTR_EVEXB; // nf bit is the MSB of aaa if (nfFromEVEX4of4(insn->vectorExtensionPrefix[3]) && - insn->opcodeType == MAP4) + (insn->opcodeType == MAP4 || isNFnotMap4(insn))) attrMask |= ATTR_EVEXNF; else if (aaaFromEVEX4of4(insn->vectorExtensionPrefix[3])) attrMask |= ATTR_EVEXK; diff --git a/llvm/test/MC/Disassembler/X86/apx/andn.txt b/llvm/test/MC/Disassembler/X86/apx/andn.txt index 8b943d2a0ac44..564b1c51920ce 100644 --- a/llvm/test/MC/Disassembler/X86/apx/andn.txt +++ b/llvm/test/MC/Disassembler/X86/apx/andn.txt @@ -1,6 +1,38 @@ # RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT # RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL +# ATT: {nf} andnl %ecx, %edx, %r10d +# INTEL: {nf} andn r10d, edx, ecx +0x62,0x72,0x6c,0x0c,0xf2,0xd1 + +# ATT: andnl %ecx, %edx, %r10d +# INTEL: andn r10d, edx, ecx +0x62,0x72,0x6c,0x08,0xf2,0xd1 + +# ATT: {nf} andnq %r9, %r15, %r11 +# INTEL: {nf} andn r11, r15, r9 +0x62,0x52,0x84,0x0c,0xf2,0xd9 + +# ATT: andnq %r9, %r15, %r11 +# INTEL: andn r11, r15, r9 +0x62,0x52,0x84,0x08,0xf2,0xd9 + +# ATT: {nf} andnl 123(%rax,%rbx,4), %ecx, %edx +# INTEL: {nf} andn edx, ecx, dword ptr [rax + 4*rbx + 123] +0x62,0xf2,0x74,0x0c,0xf2,0x94,0x98,0x7b,0x00,0x00,0x00 + +# ATT: andnl 123(%rax,%rbx,4), %ecx, %edx +# INTEL: andn edx, ecx, dword ptr [rax + 4*rbx + 123] +0x62,0xf2,0x74,0x08,0xf2,0x94,0x98,0x7b,0x00,0x00,0x00 + +# ATT: {nf} andnq 123(%rax,%rbx,4), %r9, %r15 +# INTEL: {nf} andn r15, r9, qword ptr [rax + 4*rbx + 123] +0x62,0x72,0xb4,0x0c,0xf2,0xbc,0x98,0x7b,0x00,0x00,0x00 + +# ATT: andnq 123(%rax,%rbx,4), %r9, %r15 +# INTEL: andn r15, r9, qword ptr [rax + 4*rbx + 123] +0x62,0x72,0xb4,0x08,0xf2,0xbc,0x98,0x7b,0x00,0x00,0x00 + # ATT: andnl %r18d, %r22d, %r26d # INTEL: andn r26d, r22d, r18d 0x62,0x6a,0x4c,0x00,0xf2,0xd2 diff --git a/llvm/test/MC/Disassembler/X86/apx/bextr.txt b/llvm/test/MC/Disassembler/X86/apx/bextr.txt index abd92864b315e..e5dfbbbdd5fa1 100644 --- a/llvm/test/MC/Disassembler/X86/apx/bextr.txt +++ b/llvm/test/MC/Disassembler/X86/apx/bextr.txt @@ -1,6 +1,39 @@ # RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT # RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL +# CHECK: {nf} bextr r10d, edx, ecx +# CHECK: encoding: [0x62,0x72,0x74,0x0c,0xf7,0xd2] + {nf} bextr r10d, edx, ecx + +# CHECK: bextr r10d, edx, ecx +# CHECK: encoding: [0x62,0x72,0x74,0x08,0xf7,0xd2] + bextr r10d, edx, ecx + +# CHECK: {nf} bextr edx, dword ptr [rax + 4*rbx + 123], ecx +# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00] + {nf} bextr edx, dword ptr [rax + 4*rbx + 123], ecx + +# CHECK: bextr edx, dword ptr [rax + 4*rbx + 123], ecx +# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00] + bextr edx, dword ptr [rax + 4*rbx + 123], ecx + +# CHECK: {nf} bextr r11, r15, r9 +# CHECK: encoding: [0x62,0x52,0xb4,0x0c,0xf7,0xdf] + {nf} bextr r11, r15, r9 + +# CHECK: bextr r11, r15, r9 +# CHECK: encoding: [0x62,0x52,0xb4,0x08,0xf7,0xdf] + bextr r11, r15, r9 + +# CHECK: {nf} bextr r15, qword ptr [rax + 4*rbx + 123], r9 +# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00] + {nf} bextr r15, qword ptr [rax + 4*rbx + 123], r9 + +# CHECK: bextr r15, qword ptr [rax + 4*rbx + 123], r9 +# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00] + bextr r15, qword ptr [rax + 4*rbx + 123], r9 + + # ATT: bextrl %r18d, %r22d, %r26d # INTEL: bextr r26d, r22d, r18d 0x62,0x6a,0x6c,0x00,0xf7,0xd6 diff --git a/llvm/test/MC/Disassembler/X86/apx/blsi.txt b/llvm/test/MC/Disassembler/X86/apx/blsi.txt index 254ec90caea51..af984a8b7b637 100644 --- a/llvm/test/MC/Disassembler/X86/apx/blsi.txt +++ b/llvm/test/MC/Disassembler/X86/apx/blsi.txt @@ -1,6 +1,38 @@ # RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT # RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL +# ATT: {nf} blsil %ecx, %edx +# INTEL: {nf} blsi edx, ecx +0x62,0xf2,0x6c,0x0c,0xf3,0xd9 + +# ATT: blsil %ecx, %edx +# INTEL: blsi edx, ecx +0x62,0xf2,0x6c,0x08,0xf3,0xd9 + +# ATT: {nf} blsiq %r9, %r15 +# INTEL: {nf} blsi r15, r9 +0x62,0xd2,0x84,0x0c,0xf3,0xd9 + +# ATT: blsiq %r9, %r15 +# INTEL: blsi r15, r9 +0x62,0xd2,0x84,0x08,0xf3,0xd9 + +# ATT: {nf} blsil 123(%rax,%rbx,4), %ecx +# INTEL: {nf} blsi ecx, dword ptr [rax + 4*rbx + 123] +0x62,0xf2,0x74,0x0c,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00 + +# ATT: blsil 123(%rax,%rbx,4), %ecx +# INTEL: blsi ecx, dword ptr [rax + 4*rbx + 123] +0x62,0xf2,0x74,0x08,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00 + +# ATT: {nf} blsiq 123(%rax,%rbx,4), %r9 +# INTEL: {nf} blsi r9, qword ptr [rax + 4*rbx + 123] +0x62,0xf2,0xb4,0x0c,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00 + +# ATT: blsiq 123(%rax,%rbx,4), %r9 +# INTEL: blsi r9, qword ptr [rax + 4*rbx + 123] +0x62,0xf2,0xb4,0x08,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00 + # ATT: blsil %r18d, %r22d # INTEL: blsi r22d, r18d 0x62,0xfa,0x4c,0x00,0xf3,0xda diff --git a/llvm/test/MC/Disassembler/X86/apx/blsr.txt b/llvm/test/MC/Disassembler/X86/apx/blsr.txt index 37df4306da26e..6f7874595aa7a 100644 --- a/llvm/test/MC/Disassembler/X86/apx/blsr.txt +++ b/llvm/test/MC/Disassembler/X86/apx/blsr.txt @@ -1,6 +1,38 @@ # RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT # RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL +# ATT: {nf} blsrl %ecx, %edx +# INTEL: {nf} blsr edx, ecx +0x62,0xf2,0x6c,0x0c,0xf3,0xc9 + +# ATT: blsrl %ecx, %edx +# INTEL: blsr edx, ecx +0x62,0xf2,0x6c,0x08,0xf3,0xc9 + +# ATT: {nf} blsrq %r9, %r15 +# INTEL: {nf} blsr r15, r9 +0x62,0xd2,0x84,0x0c,0xf3,0xc9 + +# ATT: blsrq %r9, %r15 +# INTEL: blsr r15, r9 +0x62,0xd2,0x84,0x08,0xf3,0xc9 + +# ATT: {nf} blsrl 123(%rax,%rbx,4), %ecx +# INTEL: {nf} blsr ecx, dword ptr [rax + 4*rbx + 123] +0x62,0xf2,0x74,0x0c,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00 + +# ATT: blsrl 123(%rax,%rbx,4), %ecx +# INTEL: blsr ecx, dword ptr [rax + 4*rbx + 123] +0x62,0xf2,0x74,0x08,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00 + +# ATT: {nf} blsrq 123(%rax,%rbx,4), %r9 +# INTEL: {nf} blsr r9, qword ptr [rax + 4*rbx + 123] +0x62,0xf2,0xb4,0x0c,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00 + +# ATT: blsrq 123(%rax,%rbx,4), %r9 +# INTEL: blsr r9, qword ptr [rax + 4*rbx + 123] +0x62,0xf2,0xb4,0x08,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00 + # ATT: blsrl %r18d, %r22d # INTEL: blsr r22d, r18d 0x62,0xfa,0x4c,0x00,0xf3,0xca diff --git a/llvm/test/MC/Disassembler/X86/apx/bzhi.txt b/llvm/test/MC/Disassembler/X86/apx/bzhi.txt index 44f496e3cc084..8eec590b04878 100644 --- a/llvm/test/MC/Disassembler/X86/apx/bzhi.txt +++ b/llvm/test/MC/Disassembler/X86/apx/bzhi.txt @@ -1,6 +1,38 @@ # RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT # RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL +# ATT: {nf} bzhil %ecx, %edx, %r10d +# INTEL: {nf} bzhi r10d, edx, ecx +0x62,0x72,0x74,0x0c,0xf5,0xd2 + +# ATT: bzhil %ecx, %edx, %r10d +# INTEL: bzhi r10d, edx, ecx +0x62,0x72,0x74,0x08,0xf5,0xd2 + +# ATT: {nf} bzhil %ecx, 123(%rax,%rbx,4), %edx +# INTEL: {nf} bzhi edx, dword ptr [rax + 4*rbx + 123], ecx +0x62,0xf2,0x74,0x0c,0xf5,0x94,0x98,0x7b,0x00,0x00,0x00 + +# ATT: bzhil %ecx, 123(%rax,%rbx,4), %edx +# INTEL: bzhi edx, dword ptr [rax + 4*rbx + 123], ecx +0x62,0xf2,0x74,0x08,0xf5,0x94,0x98,0x7b,0x00,0x00,0x00 + +# ATT: {nf} bzhiq %r9, %r15, %r11 +# INTEL: {nf} bzhi r11, r15, r9 +0x62,0x52,0xb4,0x0c,0xf5,0xdf + +# ATT: bzhiq %r9, %r15, %r11 +# INTEL: bzhi r11, r15, r9 +0x62,0x52,0xb4,0x08,0xf5,0xdf + +# ATT: {nf} bzhiq %r9, 123(%rax,%rbx,4), %r15 +# INTEL: {nf} bzhi r15, qword ptr [rax + 4*rbx + 123], r9 +0x62,0x72,0xb4,0x0c,0xf5,0xbc,0x98,0x7b,0x00,0x00,0x00 + +# ATT: bzhiq %r9, 123(%rax,%rbx,4), %r15 +# INTEL: bzhi r15, qword ptr [rax + 4*rbx + 123], r9 +0x62,0x72,0xb4,0x08,0xf5,0xbc,0x98,0x7b,0x00,0x00,0x00 + # ATT: bzhil %r18d, %r22d, %r26d # INTEL: bzhi r26d, r22d, r18d 0x62,0x6a,0x6c,0x00,0xf5,0xd6 diff --git a/llvm/test/MC/X86/apx/andn-att.s b/llvm/test/MC/X86/apx/andn-att.s index d68cee8bcf1f7..f6ab0f0069ec0 100644 --- a/llvm/test/MC/X86/apx/andn-att.s +++ b/llvm/test/MC/X86/apx/andn-att.s @@ -1,8 +1,40 @@ # RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s # RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR -# ERROR-COUNT-4: error: +# ERROR-COUNT-12: error: # ERROR-NOT: error: +# CHECK: {nf} andnl %ecx, %edx, %r10d +# CHECK: encoding: [0x62,0x72,0x6c,0x0c,0xf2,0xd1] + {nf} andnl %ecx, %edx, %r10d + +# CHECK: {evex} andnl %ecx, %edx, %r10d +# CHECK: encoding: [0x62,0x72,0x6c,0x08,0xf2,0xd1] + {evex} andnl %ecx, %edx, %r10d + +# CHECK: {nf} andnq %r9, %r15, %r11 +# CHECK: encoding: [0x62,0x52,0x84,0x0c,0xf2,0xd9] + {nf} andnq %r9, %r15, %r11 + +# CHECK: {evex} andnq %r9, %r15, %r11 +# CHECK: encoding: [0x62,0x52,0x84,0x08,0xf2,0xd9] + {evex} andnq %r9, %r15, %r11 + +# CHECK: {nf} andnl 123(%rax,%rbx,4), %ecx, %edx +# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf2,0x94,0x98,0x7b,0x00,0x00,0x00] + {nf} andnl 123(%rax,%rbx,4), %ecx, %edx + +# CHECK: {evex} andnl 123(%rax,%rbx,4), %ecx, %edx +# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf2,0x94,0x98,0x7b,0x00,0x00,0x00] + {evex} andnl 123(%rax,%rbx,4), %ecx, %edx + +# CHECK: {nf} andnq 123(%rax,%rbx,4), %r9, %r15 +# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf2,0xbc,0x98,0x7b,0x00,0x00,0x00] + {nf} andnq 123(%rax,%rbx,4), %r9, %r15 + +# CHECK: {evex} andnq 123(%rax,%rbx,4), %r9, %r15 +# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf2,0xbc,0x98,0x7b,0x00,0x00,0x00] + {evex} andnq 123(%rax,%rbx,4), %r9, %r15 + # CHECK: andnl %r18d, %r22d, %r26d # CHECK: encoding: [0x62,0x6a,0x4c,0x00,0xf2,0xd2] andnl %r18d, %r22d, %r26d diff --git a/llvm/test/MC/X86/apx/andn-intel.s b/llvm/test/MC/X86/apx/andn-intel.s index 583e6e763b1ec..4a369a0d3b689 100644 --- a/llvm/test/MC/X86/apx/andn-intel.s +++ b/llvm/test/MC/X86/apx/andn-intel.s @@ -1,5 +1,37 @@ # RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s +# CHECK: {nf} andn r10d, edx, ecx +# CHECK: encoding: [0x62,0x72,0x6c,0x0c,0xf2,0xd1] + {nf} andn r10d, edx, ecx + +# CHECK: {evex} andn r10d, edx, ecx +# CHECK: encoding: [0x62,0x72,0x6c,0x08,0xf2,0xd1] + {evex} andn r10d, edx, ecx + +# CHECK: {nf} andn r11, r15, r9 +# CHECK: encoding: [0x62,0x52,0x84,0x0c,0xf2,0xd9] + {nf} andn r11, r15, r9 + +# CHECK: {evex} andn r11, r15, r9 +# CHECK: encoding: [0x62,0x52,0x84,0x08,0xf2,0xd9] + {evex} andn r11, r15, r9 + +# CHECK: {nf} andn edx, ecx, dword ptr [rax + 4*rbx + 123] +# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf2,0x94,0x98,0x7b,0x00,0x00,0x00] + {nf} andn edx, ecx, dword ptr [rax + 4*rbx + 123] + +# CHECK: {evex} andn edx, ecx, dword ptr [rax + 4*rbx + 123] +# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf2,0x94,0x98,0x7b,0x00,0x00,0x00] + {evex} andn edx, ecx, dword ptr [rax + 4*rbx + 123] + +# CHECK: {nf} andn r15, r9, qword ptr [rax + 4*rbx + 123] +# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf2,0xbc,0x98,0x7b,0x00,0x00,0x00] + {nf} andn r15, r9, qword ptr [rax + 4*rbx + 123] + +# CHECK: {evex} andn r15, r9, qword ptr [rax + 4*rbx + 123] +# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf2,0xbc,0x98,0x7b,0x00,0x00,0x00] + {evex} andn r15, r9, qword ptr [rax + 4*rbx + 123] + # CHECK: andn r26d, r22d, r18d # CHECK: encoding: [0x62,0x6a,0x4c,0x00,0xf2,0xd2] andn r26d, r22d, r18d diff --git a/llvm/test/MC/X86/apx/bextr-att.s b/llvm/test/MC/X86/apx/bextr-att.s index 6095ffa389a34..57f5d3e1c2b44 100644 --- a/llvm/test/MC/X86/apx/bextr-att.s +++ b/llvm/test/MC/X86/apx/bextr-att.s @@ -1,8 +1,40 @@ # RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s # RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR -# ERROR-COUNT-4: error: +# ERROR-COUNT-12: error: # ERROR-NOT: error: +# CHECK: {nf} bextrl %ecx, %edx, %r10d +# CHECK: encoding: [0x62,0x72,0x74,0x0c,0xf7,0xd2] + {nf} bextrl %ecx, %edx, %r10d + +# CHECK: {evex} bextrl %ecx, %edx, %r10d +# CHECK: encoding: [0x62,0x72,0x74,0x08,0xf7,0xd2] + {evex} bextrl %ecx, %edx, %r10d + +# CHECK: {nf} bextrl %ecx, 123(%rax,%rbx,4), %edx +# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00] + {nf} bextrl %ecx, 123(%rax,%rbx,4), %edx + +# CHECK: {evex} bextrl %ecx, 123(%rax,%rbx,4), %edx +# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00] + {evex} bextrl %ecx, 123(%rax,%rbx,4), %edx + +# CHECK: {nf} bextrq %r9, %r15, %r11 +# CHECK: encoding: [0x62,0x52,0xb4,0x0c,0xf7,0xdf] + {nf} bextrq %r9, %r15, %r11 + +# CHECK: {evex} bextrq %r9, %r15, %r11 +# CHECK: encoding: [0x62,0x52,0xb4,0x08,0xf7,0xdf] + {evex} bextrq %r9, %r15, %r11 + +# CHECK: {nf} bextrq %r9, 123(%rax,%rbx,4), %r15 +# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00] + {nf} bextrq %r9, 123(%rax,%rbx,4), %r15 + +# CHECK: {evex} bextrq %r9, 123(%rax,%rbx,4), %r15 +# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00] + {evex} bextrq %r9, 123(%rax,%rbx,4), %r15 + # CHECK: bextrl %r18d, %r22d, %r26d # CHECK: encoding: [0x62,0x6a,0x6c,0x00,0xf7,0xd6] bextrl %r18d, %r22d, %r26d diff --git a/llvm/test/MC/X86/apx/bextr-intel.s b/llvm/test/MC/X86/apx/bextr-intel.s index af70c00c1d631..7a133d6e50f34 100644 --- a/llvm/test/MC/X86/apx/bextr-intel.s +++ b/llvm/test/MC/X86/apx/bextr-intel.s @@ -1,5 +1,37 @@ # RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s +# CHECK: {nf} bextr r10d, edx, ecx +# CHECK: encoding: [0x62,0x72,0x74,0x0c,0xf7,0xd2] + {nf} bextr r10d, edx, ecx + +# CHECK: {evex} bextr r10d, edx, ecx +# CHECK: encoding: [0x62,0x72,0x74,0x08,0xf7,0xd2] + {evex} bextr r10d, edx, ecx + +# CHECK: {nf} bextr edx, dword ptr [rax + 4*rbx + 123], ecx +# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00] + {nf} bextr edx, dword ptr [rax + 4*rbx + 123], ecx + +# CHECK: {evex} bextr edx, dword ptr [rax + 4*rbx + 123], ecx +# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00] + {evex} bextr edx, dword ptr [rax + 4*rbx + 123], ecx + +# CHECK: {nf} bextr r11, r15, r9 +# CHECK: encoding: [0x62,0x52,0xb4,0x0c,0xf7,0xdf] + {nf} bextr r11, r15, r9 + +# CHECK: {evex} bextr r11, r15, r9 +# CHECK: encoding: [0x62,0x52,0xb4,0x08,0xf7,0xdf] + {evex} bextr r11, r15, r9 + +# CHECK: {nf} bextr r15, qword ptr [rax + 4*rbx + 123], r9 +# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00] + {nf} bextr r15, qword ptr [rax + 4*rbx + 123], r9 + +# CHECK: {evex} bextr r15, qword ptr [rax + 4*rbx + 123], r9 +# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00] + {evex} bextr r15, qword ptr [rax + 4*rbx + 123], r9 + # CHECK: bextr r26d, r22d, r18d # CHECK: encoding: [0x62,0x6a,0x6c,0x00,0xf7,0xd6] bextr r26d, r22d, r18d diff --git a/llvm/test/MC/X86/apx/blsi-att.s b/llvm/test/MC/X86/apx/blsi-att.s index 65b2fd2b4d09b..9a117e5c0d364 100644 --- a/llvm/test/MC/X86/apx/blsi-att.s +++ b/llvm/test/MC/X86/apx/blsi-att.s @@ -1,8 +1,40 @@ # RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s # RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR -# ERROR-COUNT-4: error: +# ERROR-COUNT-12: error: # ERROR-NOT: error: +# CHECK: {nf} blsil %ecx, %edx +# CHECK: encoding: [0x62,0xf2,0x6c,0x0c,0xf3,0xd9] + {nf} blsil %ecx, %edx + +# CHECK: {evex} blsil %ecx, %edx +# CHECK: encoding: [0x62,0xf2,0x6c,0x08,0xf3,0xd9] + {evex} blsil %ecx, %edx + +# CHECK: {nf} blsiq %r9, %r15 +# CHECK: encoding: [0x62,0xd2,0x84,0x0c,0xf3,0xd9] + {nf} blsiq %r9, %r15 + +# CHECK: {evex} blsiq %r9, %r15 +# CHECK: encoding: [0x62,0xd2,0x84,0x08,0xf3,0xd9] + {evex} blsiq %r9, %r15 + +# CHECK: {nf} blsil 123(%rax,%rbx,4), %ecx +# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00] + {nf} blsil 123(%rax,%rbx,4), %ecx + +# CHECK: {evex} blsil 123(%rax,%rbx,4), %ecx +# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00] + {evex} blsil 123(%rax,%rbx,4), %ecx + +# CHECK: {nf} blsiq 123(%rax,%rbx,4), %r9 +# CHECK: encoding: [0x62,0xf2,0xb4,0x0c,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00] + {nf} blsiq 123(%rax,%rbx,4), %r9 + +# CHECK: {evex} blsiq 123(%rax,%rbx,4), %r9 +# CHECK: encoding: [0x62,0xf2,0xb4,0x08,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00] + {evex} blsiq 123(%rax,%rbx,4), %r9 + # CHECK: blsil %r18d, %r22d # CHECK: encoding: [0x62,0xfa,0x4c,0x00,0xf3,0xda] blsil %r18d, %r22d diff --git a/llvm/test/MC/X86/apx/blsi-intel.s b/llvm/test/MC/X86/apx/blsi-intel.s index edf5711cc74b5..54a3c84caf572 100644 --- a/llvm/test/MC/X86/apx/blsi-intel.s +++ b/llvm/test/MC/X86/apx/blsi-intel.s @@ -1,5 +1,37 @@ # RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s +# CHECK: {nf} blsi edx, ecx +# CHECK: encoding: [0x62,0xf2,0x6c,0x0c,0xf3,0xd9] + {nf} blsi edx, ecx + +# CHECK: {evex} blsi edx, ecx +# CHECK: encoding: [0x62,0xf2,0x6c,0x08,0xf3,0xd9] + {evex} blsi edx, ecx + +# CHECK: {nf} blsi r15, r9 +# CHECK: encoding: [0x62,0xd2,0x84,0x0c,0xf3,0xd9] + {nf} blsi r15, r9 + +# CHECK: {evex} blsi r15, r9 +# CHECK: encoding: [0x62,0xd2,0x84,0x08,0xf3,0xd9] + {evex} blsi r15, r9 + +# CHECK: {nf} blsi ecx, dword ptr [rax + 4*rbx + 123] +# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00] + {nf} blsi ecx, dword ptr [rax + 4*rbx + 123] + +# CHECK: {evex} blsi ecx, dword ptr [rax + 4*rbx + 123] +# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00] + {evex} blsi ecx, dword ptr [rax + 4*rbx + 123] + +# CHECK: {nf} blsi r9, qword ptr [rax + 4*rbx + 123] +# CHECK: encoding: [0x62,0xf2,0xb4,0x0c,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00] + {nf} blsi r9, qword ptr [rax + 4*rbx + 123] + +# CHECK: {evex} blsi r9, qword ptr [rax + 4*rbx + 123] +# CHECK: encoding: [0x62,0xf2,0xb4,0x08,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00] + {evex} blsi r9, qword ptr [rax + 4*rbx + 123] + # CHECK: blsi r22d, r18d # CHECK: encoding: [0x62,0xfa,0x4c,0x00,0xf3,0xda] blsi r22d, r18d diff --git a/llvm/test/MC/X86/apx/blsmsk-att.s b/llvm/test/MC/X86/apx/blsmsk-att.s index 710fcabddcc3a..fcbaefcc42c8f 100644 --- a/llvm/test/MC/X86/apx/blsmsk-att.s +++ b/llvm/test/MC/X86/apx/blsmsk-att.s @@ -1,8 +1,40 @@ # RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s # RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR -# ERROR-COUNT-4: error: +# ERROR-COUNT-12: error: # ERROR-NOT: error: +# CHECK: {nf} blsmskl %ecx, %edx +# CHECK: encoding: [0x62,0xf2,0x6c,0x0c,0xf3,0xd1] + {nf} blsmskl %ecx, %edx + +# CHECK: {evex} blsmskl %ecx, %edx +# CHECK: encoding: [0x62,0xf2,0x6c,0x08,0xf3,0xd1] + {evex} blsmskl %ecx, %edx + +# CHECK: {nf} blsmskq %r9, %r15 +# CHECK: encoding: [0x62,0xd2,0x84,0x0c,0xf3,0xd1] + {nf} blsmskq %r9, %r15 + +# CHECK: {evex} blsmskq %r9, %r15 +# CHECK: encoding: [0x62,0xd2,0x84,0x08,0xf3,0xd1] + {evex} blsmskq %r9, %r15 + +# CHECK: {nf} blsmskl 123(%rax,%rbx,4), %ecx +# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf3,0x94,0x98,0x7b,0x00,0x00,0x00] + {nf} blsmskl 123(%rax,%rbx,4), %ecx + +# CHECK: {evex} blsmskl 123(%rax,%rbx,4), %ecx +# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf3,0x94,0x98,0x7b,0x00,0x00,0x00] + {evex} blsmskl 123(%rax,%rbx,4), %ecx + +# CHECK: {nf} blsmskq 123(%rax,%rbx,4), %r9 +# CHECK: encoding: [0x62,0xf2,0xb4,0x0c,0xf3,0x94,0x98,0x7b,0x00,0x00,0x00] + {nf} blsmskq 123(%rax,%rbx,4), %r9 + +# CHECK: {evex} blsmskq 123(%rax,%rbx,4), %r9 +# CHECK: encoding: [0x62,0xf2,0xb4,0x08,0xf3,0x94,0x98,0x7b,0x00,0x00,0x00] + {evex} blsmskq 123(%rax,%rbx,4), %r9 + # CHECK: blsmskl %r18d, %r22d # CHECK: encoding: [0x62,0xfa,0x4c,0x00,0xf3,0xd2] blsmskl %r18d, %r22d diff --git a/llvm/test/MC/X86/apx/blsmsk-intel.s b/llvm/test/MC/X86/apx/blsmsk-intel.s index bb8197d3d4102..168a9cfb6289e 100644 --- a/llvm/test/MC/X86/apx/blsmsk-intel.s +++ b/llvm/test/MC/X86/apx/blsmsk-intel.s @@ -1,5 +1,37 @@ # RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s +# CHECK: {nf} blsmsk edx, ecx +# CHECK: encoding: [0x62,0xf2,0x6c,0x0c,0xf3,0xd1] + {nf} blsmsk edx, ecx + +# CHECK: {evex} blsmsk edx, ecx +# CHECK: encoding: [0x62,0xf2,0x6c,0x08,0xf3,0xd1] + {evex} blsmsk edx, ecx + +# CHECK: {nf} blsmsk r15, r9 +# CHECK: encoding: [0x62,0xd2,0x84,0x0c,0xf3,0xd1] + {nf} blsmsk r15, r9 + +# CHECK: {evex} blsmsk r15, r9 +# CHECK: encoding: [0x62,0xd2,0x84,0x08,0xf3,0xd1] + {evex} blsmsk r15, r9 + +# CHECK: {nf} blsmsk ecx, dword ptr [rax + 4*rbx + 123] +# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf3,0x94,0x98,0x7b,0x00,0x00,0x00] + {nf} blsmsk ecx, dword ptr [rax + 4*rbx + 123] + +# CHECK: {evex} blsmsk ecx, dword ptr [rax + 4*rbx + 123] +# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf3,0x94,0x98,0x7b,0x00,0x00,0x00] + {evex} blsmsk ecx, dword ptr [rax + 4*rbx + 123] + +# CHECK: {nf} blsmsk r9, qword ptr [rax + 4*rbx + 123] +# CHECK: encoding: [0x62,0xf2,0xb4,0x0c,0xf3,0x94,0x98,0x7b,0x00,0x00,0x00] + {nf} blsmsk r9, qword ptr [rax + 4*rbx + 123] + +# CHECK: {evex} blsmsk r9, qword ptr [rax + 4*rbx + 123] +# CHECK: encoding: [0x62,0xf2,0xb4,0x08,0xf3,0x94,0x98,0x7b,0x00,0x00,0x00] + {evex} blsmsk r9, qword ptr [rax + 4*rbx + 123] + # CHECK: blsmsk r22d, r18d # CHECK: encoding: [0x62,0xfa,0x4c,0x00,0xf3,0xd2] blsmsk r22d, r18d diff --git a/llvm/test/MC/X86/apx/blsr-att.s b/llvm/test/MC/X86/apx/blsr-att.s index c9ca56149cf1a..40f5d4e4cf68f 100644 --- a/llvm/test/MC/X86/apx/blsr-att.s +++ b/llvm/test/MC/X86/apx/blsr-att.s @@ -1,8 +1,40 @@ # RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s # RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR -# ERROR-COUNT-4: error: +# ERROR-COUNT-12: error: # ERROR-NOT: error: +# CHECK: {nf} blsrl %ecx, %edx +# CHECK: encoding: [0x62,0xf2,0x6c,0x0c,0xf3,0xc9] + {nf} blsrl %ecx, %edx + +# CHECK: {evex} blsrl %ecx, %edx +# CHECK: encoding: [0x62,0xf2,0x6c,0x08,0xf3,0xc9] + {evex} blsrl %ecx, %edx + +# CHECK: {nf} blsrq %r9, %r15 +# CHECK: encoding: [0x62,0xd2,0x84,0x0c,0xf3,0xc9] + {nf} blsrq %r9, %r15 + +# CHECK: {evex} blsrq %r9, %r15 +# CHECK: encoding: [0x62,0xd2,0x84,0x08,0xf3,0xc9] + {evex} blsrq %r9, %r15 + +# CHECK: {nf} blsrl 123(%rax,%rbx,4), %ecx +# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00] + {nf} blsrl 123(%rax,%rbx,4), %ecx + +# CHECK: {evex} blsrl 123(%rax,%rbx,4), %ecx +# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00] + {evex} blsrl 123(%rax,%rbx,4), %ecx + +# CHECK: {nf} blsrq 123(%rax,%rbx,4), %r9 +# CHECK: encoding: [0x62,0xf2,0xb4,0x0c,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00] + {nf} blsrq 123(%rax,%rbx,4), %r9 + +# CHECK: {evex} blsrq 123(%rax,%rbx,4), %r9 +# CHECK: encoding: [0x62,0xf2,0xb4,0x08,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00] + {evex} blsrq 123(%rax,%rbx,4), %r9 + # CHECK: blsrl %r18d, %r22d # CHECK: encoding: [0x62,0xfa,0x4c,0x00,0xf3,0xca] blsrl %r18d, %r22d diff --git a/llvm/test/MC/X86/apx/blsr-intel.s b/llvm/test/MC/X86/apx/blsr-intel.s index acbfb81964614..6d6d475819ee5 100644 --- a/llvm/test/MC/X86/apx/blsr-intel.s +++ b/llvm/test/MC/X86/apx/blsr-intel.s @@ -1,5 +1,37 @@ # RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s +# CHECK: {nf} blsr edx, ecx +# CHECK: encoding: [0x62,0xf2,0x6c,0x0c,0xf3,0xc9] + {nf} blsr edx, ecx + +# CHECK: {evex} blsr edx, ecx +# CHECK: encoding: [0x62,0xf2,0x6c,0x08,0xf3,0xc9] + {evex} blsr edx, ecx + +# CHECK: {nf} blsr r15, r9 +# CHECK: encoding: [0x62,0xd2,0x84,0x0c,0xf3,0xc9] + {nf} blsr r15, r9 + +# CHECK: {evex} blsr r15, r9 +# CHECK: encoding: [0x62,0xd2,0x84,0x08,0xf3,0xc9] + {evex} blsr r15, r9 + +# CHECK: {nf} blsr ecx, dword ptr [rax + 4*rbx + 123] +# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00] + {nf} blsr ecx, dword ptr [rax + 4*rbx + 123] + +# CHECK: {evex} blsr ecx, dword ptr [rax + 4*rbx + 123] +# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00] + {evex} blsr ecx, dword ptr [rax + 4*rbx + 123] + +# CHECK: {nf} blsr r9, qword ptr [rax + 4*rbx + 123] +# CHECK: encoding: [0x62,0xf2,0xb4,0x0c,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00] + {nf} blsr r9, qword ptr [rax + 4*rbx + 123] + +# CHECK: {evex} blsr r9, qword ptr [rax + 4*rbx + 123] +# CHECK: encoding: [0x62,0xf2,0xb4,0x08,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00] + {evex} blsr r9, qword ptr [rax + 4*rbx + 123] + # CHECK: blsr r22d, r18d # CHECK: encoding: [0x62,0xfa,0x4c,0x00,0xf3,0xca] blsr r22d, r18d diff --git a/llvm/test/MC/X86/apx/bzhi-att.s b/llvm/test/MC/X86/apx/bzhi-att.s index 635cfa14e6b4f..222c91f6dea3e 100644 --- a/llvm/test/MC/X86/apx/bzhi-att.s +++ b/llvm/test/MC/X86/apx/bzhi-att.s @@ -1,8 +1,40 @@ # RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s # RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR -# ERROR-COUNT-4: error: +# ERROR-COUNT-12: error: # ERROR-NOT: error: +# CHECK: {nf} bzhil %ecx, %edx, %r10d +# CHECK: encoding: [0x62,0x72,0x74,0x0c,0xf5,0xd2] + {nf} bzhil %ecx, %edx, %r10d + +# CHECK: {evex} bzhil %ecx, %edx, %r10d +# CHECK: encoding: [0x62,0x72,0x74,0x08,0xf5,0xd2] + {evex} bzhil %ecx, %edx, %r10d + +# CHECK: {nf} bzhil %ecx, 123(%rax,%rbx,4), %edx +# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf5,0x94,0x98,0x7b,0x00,0x00,0x00] + {nf} bzhil %ecx, 123(%rax,%rbx,4), %edx + +# CHECK: {evex} bzhil %ecx, 123(%rax,%rbx,4), %edx +# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf5,0x94,0x98,0x7b,0x00,0x00,0x00] + {evex} bzhil %ecx, 123(%rax,%rbx,4), %edx + +# CHECK: {nf} bzhiq %r9, %r15, %r11 +# CHECK: encoding: [0x62,0x52,0xb4,0x0c,0xf5,0xdf] + {nf} bzhiq %r9, %r15, %r11 + +# CHECK: {evex} bzhiq %r9, %r15, %r11 +# CHECK: encoding: [0x62,0x52,0xb4,0x08,0xf5,0xdf] + {evex} bzhiq %r9, %r15, %r11 + +# CHECK: {nf} bzhiq %r9, 123(%rax,%rbx,4), %r15 +# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf5,0xbc,0x98,0x7b,0x00,0x00,0x00] + {nf} bzhiq %r9, 123(%rax,%rbx,4), %r15 + +# CHECK: {evex} bzhiq %r9, 123(%rax,%rbx,4), %r15 +# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf5,0xbc,0x98,0x7b,0x00,0x00,0x00] + {evex} bzhiq %r9, 123(%rax,%rbx,4), %r15 + # CHECK: bzhil %r18d, %r22d, %r26d # CHECK: encoding: [0x62,0x6a,0x6c,0x00,0xf5,0xd6] bzhil %r18d, %r22d, %r26d diff --git a/llvm/test/MC/X86/apx/bzhi-intel.s b/llvm/test/MC/X86/apx/bzhi-intel.s index f7ab72dd717ee..a45625a6fb7f0 100644 --- a/llvm/test/MC/X86/apx/bzhi-intel.s +++ b/llvm/test/MC/X86/apx/bzhi-intel.s @@ -1,5 +1,37 @@ # RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s +# CHECK: {nf} bzhi r10d, edx, ecx +# CHECK: encoding: [0x62,0x72,0x74,0x0c,0xf5,0xd2] + {nf} bzhi r10d, edx, ecx + +# CHECK: {evex} bzhi r10d, edx, ecx +# CHECK: encoding: [0x62,0x72,0x74,0x08,0xf5,0xd2] + {evex} bzhi r10d, edx, ecx + +# CHECK: {nf} bzhi edx, dword ptr [rax + 4*rbx + 123], ecx +# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf5,0x94,0x98,0x7b,0x00,0x00,0x00] + {nf} bzhi edx, dword ptr [rax + 4*rbx + 123], ecx + +# CHECK: {evex} bzhi edx, dword ptr [rax + 4*rbx + 123], ecx +# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf5,0x94,0x98,0x7b,0x00,0x00,0x00] + {evex} bzhi edx, dword ptr [rax + 4*rbx + 123], ecx + +# CHECK: {nf} bzhi r11, r15, r9 +# CHECK: encoding: [0x62,0x52,0xb4,0x0c,0xf5,0xdf] + {nf} bzhi r11, r15, r9 + +# CHECK: {evex} bzhi r11, r15, r9 +# CHECK: encoding: [0x62,0x52,0xb4,0x08,0xf5,0xdf] + {evex} bzhi r11, r15, r9 + +# CHECK: {nf} bzhi r15, qword ptr [rax + 4*rbx + 123], r9 +# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf5,0xbc,0x98,0x7b,0x00,0x00,0x00] + {nf} bzhi r15, qword ptr [rax + 4*rbx + 123], r9 + +# CHECK: {evex} bzhi r15, qword ptr [rax + 4*rbx + 123], r9 +# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf5,0xbc,0x98,0x7b,0x00,0x00,0x00] + {evex} bzhi r15, qword ptr [rax + 4*rbx + 123], r9 + # CHECK: bzhi r26d, r22d, r18d # CHECK: encoding: [0x62,0x6a,0x6c,0x00,0xf5,0xd6] bzhi r26d, r22d, r18d diff --git a/llvm/test/TableGen/x86-fold-tables.inc b/llvm/test/TableGen/x86-fold-tables.inc index 02e4ae52cc914..a75e433011c2f 100644 --- a/llvm/test/TableGen/x86-fold-tables.inc +++ b/llvm/test/TableGen/x86-fold-tables.inc @@ -550,8 +550,10 @@ static const X86FoldTableEntry Table1[] = { {X86::AND8rr_NF_ND, X86::AND8mr_NF_ND, 0}, {X86::BEXTR32rr, X86::BEXTR32rm, 0}, {X86::BEXTR32rr_EVEX, X86::BEXTR32rm_EVEX, 0}, + {X86::BEXTR32rr_NF, X86::BEXTR32rm_NF, 0}, {X86::BEXTR64rr, X86::BEXTR64rm, 0}, {X86::BEXTR64rr_EVEX, X86::BEXTR64rm_EVEX, 0}, + {X86::BEXTR64rr_NF, X86::BEXTR64rm_NF, 0}, {X86::BEXTRI32ri, X86::BEXTRI32mi, 0}, {X86::BEXTRI64ri, X86::BEXTRI64mi, 0}, {X86::BLCFILL32rr, X86::BLCFILL32rm, 0}, @@ -568,18 +570,24 @@ static const X86FoldTableEntry Table1[] = { {X86::BLSFILL64rr, X86::BLSFILL64rm, 0}, {X86::BLSI32rr, X86::BLSI32rm, 0}, {X86::BLSI32rr_EVEX, X86::BLSI32rm_EVEX, 0}, + {X86::BLSI32rr_NF, X86::BLSI32rm_NF, 0}, {X86::BLSI64rr, X86::BLSI64rm, 0}, {X86::BLSI64rr_EVEX, X86::BLSI64rm_EVEX, 0}, + {X86::BLSI64rr_NF, X86::BLSI64rm_NF, 0}, {X86::BLSIC32rr, X86::BLSIC32rm, 0}, {X86::BLSIC64rr, X86::BLSIC64rm, 0}, {X86::BLSMSK32rr, X86::BLSMSK32rm, 0}, {X86::BLSMSK32rr_EVEX, X86::BLSMSK32rm_EVEX, 0}, + {X86::BLSMSK32rr_NF, X86::BLSMSK32rm_NF, 0}, {X86::BLSMSK64rr, X86::BLSMSK64rm, 0}, {X86::BLSMSK64rr_EVEX, X86::BLSMSK64rm_EVEX, 0}, + {X86::BLSMSK64rr_NF, X86::BLSMSK64rm_NF, 0}, {X86::BLSR32rr, X86::BLSR32rm, 0}, {X86::BLSR32rr_EVEX, X86::BLSR32rm_EVEX, 0}, + {X86::BLSR32rr_NF, X86::BLSR32rm_NF, 0}, {X86::BLSR64rr, X86::BLSR64rm, 0}, {X86::BLSR64rr_EVEX, X86::BLSR64rm_EVEX, 0}, + {X86::BLSR64rr_NF, X86::BLSR64rm_NF, 0}, {X86::BSF16rr, X86::BSF16rm, 0}, {X86::BSF32rr, X86::BSF32rm, 0}, {X86::BSF64rr, X86::BSF64rm, 0}, @@ -588,8 +596,10 @@ static const X86FoldTableEntry Table1[] = { {X86::BSR64rr, X86::BSR64rm, 0}, {X86::BZHI32rr, X86::BZHI32rm, 0}, {X86::BZHI32rr_EVEX, X86::BZHI32rm_EVEX, 0}, + {X86::BZHI32rr_NF, X86::BZHI32rm_NF, 0}, {X86::BZHI64rr, X86::BZHI64rm, 0}, {X86::BZHI64rr_EVEX, X86::BZHI64rm_EVEX, 0}, + {X86::BZHI64rr_NF, X86::BZHI64rm_NF, 0}, {X86::CMP16rr, X86::CMP16rm, 0}, {X86::CMP32rr, X86::CMP32rm, 0}, {X86::CMP64rr, X86::CMP64rm, 0}, @@ -1636,8 +1646,10 @@ static const X86FoldTableEntry Table2[] = { {X86::AND8rr_NF_ND, X86::AND8rm_NF_ND, 0}, {X86::ANDN32rr, X86::ANDN32rm, 0}, {X86::ANDN32rr_EVEX, X86::ANDN32rm_EVEX, 0}, + {X86::ANDN32rr_NF, X86::ANDN32rm_NF, 0}, {X86::ANDN64rr, X86::ANDN64rm, 0}, {X86::ANDN64rr_EVEX, X86::ANDN64rm_EVEX, 0}, + {X86::ANDN64rr_NF, X86::ANDN64rm_NF, 0}, {X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16}, {X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16}, {X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16}, From c497c37244f6dce4dbc5fc2424d8fa47fd5cf1fb Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Tue, 2 Jan 2024 18:45:49 -0800 Subject: [PATCH 03/12] clang format --- .../X86/Disassembler/X86Disassembler.cpp | 22 +++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp index e6697e98faaa9..12a4cc7e97544 100644 --- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -1134,18 +1134,18 @@ static int getInstructionIDWithAttrMask(uint16_t *instructionID, return 0; } -static bool isNFnotMap4(InternalInstruction *insn){ -// Promoted BMI instrs below has nf version. -if (insn->opcodeType == THREEBYTE_38 && - ppFromXOP3of3(insn->vectorExtensionPrefix[2]) == VEX_PREFIX_NONE) { - switch (insn->opcode) { - case 0xf2: // ANDN - case 0xf3: // BLSI, BLSR, BLSMSK - case 0xf5: // BZHI - case 0xf7: // BEXTR - return true; +static bool isNFnotMap4(InternalInstruction *insn) { + // Promoted BMI instrs below has nf version. + if (insn->opcodeType == THREEBYTE_38 && + ppFromXOP3of3(insn->vectorExtensionPrefix[2]) == VEX_PREFIX_NONE) { + switch (insn->opcode) { + case 0xf2: // ANDN + case 0xf3: // BLSI, BLSR, BLSMSK + case 0xf5: // BZHI + case 0xf7: // BEXTR + return true; + } } -} return false; } From bdccead8ef6cbbf3c0b7aed662122920e653a8c1 Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Tue, 2 Jan 2024 22:25:59 -0800 Subject: [PATCH 04/12] Fix function name --- llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp index 12a4cc7e97544..6bf5f714d3895 100644 --- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -1137,7 +1137,7 @@ static int getInstructionIDWithAttrMask(uint16_t *instructionID, static bool isNFnotMap4(InternalInstruction *insn) { // Promoted BMI instrs below has nf version. if (insn->opcodeType == THREEBYTE_38 && - ppFromXOP3of3(insn->vectorExtensionPrefix[2]) == VEX_PREFIX_NONE) { + ppFromEVEX3of4(insn->vectorExtensionPrefix[2]) == VEX_PREFIX_NONE) { switch (insn->opcode) { case 0xf2: // ANDN case 0xf3: // BLSI, BLSR, BLSMSK From dfbfa9214fdf16f84d0fd9b6eb6d5eff820cb249 Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Wed, 3 Jan 2024 00:27:36 -0800 Subject: [PATCH 05/12] resolve comments --- llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp | 12 +++++++----- llvm/lib/Target/X86/X86InstrArithmetic.td | 4 ++-- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp index 6bf5f714d3895..911d4a69671d8 100644 --- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -1134,8 +1134,12 @@ static int getInstructionIDWithAttrMask(uint16_t *instructionID, return 0; } -static bool isNFnotMap4(InternalInstruction *insn) { - // Promoted BMI instrs below has nf version. +static bool isNF(InternalInstruction *insn) { + // NF bit is the MSB of aaa. + if (nfFromEVEX4of4(insn->vectorExtensionPrefix[3]) && + insn->opcodeType == MAP4) + return true; + // Promoted BMI instrs below has nf version but not in map4. if (insn->opcodeType == THREEBYTE_38 && ppFromEVEX3of4(insn->vectorExtensionPrefix[2]) == VEX_PREFIX_NONE) { switch (insn->opcode) { @@ -1184,9 +1188,7 @@ static int getInstructionID(struct InternalInstruction *insn, attrMask |= ATTR_EVEXKZ; if (bFromEVEX4of4(insn->vectorExtensionPrefix[3])) attrMask |= ATTR_EVEXB; - // nf bit is the MSB of aaa - if (nfFromEVEX4of4(insn->vectorExtensionPrefix[3]) && - (insn->opcodeType == MAP4 || isNFnotMap4(insn))) + if (isNF(insn)) attrMask |= ATTR_EVEXNF; else if (aaaFromEVEX4of4(insn->vectorExtensionPrefix[3])) attrMask |= ATTR_EVEXK; diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td index 7fe18f1ab0e9e..dab350ed84d7a 100644 --- a/llvm/lib/Target/X86/X86InstrArithmetic.td +++ b/llvm/lib/Target/X86/X86InstrArithmetic.td @@ -1337,8 +1337,8 @@ defm ANDN64 : AndN, VEX, REX_W, Requires<[HasBMI, NoEGPR]>; defm ANDN32 : AndN, EVEX, Requires<[HasBMI, HasEGPR, In64BitMode]>; defm ANDN64 : AndN, EVEX, REX_W, Requires<[HasBMI, HasEGPR, In64BitMode]>; let Pattern = [(null_frag)] in { -defm ANDN32 : AndN, EVEX, EVEX_NF, Requires<[In64BitMode]>; -defm ANDN64 : AndN, EVEX, EVEX_NF, REX_W, Requires<[In64BitMode]>; + defm ANDN32 : AndN, EVEX, EVEX_NF, Requires<[In64BitMode]>; + defm ANDN64 : AndN, EVEX, EVEX_NF, REX_W, Requires<[In64BitMode]>; } } From eb2a79976495dcc14dcdbf757ba7363ea476a38c Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Wed, 3 Jan 2024 02:37:44 -0800 Subject: [PATCH 06/12] resolve comment --- llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp | 12 +++++++----- llvm/lib/Target/X86/X86InstrArithmetic.td | 6 +++--- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp index 911d4a69671d8..ce7f707066bb0 100644 --- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -1135,11 +1135,11 @@ static int getInstructionIDWithAttrMask(uint16_t *instructionID, } static bool isNF(InternalInstruction *insn) { - // NF bit is the MSB of aaa. - if (nfFromEVEX4of4(insn->vectorExtensionPrefix[3]) && - insn->opcodeType == MAP4) + if (!nfFromEVEX4of4(insn->vectorExtensionPrefix[3])) + return false; + if (insn->opcodeType == MAP4) return true; - // Promoted BMI instrs below has nf version but not in map4. + // Below NF instructions are not in map4. if (insn->opcodeType == THREEBYTE_38 && ppFromEVEX3of4(insn->vectorExtensionPrefix[2]) == VEX_PREFIX_NONE) { switch (insn->opcode) { @@ -1148,6 +1148,8 @@ static bool isNF(InternalInstruction *insn) { case 0xf5: // BZHI case 0xf7: // BEXTR return true; + default: + break; } } return false; @@ -1188,7 +1190,7 @@ static int getInstructionID(struct InternalInstruction *insn, attrMask |= ATTR_EVEXKZ; if (bFromEVEX4of4(insn->vectorExtensionPrefix[3])) attrMask |= ATTR_EVEXB; - if (isNF(insn)) + if (isNF(insn)) // NF bit is the MSB of aaa. attrMask |= ATTR_EVEXNF; else if (aaaFromEVEX4of4(insn->vectorExtensionPrefix[3])) attrMask |= ATTR_EVEXK; diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td index dab350ed84d7a..9ed8d6281f08b 100644 --- a/llvm/lib/Target/X86/X86InstrArithmetic.td +++ b/llvm/lib/Target/X86/X86InstrArithmetic.td @@ -1312,7 +1312,7 @@ def : Pat<(X86testpat (loadi64 addr:$src1), i64relocImmSExt32_su:$src2), //===----------------------------------------------------------------------===// // ANDN Instruction // -multiclass AndN { +multiclass AndN { defvar andn_rr_p = [(set t.RegClass:$dst, EFLAGS, (X86and_flag (not t.RegClass:$src1), t.RegClass:$src2))]; @@ -1332,8 +1332,8 @@ multiclass AndN { // Complexity is reduced to give and with immediate a chance to match first. let AddedComplexity = -6 in { -defm ANDN32 : AndN, VEX, Requires<[HasBMI, NoEGPR]>; -defm ANDN64 : AndN, VEX, REX_W, Requires<[HasBMI, NoEGPR]>; +defm ANDN32 : AndN, VEX, Requires<[HasBMI, NoEGPR]>; +defm ANDN64 : AndN, VEX, REX_W, Requires<[HasBMI, NoEGPR]>; defm ANDN32 : AndN, EVEX, Requires<[HasBMI, HasEGPR, In64BitMode]>; defm ANDN64 : AndN, EVEX, REX_W, Requires<[HasBMI, HasEGPR, In64BitMode]>; let Pattern = [(null_frag)] in { From a7493631cf99bc975a7b280acc235c1cfc020649 Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Thu, 4 Jan 2024 01:36:54 -0800 Subject: [PATCH 07/12] resolve comments --- llvm/lib/Target/X86/X86InstrMisc.td | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td index 9aa487bb36cde..66fac2369d0a9 100644 --- a/llvm/lib/Target/X86/X86InstrMisc.td +++ b/llvm/lib/Target/X86/X86InstrMisc.td @@ -1223,7 +1223,7 @@ multiclass Bls, T8, VVVV; } -let Predicates = [HasBMI], Defs = [EFLAGS] in { +let Defs = [EFLAGS] in { defm BLSR32 : Bls<"blsr", MRM1r, MRM1m, Xi32>, VEX; defm BLSR64 : Bls<"blsr", MRM1r, MRM1m, Xi64>, VEX; defm BLSMSK32 : Bls<"blsmsk", MRM2r, MRM2m, Xi32>, VEX; @@ -1232,7 +1232,7 @@ let Predicates = [HasBMI], Defs = [EFLAGS] in { defm BLSI64 : Bls<"blsi", MRM3r, MRM3m, Xi64>, VEX; } -let Predicates = [HasBMI, In64BitMode], Defs = [EFLAGS] in { +let Predicates = [In64BitMode], Defs = [EFLAGS] in { defm BLSR32 : Bls<"blsr", MRM1r, MRM1m, Xi32, "_EVEX">, EVEX; defm BLSR64 : Bls<"blsr", MRM1r, MRM1m, Xi64, "_EVEX">, EVEX; defm BLSMSK32 : Bls<"blsmsk", MRM2r, MRM2m, Xi32, "_EVEX">, EVEX; @@ -1324,11 +1324,11 @@ let Predicates = [HasBMI2, HasEGPR, In64BitMode], Defs = [EFLAGS] in { defm BZHI64 : Bmi4VOp3<0xF5, "bzhi", Xi64, X86bzhi, WriteBZHI, "_EVEX">, EVEX; } -let Predicates = [In64BitMode], Pattern = [(null_frag)] in { - defm BEXTR32 : Bmi4VOp3<0xF7, "bextr", Xi32, X86bextr, WriteBEXTR, "_NF">, EVEX, EVEX_NF; - defm BEXTR64 : Bmi4VOp3<0xF7, "bextr", Xi64, X86bextr, WriteBEXTR, "_NF">, EVEX, EVEX_NF; - defm BZHI32 : Bmi4VOp3<0xF5, "bzhi", Xi32, X86bzhi, WriteBZHI, "_NF">, EVEX, EVEX_NF; - defm BZHI64 : Bmi4VOp3<0xF5, "bzhi", Xi64, X86bzhi, WriteBZHI, "_NF">, EVEX, EVEX_NF; +let Predicates = [In64BitMode] in { + defm BEXTR32 : Bmi4VOp3<0xF7, "bextr", Xi32, null_frag, WriteBEXTR, "_NF">, EVEX, EVEX_NF; + defm BEXTR64 : Bmi4VOp3<0xF7, "bextr", Xi64, null_frag, WriteBEXTR, "_NF">, EVEX, EVEX_NF; + defm BZHI32 : Bmi4VOp3<0xF5, "bzhi", Xi32, null_frag, WriteBZHI, "_NF">, EVEX, EVEX_NF; + defm BZHI64 : Bmi4VOp3<0xF5, "bzhi", Xi64, null_frag, WriteBZHI, "_NF">, EVEX, EVEX_NF; } def CountTrailingOnes : SDNodeXForm Date: Thu, 11 Jan 2024 00:15:39 -0800 Subject: [PATCH 08/12] add NoCD8 --- llvm/lib/Target/X86/X86InstrArithmetic.td | 12 ++--- llvm/lib/Target/X86/X86InstrMisc.td | 4 +- llvm/test/MC/Disassembler/X86/apx/bextr.txt | 49 ++++++++++----------- llvm/test/MC/Disassembler/X86/apx/bzhi.txt | 10 +++-- llvm/test/MC/X86/apx/bextr-att.s | 8 ++-- llvm/test/MC/X86/apx/bextr-intel.s | 8 ++-- llvm/test/MC/X86/apx/bzhi-att.s | 8 ++-- llvm/test/MC/X86/apx/bzhi-intel.s | 8 ++-- 8 files changed, 55 insertions(+), 52 deletions(-) diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td index 9ed8d6281f08b..757872132368f 100644 --- a/llvm/lib/Target/X86/X86InstrArithmetic.td +++ b/llvm/lib/Target/X86/X86InstrArithmetic.td @@ -1322,20 +1322,20 @@ multiclass AndN { def rr#suffix : ITy<0xF2, MRMSrcReg, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, t.RegClass:$src2), "andn", binop_ndd_args, andn_rr_p>, VVVV, Sched<[WriteALU]>, - T8, DefEFLAGS; + T8; def rm#suffix : ITy<0xF2, MRMSrcMem, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, t.MemOperand:$src2), "andn", binop_ndd_args, andn_rm_p>, VVVV, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>, - T8, DefEFLAGS; + T8; } // Complexity is reduced to give and with immediate a chance to match first. let AddedComplexity = -6 in { -defm ANDN32 : AndN, VEX, Requires<[HasBMI, NoEGPR]>; -defm ANDN64 : AndN, VEX, REX_W, Requires<[HasBMI, NoEGPR]>; -defm ANDN32 : AndN, EVEX, Requires<[HasBMI, HasEGPR, In64BitMode]>; -defm ANDN64 : AndN, EVEX, REX_W, Requires<[HasBMI, HasEGPR, In64BitMode]>; +defm ANDN32 : AndN, VEX, Requires<[HasBMI, NoEGPR]>, DefEFLAGS; +defm ANDN64 : AndN, VEX, REX_W, Requires<[HasBMI, NoEGPR]>, DefEFLAGS; +defm ANDN32 : AndN, EVEX, Requires<[HasBMI, HasEGPR, In64BitMode]>, DefEFLAGS; +defm ANDN64 : AndN, EVEX, REX_W, Requires<[HasBMI, HasEGPR, In64BitMode]>, DefEFLAGS; let Pattern = [(null_frag)] in { defm ANDN32 : AndN, EVEX, EVEX_NF, Requires<[In64BitMode]>; defm ANDN64 : AndN, EVEX, EVEX_NF, REX_W, Requires<[In64BitMode]>; diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td index 66fac2369d0a9..bcc7c47fb941f 100644 --- a/llvm/lib/Target/X86/X86InstrMisc.td +++ b/llvm/lib/Target/X86/X86InstrMisc.td @@ -1298,13 +1298,13 @@ multiclass Bmi4VOp3 o, string m, X86TypeInfo t, SDPatternOperator node, let SchedRW = [sched], Form = MRMSrcReg4VOp3 in def rr#Suffix : BinOpRR, T8; + (node t.RegClass:$src1, t.RegClass:$src2))]>, T8, NoCD8; let SchedRW = [sched.Folded, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault, sched.ReadAfterFold], Form = MRMSrcMem4VOp3 in def rm#Suffix : BinOpMR, T8; + t.RegClass:$src2))]>, T8, NoCD8; } let Predicates = [HasBMI, NoEGPR], Defs = [EFLAGS] in { diff --git a/llvm/test/MC/Disassembler/X86/apx/bextr.txt b/llvm/test/MC/Disassembler/X86/apx/bextr.txt index e5dfbbbdd5fa1..c001e00bd6d6f 100644 --- a/llvm/test/MC/Disassembler/X86/apx/bextr.txt +++ b/llvm/test/MC/Disassembler/X86/apx/bextr.txt @@ -1,38 +1,37 @@ # RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT # RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL -# CHECK: {nf} bextr r10d, edx, ecx -# CHECK: encoding: [0x62,0x72,0x74,0x0c,0xf7,0xd2] - {nf} bextr r10d, edx, ecx +# ATT: {nf} bextrl %ecx, %edx, %r10d +# INTEL: {nf} bextr r10d, edx, ecx +0x62,0x72,0x74,0x0c,0xf7,0xd2 -# CHECK: bextr r10d, edx, ecx -# CHECK: encoding: [0x62,0x72,0x74,0x08,0xf7,0xd2] - bextr r10d, edx, ecx +# ATT: bextrl %ecx, %edx, %r10d +# INTEL: bextr r10d, edx, ecx +0x62,0x72,0x74,0x08,0xf7,0xd2 -# CHECK: {nf} bextr edx, dword ptr [rax + 4*rbx + 123], ecx -# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00] - {nf} bextr edx, dword ptr [rax + 4*rbx + 123], ecx +# ATT: {nf} bextrl %ecx, 123(%rax,%rbx,4), %edx +# INTEL: {nf} bextr edx, dword ptr [rax + 4*rbx + 123], ecx +0x62,0xf2,0x74,0x0c,0xf7,0x54,0x98,0x7b -# CHECK: bextr edx, dword ptr [rax + 4*rbx + 123], ecx -# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00] - bextr edx, dword ptr [rax + 4*rbx + 123], ecx +# ATT: bextrl %ecx, 123(%rax,%rbx,4), %edx +# INTEL: bextr edx, dword ptr [rax + 4*rbx + 123], ecx +0x62,0xf2,0x74,0x08,0xf7,0x54,0x98,0x7b -# CHECK: {nf} bextr r11, r15, r9 -# CHECK: encoding: [0x62,0x52,0xb4,0x0c,0xf7,0xdf] - {nf} bextr r11, r15, r9 +# ATT: {nf} bextrq %r9, %r15, %r11 +# INTEL: {nf} bextr r11, r15, r9 +0x62,0x52,0xb4,0x0c,0xf7,0xdf -# CHECK: bextr r11, r15, r9 -# CHECK: encoding: [0x62,0x52,0xb4,0x08,0xf7,0xdf] - bextr r11, r15, r9 +# ATT: bextrq %r9, %r15, %r11 +# INTEL: bextr r11, r15, r9 +0x62,0x52,0xb4,0x08,0xf7,0xdf -# CHECK: {nf} bextr r15, qword ptr [rax + 4*rbx + 123], r9 -# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00] - {nf} bextr r15, qword ptr [rax + 4*rbx + 123], r9 - -# CHECK: bextr r15, qword ptr [rax + 4*rbx + 123], r9 -# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00] - bextr r15, qword ptr [rax + 4*rbx + 123], r9 +# ATT: {nf} bextrq %r9, 123(%rax,%rbx,4), %r15 +# INTEL: {nf} bextr r15, qword ptr [rax + 4*rbx + 123], r9 +0x62,0x72,0xb4,0x0c,0xf7,0x7c,0x98,0x7b +# ATT: bextrq %r9, 123(%rax,%rbx,4), %r15 +# INTEL: bextr r15, qword ptr [rax + 4*rbx + 123], r9 +0x62,0x72,0xb4,0x08,0xf7,0x7c,0x98,0x7b # ATT: bextrl %r18d, %r22d, %r26d # INTEL: bextr r26d, r22d, r18d diff --git a/llvm/test/MC/Disassembler/X86/apx/bzhi.txt b/llvm/test/MC/Disassembler/X86/apx/bzhi.txt index 8eec590b04878..a8d6c666c7af3 100644 --- a/llvm/test/MC/Disassembler/X86/apx/bzhi.txt +++ b/llvm/test/MC/Disassembler/X86/apx/bzhi.txt @@ -11,11 +11,11 @@ # ATT: {nf} bzhil %ecx, 123(%rax,%rbx,4), %edx # INTEL: {nf} bzhi edx, dword ptr [rax + 4*rbx + 123], ecx -0x62,0xf2,0x74,0x0c,0xf5,0x94,0x98,0x7b,0x00,0x00,0x00 +0x62,0xf2,0x74,0x0c,0xf5,0x54,0x98,0x7b # ATT: bzhil %ecx, 123(%rax,%rbx,4), %edx # INTEL: bzhi edx, dword ptr [rax + 4*rbx + 123], ecx -0x62,0xf2,0x74,0x08,0xf5,0x94,0x98,0x7b,0x00,0x00,0x00 +0x62,0xf2,0x74,0x08,0xf5,0x54,0x98,0x7b # ATT: {nf} bzhiq %r9, %r15, %r11 # INTEL: {nf} bzhi r11, r15, r9 @@ -27,7 +27,11 @@ # ATT: {nf} bzhiq %r9, 123(%rax,%rbx,4), %r15 # INTEL: {nf} bzhi r15, qword ptr [rax + 4*rbx + 123], r9 -0x62,0x72,0xb4,0x0c,0xf5,0xbc,0x98,0x7b,0x00,0x00,0x00 +0x62,0x72,0xb4,0x0c,0xf5,0x7c,0x98,0x7b + +# ATT: bzhiq %r9, 123(%rax,%rbx,4), %r15 +# INTEL: bzhi r15, qword ptr [rax + 4*rbx + 123], r9 +0x62,0x72,0xb4,0x08,0xf5,0x7c,0x98,0x7b # ATT: bzhiq %r9, 123(%rax,%rbx,4), %r15 # INTEL: bzhi r15, qword ptr [rax + 4*rbx + 123], r9 diff --git a/llvm/test/MC/X86/apx/bextr-att.s b/llvm/test/MC/X86/apx/bextr-att.s index 57f5d3e1c2b44..acb8c8fb83af7 100644 --- a/llvm/test/MC/X86/apx/bextr-att.s +++ b/llvm/test/MC/X86/apx/bextr-att.s @@ -12,11 +12,11 @@ {evex} bextrl %ecx, %edx, %r10d # CHECK: {nf} bextrl %ecx, 123(%rax,%rbx,4), %edx -# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf7,0x54,0x98,0x7b] {nf} bextrl %ecx, 123(%rax,%rbx,4), %edx # CHECK: {evex} bextrl %ecx, 123(%rax,%rbx,4), %edx -# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf7,0x54,0x98,0x7b] {evex} bextrl %ecx, 123(%rax,%rbx,4), %edx # CHECK: {nf} bextrq %r9, %r15, %r11 @@ -28,11 +28,11 @@ {evex} bextrq %r9, %r15, %r11 # CHECK: {nf} bextrq %r9, 123(%rax,%rbx,4), %r15 -# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf7,0x7c,0x98,0x7b] {nf} bextrq %r9, 123(%rax,%rbx,4), %r15 # CHECK: {evex} bextrq %r9, 123(%rax,%rbx,4), %r15 -# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf7,0x7c,0x98,0x7b] {evex} bextrq %r9, 123(%rax,%rbx,4), %r15 # CHECK: bextrl %r18d, %r22d, %r26d diff --git a/llvm/test/MC/X86/apx/bextr-intel.s b/llvm/test/MC/X86/apx/bextr-intel.s index 7a133d6e50f34..a78e08aa463bd 100644 --- a/llvm/test/MC/X86/apx/bextr-intel.s +++ b/llvm/test/MC/X86/apx/bextr-intel.s @@ -9,11 +9,11 @@ {evex} bextr r10d, edx, ecx # CHECK: {nf} bextr edx, dword ptr [rax + 4*rbx + 123], ecx -# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf7,0x54,0x98,0x7b] {nf} bextr edx, dword ptr [rax + 4*rbx + 123], ecx # CHECK: {evex} bextr edx, dword ptr [rax + 4*rbx + 123], ecx -# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf7,0x54,0x98,0x7b] {evex} bextr edx, dword ptr [rax + 4*rbx + 123], ecx # CHECK: {nf} bextr r11, r15, r9 @@ -25,11 +25,11 @@ {evex} bextr r11, r15, r9 # CHECK: {nf} bextr r15, qword ptr [rax + 4*rbx + 123], r9 -# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf7,0x7c,0x98,0x7b] {nf} bextr r15, qword ptr [rax + 4*rbx + 123], r9 # CHECK: {evex} bextr r15, qword ptr [rax + 4*rbx + 123], r9 -# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf7,0x7c,0x98,0x7b] {evex} bextr r15, qword ptr [rax + 4*rbx + 123], r9 # CHECK: bextr r26d, r22d, r18d diff --git a/llvm/test/MC/X86/apx/bzhi-att.s b/llvm/test/MC/X86/apx/bzhi-att.s index 222c91f6dea3e..891abaaeafdb1 100644 --- a/llvm/test/MC/X86/apx/bzhi-att.s +++ b/llvm/test/MC/X86/apx/bzhi-att.s @@ -12,11 +12,11 @@ {evex} bzhil %ecx, %edx, %r10d # CHECK: {nf} bzhil %ecx, 123(%rax,%rbx,4), %edx -# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf5,0x94,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf5,0x54,0x98,0x7b] {nf} bzhil %ecx, 123(%rax,%rbx,4), %edx # CHECK: {evex} bzhil %ecx, 123(%rax,%rbx,4), %edx -# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf5,0x94,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf5,0x54,0x98,0x7b] {evex} bzhil %ecx, 123(%rax,%rbx,4), %edx # CHECK: {nf} bzhiq %r9, %r15, %r11 @@ -28,11 +28,11 @@ {evex} bzhiq %r9, %r15, %r11 # CHECK: {nf} bzhiq %r9, 123(%rax,%rbx,4), %r15 -# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf5,0xbc,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf5,0x7c,0x98,0x7b] {nf} bzhiq %r9, 123(%rax,%rbx,4), %r15 # CHECK: {evex} bzhiq %r9, 123(%rax,%rbx,4), %r15 -# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf5,0xbc,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf5,0x7c,0x98,0x7b] {evex} bzhiq %r9, 123(%rax,%rbx,4), %r15 # CHECK: bzhil %r18d, %r22d, %r26d diff --git a/llvm/test/MC/X86/apx/bzhi-intel.s b/llvm/test/MC/X86/apx/bzhi-intel.s index a45625a6fb7f0..d9a6c7adaee49 100644 --- a/llvm/test/MC/X86/apx/bzhi-intel.s +++ b/llvm/test/MC/X86/apx/bzhi-intel.s @@ -9,11 +9,11 @@ {evex} bzhi r10d, edx, ecx # CHECK: {nf} bzhi edx, dword ptr [rax + 4*rbx + 123], ecx -# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf5,0x94,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf5,0x54,0x98,0x7b] {nf} bzhi edx, dword ptr [rax + 4*rbx + 123], ecx # CHECK: {evex} bzhi edx, dword ptr [rax + 4*rbx + 123], ecx -# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf5,0x94,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf5,0x54,0x98,0x7b] {evex} bzhi edx, dword ptr [rax + 4*rbx + 123], ecx # CHECK: {nf} bzhi r11, r15, r9 @@ -25,11 +25,11 @@ {evex} bzhi r11, r15, r9 # CHECK: {nf} bzhi r15, qword ptr [rax + 4*rbx + 123], r9 -# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf5,0xbc,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf5,0x7c,0x98,0x7b] {nf} bzhi r15, qword ptr [rax + 4*rbx + 123], r9 # CHECK: {evex} bzhi r15, qword ptr [rax + 4*rbx + 123], r9 -# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf5,0xbc,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf5,0x7c,0x98,0x7b] {evex} bzhi r15, qword ptr [rax + 4*rbx + 123], r9 # CHECK: bzhi r26d, r22d, r18d From 19eb5f0748e6728ad4dda3f4d9e3cbbbf33d4305 Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Thu, 11 Jan 2024 22:41:15 -0800 Subject: [PATCH 09/12] resolve comments --- llvm/lib/Target/X86/X86InstrArithmetic.td | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td index 757872132368f..ae0bc00aacfdb 100644 --- a/llvm/lib/Target/X86/X86InstrArithmetic.td +++ b/llvm/lib/Target/X86/X86InstrArithmetic.td @@ -1312,12 +1312,12 @@ def : Pat<(X86testpat (loadi64 addr:$src1), i64relocImmSExt32_su:$src2), //===----------------------------------------------------------------------===// // ANDN Instruction // -multiclass AndN { +multiclass AndN { defvar andn_rr_p = - [(set t.RegClass:$dst, EFLAGS, (X86and_flag (not t.RegClass:$src1), + [(set t.RegClass:$dst, EFLAGS, (node (not t.RegClass:$src1), t.RegClass:$src2))]; defvar andn_rm_p = - [(set t.RegClass:$dst, EFLAGS, (X86and_flag (not t.RegClass:$src1), + [(set t.RegClass:$dst, EFLAGS, (node (not t.RegClass:$src1), (t.LoadNode addr:$src2)))]; def rr#suffix : ITy<0xF2, MRMSrcReg, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, t.RegClass:$src2), "andn", @@ -1332,14 +1332,12 @@ multiclass AndN { // Complexity is reduced to give and with immediate a chance to match first. let AddedComplexity = -6 in { -defm ANDN32 : AndN, VEX, Requires<[HasBMI, NoEGPR]>, DefEFLAGS; -defm ANDN64 : AndN, VEX, REX_W, Requires<[HasBMI, NoEGPR]>, DefEFLAGS; -defm ANDN32 : AndN, EVEX, Requires<[HasBMI, HasEGPR, In64BitMode]>, DefEFLAGS; -defm ANDN64 : AndN, EVEX, REX_W, Requires<[HasBMI, HasEGPR, In64BitMode]>, DefEFLAGS; -let Pattern = [(null_frag)] in { - defm ANDN32 : AndN, EVEX, EVEX_NF, Requires<[In64BitMode]>; - defm ANDN64 : AndN, EVEX, EVEX_NF, REX_W, Requires<[In64BitMode]>; -} +defm ANDN32 : AndN, VEX, Requires<[HasBMI, NoEGPR]>, DefEFLAGS; +defm ANDN64 : AndN, VEX, REX_W, Requires<[HasBMI, NoEGPR]>, DefEFLAGS; +defm ANDN32 : AndN, EVEX, Requires<[HasBMI, HasEGPR, In64BitMode]>, DefEFLAGS; +defm ANDN64 : AndN, EVEX, REX_W, Requires<[HasBMI, HasEGPR, In64BitMode]>, DefEFLAGS; +defm ANDN32 : AndN, EVEX, EVEX_NF, Requires<[In64BitMode]>; +defm ANDN64 : AndN, EVEX, EVEX_NF, REX_W, Requires<[In64BitMode]>; } multiclass Andn_Pats { From 16b855c4d3dcf5b212f745951edf721ce2ee168b Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Tue, 16 Jan 2024 00:57:09 -0800 Subject: [PATCH 10/12] resolve comments --- llvm/lib/Target/X86/X86InstrArithmetic.td | 4 ++-- llvm/test/MC/Disassembler/X86/apx/andn.txt | 8 ++++---- llvm/test/MC/X86/apx/andn-att.s | 8 ++++---- llvm/test/MC/X86/apx/andn-intel.s | 8 ++++---- 4 files changed, 14 insertions(+), 14 deletions(-) diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td index ae0bc00aacfdb..0fd317bbc3e20 100644 --- a/llvm/lib/Target/X86/X86InstrArithmetic.td +++ b/llvm/lib/Target/X86/X86InstrArithmetic.td @@ -1322,12 +1322,12 @@ multiclass AndN { def rr#suffix : ITy<0xF2, MRMSrcReg, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, t.RegClass:$src2), "andn", binop_ndd_args, andn_rr_p>, VVVV, Sched<[WriteALU]>, - T8; + T8, NoCD8; def rm#suffix : ITy<0xF2, MRMSrcMem, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, t.MemOperand:$src2), "andn", binop_ndd_args, andn_rm_p>, VVVV, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>, - T8; + T8, NoCD8; } // Complexity is reduced to give and with immediate a chance to match first. diff --git a/llvm/test/MC/Disassembler/X86/apx/andn.txt b/llvm/test/MC/Disassembler/X86/apx/andn.txt index 564b1c51920ce..716231181c9ce 100644 --- a/llvm/test/MC/Disassembler/X86/apx/andn.txt +++ b/llvm/test/MC/Disassembler/X86/apx/andn.txt @@ -19,19 +19,19 @@ # ATT: {nf} andnl 123(%rax,%rbx,4), %ecx, %edx # INTEL: {nf} andn edx, ecx, dword ptr [rax + 4*rbx + 123] -0x62,0xf2,0x74,0x0c,0xf2,0x94,0x98,0x7b,0x00,0x00,0x00 +0x62,0xf2,0x74,0x0c,0xf2,0x54,0x98,0x7b # ATT: andnl 123(%rax,%rbx,4), %ecx, %edx # INTEL: andn edx, ecx, dword ptr [rax + 4*rbx + 123] -0x62,0xf2,0x74,0x08,0xf2,0x94,0x98,0x7b,0x00,0x00,0x00 +0x62,0xf2,0x74,0x08,0xf2,0x54,0x98,0x7b # ATT: {nf} andnq 123(%rax,%rbx,4), %r9, %r15 # INTEL: {nf} andn r15, r9, qword ptr [rax + 4*rbx + 123] -0x62,0x72,0xb4,0x0c,0xf2,0xbc,0x98,0x7b,0x00,0x00,0x00 +0x62,0x72,0xb4,0x0c,0xf2,0x7c,0x98,0x7b # ATT: andnq 123(%rax,%rbx,4), %r9, %r15 # INTEL: andn r15, r9, qword ptr [rax + 4*rbx + 123] -0x62,0x72,0xb4,0x08,0xf2,0xbc,0x98,0x7b,0x00,0x00,0x00 +0x62,0x72,0xb4,0x08,0xf2,0x7c,0x98,0x7b # ATT: andnl %r18d, %r22d, %r26d # INTEL: andn r26d, r22d, r18d diff --git a/llvm/test/MC/X86/apx/andn-att.s b/llvm/test/MC/X86/apx/andn-att.s index f6ab0f0069ec0..d072c29987f91 100644 --- a/llvm/test/MC/X86/apx/andn-att.s +++ b/llvm/test/MC/X86/apx/andn-att.s @@ -20,19 +20,19 @@ {evex} andnq %r9, %r15, %r11 # CHECK: {nf} andnl 123(%rax,%rbx,4), %ecx, %edx -# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf2,0x94,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf2,0x54,0x98,0x7b] {nf} andnl 123(%rax,%rbx,4), %ecx, %edx # CHECK: {evex} andnl 123(%rax,%rbx,4), %ecx, %edx -# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf2,0x94,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf2,0x54,0x98,0x7b] {evex} andnl 123(%rax,%rbx,4), %ecx, %edx # CHECK: {nf} andnq 123(%rax,%rbx,4), %r9, %r15 -# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf2,0xbc,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf2,0x7c,0x98,0x7b] {nf} andnq 123(%rax,%rbx,4), %r9, %r15 # CHECK: {evex} andnq 123(%rax,%rbx,4), %r9, %r15 -# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf2,0xbc,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf2,0x7c,0x98,0x7b] {evex} andnq 123(%rax,%rbx,4), %r9, %r15 # CHECK: andnl %r18d, %r22d, %r26d diff --git a/llvm/test/MC/X86/apx/andn-intel.s b/llvm/test/MC/X86/apx/andn-intel.s index 4a369a0d3b689..0adb949f1e29c 100644 --- a/llvm/test/MC/X86/apx/andn-intel.s +++ b/llvm/test/MC/X86/apx/andn-intel.s @@ -17,19 +17,19 @@ {evex} andn r11, r15, r9 # CHECK: {nf} andn edx, ecx, dword ptr [rax + 4*rbx + 123] -# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf2,0x94,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf2,0x54,0x98,0x7b] {nf} andn edx, ecx, dword ptr [rax + 4*rbx + 123] # CHECK: {evex} andn edx, ecx, dword ptr [rax + 4*rbx + 123] -# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf2,0x94,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf2,0x54,0x98,0x7b] {evex} andn edx, ecx, dword ptr [rax + 4*rbx + 123] # CHECK: {nf} andn r15, r9, qword ptr [rax + 4*rbx + 123] -# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf2,0xbc,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf2,0x7c,0x98,0x7b] {nf} andn r15, r9, qword ptr [rax + 4*rbx + 123] # CHECK: {evex} andn r15, r9, qword ptr [rax + 4*rbx + 123] -# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf2,0xbc,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf2,0x7c,0x98,0x7b] {evex} andn r15, r9, qword ptr [rax + 4*rbx + 123] # CHECK: andn r26d, r22d, r18d From e50f216bf3cfd85ca54dc52b4c3f1baac6ca3a9e Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Fri, 19 Jan 2024 01:25:46 -0800 Subject: [PATCH 11/12] update test --- llvm/lib/Target/X86/X86InstrArithmetic.td | 6 ++-- llvm/lib/Target/X86/X86InstrMisc.td | 4 +-- llvm/test/MC/Disassembler/X86/apx/blsi.txt | 8 ++--- llvm/test/MC/Disassembler/X86/apx/blsmsk.txt | 32 ++++++++++++++++++++ llvm/test/MC/Disassembler/X86/apx/blsr.txt | 8 ++--- llvm/test/MC/X86/apx/blsi-att.s | 8 ++--- llvm/test/MC/X86/apx/blsi-intel.s | 8 ++--- llvm/test/MC/X86/apx/blsmsk-att.s | 8 ++--- llvm/test/MC/X86/apx/blsmsk-intel.s | 8 ++--- llvm/test/MC/X86/apx/blsr-att.s | 8 ++--- llvm/test/MC/X86/apx/blsr-intel.s | 8 ++--- 11 files changed, 68 insertions(+), 38 deletions(-) diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td index 0fd317bbc3e20..2b51a94b40513 100644 --- a/llvm/lib/Target/X86/X86InstrArithmetic.td +++ b/llvm/lib/Target/X86/X86InstrArithmetic.td @@ -1321,13 +1321,11 @@ multiclass AndN { (t.LoadNode addr:$src2)))]; def rr#suffix : ITy<0xF2, MRMSrcReg, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, t.RegClass:$src2), "andn", - binop_ndd_args, andn_rr_p>, VVVV, Sched<[WriteALU]>, - T8, NoCD8; + binop_ndd_args, andn_rr_p>, VVVV, Sched<[WriteALU]>, T8; def rm#suffix : ITy<0xF2, MRMSrcMem, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, t.MemOperand:$src2), "andn", binop_ndd_args, andn_rm_p>, VVVV, - Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>, - T8, NoCD8; + Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>, T8; } // Complexity is reduced to give and with immediate a chance to match first. diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td index bcc7c47fb941f..66fac2369d0a9 100644 --- a/llvm/lib/Target/X86/X86InstrMisc.td +++ b/llvm/lib/Target/X86/X86InstrMisc.td @@ -1298,13 +1298,13 @@ multiclass Bmi4VOp3 o, string m, X86TypeInfo t, SDPatternOperator node, let SchedRW = [sched], Form = MRMSrcReg4VOp3 in def rr#Suffix : BinOpRR, T8, NoCD8; + (node t.RegClass:$src1, t.RegClass:$src2))]>, T8; let SchedRW = [sched.Folded, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault, sched.ReadAfterFold], Form = MRMSrcMem4VOp3 in def rm#Suffix : BinOpMR, T8, NoCD8; + t.RegClass:$src2))]>, T8; } let Predicates = [HasBMI, NoEGPR], Defs = [EFLAGS] in { diff --git a/llvm/test/MC/Disassembler/X86/apx/blsi.txt b/llvm/test/MC/Disassembler/X86/apx/blsi.txt index af984a8b7b637..8cb66b1dfd603 100644 --- a/llvm/test/MC/Disassembler/X86/apx/blsi.txt +++ b/llvm/test/MC/Disassembler/X86/apx/blsi.txt @@ -19,19 +19,19 @@ # ATT: {nf} blsil 123(%rax,%rbx,4), %ecx # INTEL: {nf} blsi ecx, dword ptr [rax + 4*rbx + 123] -0x62,0xf2,0x74,0x0c,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00 +0x62,0xf2,0x74,0x0c,0xf3,0x5c,0x98,0x7b # ATT: blsil 123(%rax,%rbx,4), %ecx # INTEL: blsi ecx, dword ptr [rax + 4*rbx + 123] -0x62,0xf2,0x74,0x08,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00 +0x62,0xf2,0x74,0x08,0xf3,0x5c,0x98,0x7b # ATT: {nf} blsiq 123(%rax,%rbx,4), %r9 # INTEL: {nf} blsi r9, qword ptr [rax + 4*rbx + 123] -0x62,0xf2,0xb4,0x0c,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00 +0x62,0xf2,0xb4,0x0c,0xf3,0x5c,0x98,0x7b # ATT: blsiq 123(%rax,%rbx,4), %r9 # INTEL: blsi r9, qword ptr [rax + 4*rbx + 123] -0x62,0xf2,0xb4,0x08,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00 +0x62,0xf2,0xb4,0x08,0xf3,0x5c,0x98,0x7b # ATT: blsil %r18d, %r22d # INTEL: blsi r22d, r18d diff --git a/llvm/test/MC/Disassembler/X86/apx/blsmsk.txt b/llvm/test/MC/Disassembler/X86/apx/blsmsk.txt index 5e47d3d3d625e..fa9aee9a91634 100644 --- a/llvm/test/MC/Disassembler/X86/apx/blsmsk.txt +++ b/llvm/test/MC/Disassembler/X86/apx/blsmsk.txt @@ -1,6 +1,38 @@ # RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT # RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL +# ATT: {nf} blsmskl %ecx, %edx +# INTEL: {nf} blsmsk edx, ecx +0x62,0xf2,0x6c,0x0c,0xf3,0xd1 + +# ATT: blsmskl %ecx, %edx +# INTEL: blsmsk edx, ecx +0x62,0xf2,0x6c,0x08,0xf3,0xd1 + +# ATT: {nf} blsmskq %r9, %r15 +# INTEL: {nf} blsmsk r15, r9 +0x62,0xd2,0x84,0x0c,0xf3,0xd1 + +# ATT: blsmskq %r9, %r15 +# INTEL: blsmsk r15, r9 +0x62,0xd2,0x84,0x08,0xf3,0xd1 + +# ATT: {nf} blsmskl 123(%rax,%rbx,4), %ecx +# INTEL: {nf} blsmsk ecx, dword ptr [rax + 4*rbx + 123] +0x62,0xf2,0x74,0x0c,0xf3,0x54,0x98,0x7b + +# ATT: blsmskl 123(%rax,%rbx,4), %ecx +# INTEL: blsmsk ecx, dword ptr [rax + 4*rbx + 123] +0x62,0xf2,0x74,0x08,0xf3,0x54,0x98,0x7b + +# ATT: {nf} blsmskq 123(%rax,%rbx,4), %r9 +# INTEL: {nf} blsmsk r9, qword ptr [rax + 4*rbx + 123] +0x62,0xf2,0xb4,0x0c,0xf3,0x54,0x98,0x7b + +# ATT: blsmskq 123(%rax,%rbx,4), %r9 +# INTEL: blsmsk r9, qword ptr [rax + 4*rbx + 123] +0x62,0xf2,0xb4,0x08,0xf3,0x54,0x98,0x7b + # ATT: blsmskl %r18d, %r22d # INTEL: blsmsk r22d, r18d 0x62,0xfa,0x4c,0x00,0xf3,0xd2 diff --git a/llvm/test/MC/Disassembler/X86/apx/blsr.txt b/llvm/test/MC/Disassembler/X86/apx/blsr.txt index 6f7874595aa7a..10faa60a23be3 100644 --- a/llvm/test/MC/Disassembler/X86/apx/blsr.txt +++ b/llvm/test/MC/Disassembler/X86/apx/blsr.txt @@ -19,19 +19,19 @@ # ATT: {nf} blsrl 123(%rax,%rbx,4), %ecx # INTEL: {nf} blsr ecx, dword ptr [rax + 4*rbx + 123] -0x62,0xf2,0x74,0x0c,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00 +0x62,0xf2,0x74,0x0c,0xf3,0x4c,0x98,0x7b # ATT: blsrl 123(%rax,%rbx,4), %ecx # INTEL: blsr ecx, dword ptr [rax + 4*rbx + 123] -0x62,0xf2,0x74,0x08,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00 +0x62,0xf2,0x74,0x08,0xf3,0x4c,0x98,0x7b # ATT: {nf} blsrq 123(%rax,%rbx,4), %r9 # INTEL: {nf} blsr r9, qword ptr [rax + 4*rbx + 123] -0x62,0xf2,0xb4,0x0c,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00 +0x62,0xf2,0xb4,0x0c,0xf3,0x4c,0x98,0x7b # ATT: blsrq 123(%rax,%rbx,4), %r9 # INTEL: blsr r9, qword ptr [rax + 4*rbx + 123] -0x62,0xf2,0xb4,0x08,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00 +0x62,0xf2,0xb4,0x08,0xf3,0x4c,0x98,0x7b # ATT: blsrl %r18d, %r22d # INTEL: blsr r22d, r18d diff --git a/llvm/test/MC/X86/apx/blsi-att.s b/llvm/test/MC/X86/apx/blsi-att.s index 9a117e5c0d364..07ca7f37b0385 100644 --- a/llvm/test/MC/X86/apx/blsi-att.s +++ b/llvm/test/MC/X86/apx/blsi-att.s @@ -20,19 +20,19 @@ {evex} blsiq %r9, %r15 # CHECK: {nf} blsil 123(%rax,%rbx,4), %ecx -# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf3,0x5c,0x98,0x7b] {nf} blsil 123(%rax,%rbx,4), %ecx # CHECK: {evex} blsil 123(%rax,%rbx,4), %ecx -# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf3,0x5c,0x98,0x7b] {evex} blsil 123(%rax,%rbx,4), %ecx # CHECK: {nf} blsiq 123(%rax,%rbx,4), %r9 -# CHECK: encoding: [0x62,0xf2,0xb4,0x0c,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0xb4,0x0c,0xf3,0x5c,0x98,0x7b] {nf} blsiq 123(%rax,%rbx,4), %r9 # CHECK: {evex} blsiq 123(%rax,%rbx,4), %r9 -# CHECK: encoding: [0x62,0xf2,0xb4,0x08,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0xb4,0x08,0xf3,0x5c,0x98,0x7b] {evex} blsiq 123(%rax,%rbx,4), %r9 # CHECK: blsil %r18d, %r22d diff --git a/llvm/test/MC/X86/apx/blsi-intel.s b/llvm/test/MC/X86/apx/blsi-intel.s index 54a3c84caf572..6b3c5e613dd84 100644 --- a/llvm/test/MC/X86/apx/blsi-intel.s +++ b/llvm/test/MC/X86/apx/blsi-intel.s @@ -17,19 +17,19 @@ {evex} blsi r15, r9 # CHECK: {nf} blsi ecx, dword ptr [rax + 4*rbx + 123] -# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf3,0x5c,0x98,0x7b] {nf} blsi ecx, dword ptr [rax + 4*rbx + 123] # CHECK: {evex} blsi ecx, dword ptr [rax + 4*rbx + 123] -# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf3,0x5c,0x98,0x7b] {evex} blsi ecx, dword ptr [rax + 4*rbx + 123] # CHECK: {nf} blsi r9, qword ptr [rax + 4*rbx + 123] -# CHECK: encoding: [0x62,0xf2,0xb4,0x0c,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0xb4,0x0c,0xf3,0x5c,0x98,0x7b] {nf} blsi r9, qword ptr [rax + 4*rbx + 123] # CHECK: {evex} blsi r9, qword ptr [rax + 4*rbx + 123] -# CHECK: encoding: [0x62,0xf2,0xb4,0x08,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0xb4,0x08,0xf3,0x5c,0x98,0x7b] {evex} blsi r9, qword ptr [rax + 4*rbx + 123] # CHECK: blsi r22d, r18d diff --git a/llvm/test/MC/X86/apx/blsmsk-att.s b/llvm/test/MC/X86/apx/blsmsk-att.s index fcbaefcc42c8f..a269904901900 100644 --- a/llvm/test/MC/X86/apx/blsmsk-att.s +++ b/llvm/test/MC/X86/apx/blsmsk-att.s @@ -20,19 +20,19 @@ {evex} blsmskq %r9, %r15 # CHECK: {nf} blsmskl 123(%rax,%rbx,4), %ecx -# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf3,0x94,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf3,0x54,0x98,0x7b] {nf} blsmskl 123(%rax,%rbx,4), %ecx # CHECK: {evex} blsmskl 123(%rax,%rbx,4), %ecx -# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf3,0x94,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf3,0x54,0x98,0x7b] {evex} blsmskl 123(%rax,%rbx,4), %ecx # CHECK: {nf} blsmskq 123(%rax,%rbx,4), %r9 -# CHECK: encoding: [0x62,0xf2,0xb4,0x0c,0xf3,0x94,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0xb4,0x0c,0xf3,0x54,0x98,0x7b] {nf} blsmskq 123(%rax,%rbx,4), %r9 # CHECK: {evex} blsmskq 123(%rax,%rbx,4), %r9 -# CHECK: encoding: [0x62,0xf2,0xb4,0x08,0xf3,0x94,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0xb4,0x08,0xf3,0x54,0x98,0x7b] {evex} blsmskq 123(%rax,%rbx,4), %r9 # CHECK: blsmskl %r18d, %r22d diff --git a/llvm/test/MC/X86/apx/blsmsk-intel.s b/llvm/test/MC/X86/apx/blsmsk-intel.s index 168a9cfb6289e..9a04c3dc2d6f6 100644 --- a/llvm/test/MC/X86/apx/blsmsk-intel.s +++ b/llvm/test/MC/X86/apx/blsmsk-intel.s @@ -17,19 +17,19 @@ {evex} blsmsk r15, r9 # CHECK: {nf} blsmsk ecx, dword ptr [rax + 4*rbx + 123] -# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf3,0x94,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf3,0x54,0x98,0x7b] {nf} blsmsk ecx, dword ptr [rax + 4*rbx + 123] # CHECK: {evex} blsmsk ecx, dword ptr [rax + 4*rbx + 123] -# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf3,0x94,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf3,0x54,0x98,0x7b] {evex} blsmsk ecx, dword ptr [rax + 4*rbx + 123] # CHECK: {nf} blsmsk r9, qword ptr [rax + 4*rbx + 123] -# CHECK: encoding: [0x62,0xf2,0xb4,0x0c,0xf3,0x94,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0xb4,0x0c,0xf3,0x54,0x98,0x7b] {nf} blsmsk r9, qword ptr [rax + 4*rbx + 123] # CHECK: {evex} blsmsk r9, qword ptr [rax + 4*rbx + 123] -# CHECK: encoding: [0x62,0xf2,0xb4,0x08,0xf3,0x94,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0xb4,0x08,0xf3,0x54,0x98,0x7b] {evex} blsmsk r9, qword ptr [rax + 4*rbx + 123] # CHECK: blsmsk r22d, r18d diff --git a/llvm/test/MC/X86/apx/blsr-att.s b/llvm/test/MC/X86/apx/blsr-att.s index 40f5d4e4cf68f..35548f3308c57 100644 --- a/llvm/test/MC/X86/apx/blsr-att.s +++ b/llvm/test/MC/X86/apx/blsr-att.s @@ -20,19 +20,19 @@ {evex} blsrq %r9, %r15 # CHECK: {nf} blsrl 123(%rax,%rbx,4), %ecx -# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf3,0x4c,0x98,0x7b] {nf} blsrl 123(%rax,%rbx,4), %ecx # CHECK: {evex} blsrl 123(%rax,%rbx,4), %ecx -# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf3,0x4c,0x98,0x7b] {evex} blsrl 123(%rax,%rbx,4), %ecx # CHECK: {nf} blsrq 123(%rax,%rbx,4), %r9 -# CHECK: encoding: [0x62,0xf2,0xb4,0x0c,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0xb4,0x0c,0xf3,0x4c,0x98,0x7b] {nf} blsrq 123(%rax,%rbx,4), %r9 # CHECK: {evex} blsrq 123(%rax,%rbx,4), %r9 -# CHECK: encoding: [0x62,0xf2,0xb4,0x08,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0xb4,0x08,0xf3,0x4c,0x98,0x7b] {evex} blsrq 123(%rax,%rbx,4), %r9 # CHECK: blsrl %r18d, %r22d diff --git a/llvm/test/MC/X86/apx/blsr-intel.s b/llvm/test/MC/X86/apx/blsr-intel.s index 6d6d475819ee5..ec1d21eb22d86 100644 --- a/llvm/test/MC/X86/apx/blsr-intel.s +++ b/llvm/test/MC/X86/apx/blsr-intel.s @@ -17,19 +17,19 @@ {evex} blsr r15, r9 # CHECK: {nf} blsr ecx, dword ptr [rax + 4*rbx + 123] -# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf3,0x4c,0x98,0x7b] {nf} blsr ecx, dword ptr [rax + 4*rbx + 123] # CHECK: {evex} blsr ecx, dword ptr [rax + 4*rbx + 123] -# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf3,0x4c,0x98,0x7b] {evex} blsr ecx, dword ptr [rax + 4*rbx + 123] # CHECK: {nf} blsr r9, qword ptr [rax + 4*rbx + 123] -# CHECK: encoding: [0x62,0xf2,0xb4,0x0c,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0xb4,0x0c,0xf3,0x4c,0x98,0x7b] {nf} blsr r9, qword ptr [rax + 4*rbx + 123] # CHECK: {evex} blsr r9, qword ptr [rax + 4*rbx + 123] -# CHECK: encoding: [0x62,0xf2,0xb4,0x08,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00] +# CHECK: encoding: [0x62,0xf2,0xb4,0x08,0xf3,0x4c,0x98,0x7b] {evex} blsr r9, qword ptr [rax + 4*rbx + 123] # CHECK: blsr r22d, r18d From b907bbad83e07aef9875d985128bac082c227bb8 Mon Sep 17 00:00:00 2001 From: "Wang, Xin10" Date: Wed, 24 Jan 2024 01:00:35 -0800 Subject: [PATCH 12/12] remove rexw --- llvm/lib/Target/X86/X86InstrArithmetic.td | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td index 2b51a94b40513..fef0a5a90cd6f 100644 --- a/llvm/lib/Target/X86/X86InstrArithmetic.td +++ b/llvm/lib/Target/X86/X86InstrArithmetic.td @@ -1331,11 +1331,11 @@ multiclass AndN { // Complexity is reduced to give and with immediate a chance to match first. let AddedComplexity = -6 in { defm ANDN32 : AndN, VEX, Requires<[HasBMI, NoEGPR]>, DefEFLAGS; -defm ANDN64 : AndN, VEX, REX_W, Requires<[HasBMI, NoEGPR]>, DefEFLAGS; +defm ANDN64 : AndN, VEX, Requires<[HasBMI, NoEGPR]>, DefEFLAGS; defm ANDN32 : AndN, EVEX, Requires<[HasBMI, HasEGPR, In64BitMode]>, DefEFLAGS; -defm ANDN64 : AndN, EVEX, REX_W, Requires<[HasBMI, HasEGPR, In64BitMode]>, DefEFLAGS; +defm ANDN64 : AndN, EVEX, Requires<[HasBMI, HasEGPR, In64BitMode]>, DefEFLAGS; defm ANDN32 : AndN, EVEX, EVEX_NF, Requires<[In64BitMode]>; -defm ANDN64 : AndN, EVEX, EVEX_NF, REX_W, Requires<[In64BitMode]>; +defm ANDN64 : AndN, EVEX, EVEX_NF, Requires<[In64BitMode]>; } multiclass Andn_Pats {