diff --git a/llvm/lib/Target/X86/X86CompressEVEX.cpp b/llvm/lib/Target/X86/X86CompressEVEX.cpp index a9704e30478d1..7191e05178610 100644 --- a/llvm/lib/Target/X86/X86CompressEVEX.cpp +++ b/llvm/lib/Target/X86/X86CompressEVEX.cpp @@ -225,9 +225,12 @@ static bool CompressEVEXImpl(MachineInstr &MI, const X86Subtarget &ST) { // // For AVX512 cases, EVEX prefix is needed in order to carry this information // thus preventing the transformation to VEX encoding. + // MOVBE*rr is special because it has semantic of NDD but not set EVEX_B. + bool IsMovberr = + MI.getOpcode() == X86::MOVBE32rr || MI.getOpcode() == X86::MOVBE64rr; bool IsND = X86II::hasNewDataDest(TSFlags); - if (TSFlags & X86II::EVEX_B) - if (!IsND || !isRedundantNewDataDest(MI, ST)) + if ((TSFlags & X86II::EVEX_B) || IsMovberr) + if (!IsND && !IsMovberr || !isRedundantNewDataDest(MI, ST)) return false; ArrayRef Table = ArrayRef(X86CompressEVEXTable); @@ -239,7 +242,7 @@ static bool CompressEVEXImpl(MachineInstr &MI, const X86Subtarget &ST) { return false; } - if (!IsND) { + if (!IsND && !IsMovberr) { if (usesExtendedRegister(MI) || !checkPredicate(I->NewOpc, &ST) || !performCustomAdjustments(MI, I->NewOpc)) return false; diff --git a/llvm/test/CodeGen/X86/apx/compress-evex.mir b/llvm/test/CodeGen/X86/apx/compress-evex.mir index 5a3d7ceb10c43..997a8395aa752 100644 --- a/llvm/test/CodeGen/X86/apx/compress-evex.mir +++ b/llvm/test/CodeGen/X86/apx/compress-evex.mir @@ -71,3 +71,13 @@ body: | renamable $rax = XOR64rr_NF_ND killed renamable $rax, killed renamable $r16 RET64 $rax ... +--- +name: bswapr_to_movberr +body: | + bb.0.entry: + liveins: $rax + ; CHECK: bswapq %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xc8] + renamable $rax = MOVBE64rr killed renamable $rax + RET64 killed $rax + +... diff --git a/llvm/utils/TableGen/X86ManualCompressEVEXTables.def b/llvm/utils/TableGen/X86ManualCompressEVEXTables.def index 58ca10e9e10f8..77cf65be68425 100644 --- a/llvm/utils/TableGen/X86ManualCompressEVEXTables.def +++ b/llvm/utils/TableGen/X86ManualCompressEVEXTables.def @@ -328,4 +328,6 @@ ENTRY(VBROADCASTSDZ256rm, VBROADCASTSDYrm) ENTRY(VBROADCASTSDZ256rr, VBROADCASTSDYrr) ENTRY(VPBROADCASTQZ256rm, VPBROADCASTQYrm) ENTRY(VPBROADCASTQZ256rr, VPBROADCASTQYrr) +ENTRY(MOVBE32rr, BSWAP32r) +ENTRY(MOVBE64rr, BSWAP64r) #undef ENTRY