diff --git a/mlir/test/Analysis/DataFlow/test-next-access.mlir b/mlir/test/Analysis/DataFlow/test-next-access.mlir index 8825c699dd130..700a23aa8bc40 100644 --- a/mlir/test/Analysis/DataFlow/test-next-access.mlir +++ b/mlir/test/Analysis/DataFlow/test-next-access.mlir @@ -63,7 +63,7 @@ func.func @branch(%arg0: memref, %arg1: f32, %arg2: i1) -> f32 { return %phi : f32 } -// CHECK-LABEL @dead_branch +// CHECK-LABEL: @dead_branch func.func @dead_branch(%arg0: memref, %arg1: f32) -> f32 { // CHECK: name = "store" // CHECK-SAME: next_access = ["unknown", ["load 2"]] @@ -191,7 +191,7 @@ func.func @loop_cf(%arg0: memref, %arg1: f32, %arg2: index, %arg3: index, return %8 : f32 } -// CHECK-LABEL @conditional_cf +// CHECK-LABEL: @conditional_cf func.func @conditional_cf(%arg0: i1, %arg1: memref) { // CHECK: name = "pre" // CHECK-SAME: next_access = {{\[}}["then", "post"]] diff --git a/mlir/test/Conversion/BufferizationToMemRef/bufferization-to-memref.mlir b/mlir/test/Conversion/BufferizationToMemRef/bufferization-to-memref.mlir index 1eb387ce0e5b7..f58a2afa1a896 100644 --- a/mlir/test/Conversion/BufferizationToMemRef/bufferization-to-memref.mlir +++ b/mlir/test/Conversion/BufferizationToMemRef/bufferization-to-memref.mlir @@ -79,7 +79,7 @@ func.func @conversion_dealloc_simple(%arg0: memref<2xf32>, %arg1: i1) { return } -// CHECk: scf.if [[ARG1]] { -// CHECk-NEXT: memref.dealloc [[ARG0]] : memref<2xf32> -// CHECk-NEXT: } -// CHECk-NEXT: return +// CHECK: scf.if [[ARG1]] { +// CHECK-NEXT: memref.dealloc [[ARG0]] : memref<2xf32> +// CHECK-NEXT: } +// CHECK-NEXT: return diff --git a/mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm.mlir b/mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm.mlir index dbf8ead49f78d..1b046d32f163a 100644 --- a/mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm.mlir +++ b/mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm.mlir @@ -778,11 +778,11 @@ func.func @create_tensor_map(%devicePtr2d : memref<64x128xf32>, %devicePtr1d : m %crd0 = arith.constant 64 : index %crd1 = arith.constant 128 : index %devicePtr2d_unranked = memref.cast %devicePtr2d : memref<64x128xf32> to memref<*xf32> - // CHECK : llvm.call @mgpuTensorMapEncodeTiledMemref + // CHECK: llvm.call @mgpuTensorMapEncodeTiledMemref %tensorMap2d = nvgpu.tma.create.descriptor %devicePtr2d_unranked box[%crd0, %crd1] : memref<*xf32> -> !tensorMap2d %devicePtr1d_unranked = memref.cast %devicePtr1d : memref<128xf32> to memref<*xf32> - // CHECK : llvm.call @mgpuTensorMapEncodeTiledMemref + // CHECK: llvm.call @mgpuTensorMapEncodeTiledMemref %tensorMap1d = nvgpu.tma.create.descriptor %devicePtr1d_unranked box[%crd1] : memref<*xf32> -> !tensorMap1d func.return } diff --git a/mlir/test/Conversion/PDLToPDLInterp/pdl-to-pdl-interp-matcher.mlir b/mlir/test/Conversion/PDLToPDLInterp/pdl-to-pdl-interp-matcher.mlir index 92afb765b5ab4..d2abaee149854 100644 --- a/mlir/test/Conversion/PDLToPDLInterp/pdl-to-pdl-interp-matcher.mlir +++ b/mlir/test/Conversion/PDLToPDLInterp/pdl-to-pdl-interp-matcher.mlir @@ -588,7 +588,7 @@ module @variadic_results_all { // CHECK-DAG: %[[OPS:.*]] = pdl_interp.get_users of %[[VAL0]] : !pdl.value // CHECK-DAG: pdl_interp.foreach %[[OP:.*]] : !pdl.operation in %[[OPS]] // CHECK-DAG: %[[OPERANDS:.*]] = pdl_interp.get_operands of %[[OP]] - // CHECK-DAG pdl_interp.are_equal %[[VALS]], %[[OPERANDS]] -> ^{{.*}}, ^[[CONTINUE:.*]] + // CHECK-DAG: pdl_interp.are_equal %[[VALS]], %[[OPERANDS]] -> ^{{.*}}, ^[[CONTINUE:.*]] // CHECK-DAG: pdl_interp.is_not_null %[[OP]] // CHECK-DAG: pdl_interp.check_result_count of %[[OP]] is 0 pdl.pattern @variadic_results_all : benefit(1) { @@ -701,7 +701,7 @@ module @common_connector { // CHECK-DAG: pdl_interp.are_equal %[[ROOTA_OP]], %[[VAL0]] : !pdl.value // CHECK-DAG: %[[ROOTB_OP:.*]] = pdl_interp.get_operand 0 of %[[ROOTB]] // CHECK-DAG: pdl_interp.are_equal %[[ROOTB_OP]], %[[VAL0]] : !pdl.value - // CHECK-DAG } -> ^[[CONTA:.*]] + // CHECK-DAG: } -> ^[[CONTA:.*]] pdl.pattern @common_connector : benefit(1) { %type = type %op = operation -> (%type, %type : !pdl.type, !pdl.type) @@ -742,7 +742,7 @@ module @common_connector_range { // CHECK-DAG: pdl_interp.are_equal %[[ROOTA_OPS]], %[[VALS0]] : !pdl.range // CHECK-DAG: %[[ROOTB_OPS:.*]] = pdl_interp.get_operands of %[[ROOTB]] // CHECK-DAG: pdl_interp.are_equal %[[ROOTB_OPS]], %[[VALS0]] : !pdl.range - // CHECK-DAG } -> ^[[CONTA:.*]] + // CHECK-DAG: } -> ^[[CONTA:.*]] pdl.pattern @common_connector_range : benefit(1) { %types = types %op = operation -> (%types, %types : !pdl.range, !pdl.range) diff --git a/mlir/test/Conversion/SPIRVToLLVM/spirv-storage-class-mapping.mlir b/mlir/test/Conversion/SPIRVToLLVM/spirv-storage-class-mapping.mlir index b9c56a3fcffd0..980406d775d1e 100644 --- a/mlir/test/Conversion/SPIRVToLLVM/spirv-storage-class-mapping.mlir +++ b/mlir/test/Conversion/SPIRVToLLVM/spirv-storage-class-mapping.mlir @@ -91,5 +91,5 @@ spirv.func @pointerCodeSectionINTEL(!spirv.ptr) "None" spirv.func @pointerDeviceOnlyINTEL(!spirv.ptr) "None" // CHECK-OPENCL: llvm.func @pointerHostOnlyINTEL(!llvm.ptr<6>) -// CHECK-UNKOWN: llvm.func @pointerHostOnlyINTEL(!llvm.ptr) +// CHECK-UNKNOWN: llvm.func @pointerHostOnlyINTEL(!llvm.ptr) spirv.func @pointerHostOnlyINTEL(!spirv.ptr) "None" diff --git a/mlir/test/Dialect/Arith/unsigned-when-equivalent.mlir b/mlir/test/Dialect/Arith/unsigned-when-equivalent.mlir index ce77d3d2f4251..49bd74cfe9124 100644 --- a/mlir/test/Dialect/Arith/unsigned-when-equivalent.mlir +++ b/mlir/test/Dialect/Arith/unsigned-when-equivalent.mlir @@ -1,6 +1,6 @@ // RUN: mlir-opt -arith-unsigned-when-equivalent %s | FileCheck %s -// CHECK-LABEL func @not_with_maybe_overflow +// CHECK-LABEL: func @not_with_maybe_overflow // CHECK: arith.divsi // CHECK: arith.ceildivsi // CHECK: arith.floordivsi @@ -32,7 +32,7 @@ func.func @not_with_maybe_overflow(%arg0 : i32) { func.return } -// CHECK-LABEL func @yes_with_no_overflow +// CHECK-LABEL: func @yes_with_no_overflow // CHECK: arith.divui // CHECK: arith.ceildivui // CHECK: arith.divui diff --git a/mlir/test/Dialect/ArmSME/tile-allocation-liveness.mlir b/mlir/test/Dialect/ArmSME/tile-allocation-liveness.mlir index 88fc8a8923d34..fe4c005c7c42f 100644 --- a/mlir/test/Dialect/ArmSME/tile-allocation-liveness.mlir +++ b/mlir/test/Dialect/ArmSME/tile-allocation-liveness.mlir @@ -366,15 +366,15 @@ func.func @avoidable_spill(%a: vector<[4]xf32>, %b: vector<[4]xf32>, %c: vector< // CHECK-LIVE-RANGE-LABEL: @cond_branch_with_backedge // CHECK-LIVE-RANGE: ^bb1: -// CHECK-LIVE-RANGE--NEXT: ||| | arith.cmpi -// CHECK-LIVE-RANGE--NEXT: EEE E cf.cond_br +// CHECK-LIVE-RANGE-NEXT: ||| | arith.cmpi +// CHECK-LIVE-RANGE-NEXT: EEE E cf.cond_br // -// CHECK-LIVE-RANGE--NEXT: ^[[BB3_COPIES:[[:alnum:]]+]]: -// CHECK-LIVE-RANGE--NEXT: ||| ES arm_sme.copy_tile -// CHECK-LIVE-RANGE--NEXT: E|| |S arm_sme.copy_tile -// CHECK-LIVE-RANGE--NEXT: E| ||S arm_sme.copy_tile -// CHECK-LIVE-RANGE--NEXT: E |||S arm_sme.copy_tile -// CHECK-LIVE-RANGE--NEXT: EEEE cf.br +// CHECK-LIVE-RANGE-NEXT: ^[[BB3_COPIES:[[:alnum:]]+]]: +// CHECK-LIVE-RANGE-NEXT: ||| ES arm_sme.copy_tile +// CHECK-LIVE-RANGE-NEXT: E|| |S arm_sme.copy_tile +// CHECK-LIVE-RANGE-NEXT: E| ||S arm_sme.copy_tile +// CHECK-LIVE-RANGE-NEXT: E |||S arm_sme.copy_tile +// CHECK-LIVE-RANGE-NEXT: EEEE cf.br // // It is important to note that the first three live ranges in ^bb1 do not end // at the `cf.cond_br` they are live-out via the backedge bb1 -> bb2 -> bb1. @@ -389,15 +389,15 @@ func.func @avoidable_spill(%a: vector<[4]xf32>, %b: vector<[4]xf32>, %c: vector< // // CHECK-LIVE-RANGE: ========== Coalesced Live Ranges: // CHECK-LIVE-RANGE: ^bb1: -// CHECK-LIVE-RANGE--NEXT: |||| arith.cmpi -// CHECK-LIVE-RANGE--NEXT: EEEE cf.cond_br +// CHECK-LIVE-RANGE-NEXT: |||| arith.cmpi +// CHECK-LIVE-RANGE-NEXT: EEEE cf.cond_br // -// CHECK-LIVE-RANGE--NEXT: ^[[BB3_COPIES]]: -// CHECK-LIVE-RANGE--NEXT: |||| arm_sme.copy_tile -// CHECK-LIVE-RANGE--NEXT: |||| arm_sme.copy_tile -// CHECK-LIVE-RANGE--NEXT: |||| arm_sme.copy_tile -// CHECK-LIVE-RANGE--NEXT: |||| arm_sme.copy_tile -// CHECK-LIVE-RANGE--NEXT: EEEE cf.br +// CHECK-LIVE-RANGE-NEXT: ^[[BB3_COPIES]]: +// CHECK-LIVE-RANGE-NEXT: |||| arm_sme.copy_tile +// CHECK-LIVE-RANGE-NEXT: |||| arm_sme.copy_tile +// CHECK-LIVE-RANGE-NEXT: |||| arm_sme.copy_tile +// CHECK-LIVE-RANGE-NEXT: |||| arm_sme.copy_tile +// CHECK-LIVE-RANGE-NEXT: EEEE cf.br // CHECK-LABEL: @cond_branch_with_backedge // CHECK-NOT: tile_id = 16 diff --git a/mlir/test/Dialect/Bufferization/Transforms/lower-deallocations-func.mlir b/mlir/test/Dialect/Bufferization/Transforms/lower-deallocations-func.mlir index 03cf10aa0c05b..3de3a6a693cfb 100644 --- a/mlir/test/Dialect/Bufferization/Transforms/lower-deallocations-func.mlir +++ b/mlir/test/Dialect/Bufferization/Transforms/lower-deallocations-func.mlir @@ -9,10 +9,10 @@ func.func @conversion_dealloc_simple(%arg0: memref<2xf32>, %arg1: i1) { return } -// CHECk: scf.if [[ARG1]] { -// CHECk-NEXT: memref.dealloc [[ARG0]] : memref<2xf32> -// CHECk-NEXT: } -// CHECk-NEXT: return +// CHECK: scf.if [[ARG1]] { +// CHECK-NEXT: memref.dealloc [[ARG0]] : memref<2xf32> +// CHECK-NEXT: } +// CHECK-NEXT: return // ----- diff --git a/mlir/test/Dialect/Bufferization/Transforms/lower-deallocations.mlir b/mlir/test/Dialect/Bufferization/Transforms/lower-deallocations.mlir index 2c69fcab08a8d..5fedd45555fcd 100644 --- a/mlir/test/Dialect/Bufferization/Transforms/lower-deallocations.mlir +++ b/mlir/test/Dialect/Bufferization/Transforms/lower-deallocations.mlir @@ -29,10 +29,10 @@ func.func @conversion_dealloc_simple(%arg0: memref<2xf32>, %arg1: i1) { return } -// CHECk: scf.if [[ARG1]] { -// CHECk-NEXT: memref.dealloc [[ARG0]] : memref<2xf32> -// CHECk-NEXT: } -// CHECk-NEXT: return +// CHECK: scf.if [[ARG1]] { +// CHECK-NEXT: memref.dealloc [[ARG0]] : memref<2xf32> +// CHECK-NEXT: } +// CHECK-NEXT: return // ----- diff --git a/mlir/test/Dialect/GPU/barrier-elimination.mlir b/mlir/test/Dialect/GPU/barrier-elimination.mlir index 844dc7dd6ac00..1f5b84937deb0 100644 --- a/mlir/test/Dialect/GPU/barrier-elimination.mlir +++ b/mlir/test/Dialect/GPU/barrier-elimination.mlir @@ -61,7 +61,7 @@ func.func @write_in_a_loop(%arg0: memref, %arg1: f32) attributes {__paral return } -// CHECK-LABEL @read_read_write_loop +// CHECK-LABEL: @read_read_write_loop func.func @read_read_write_loop(%arg0: memref, %arg1: f32) attributes {__parallel_region_boundary_for_test} { %c0 = arith.constant 0 : index %c42 = arith.constant 42 : index diff --git a/mlir/test/Dialect/GPU/ops.mlir b/mlir/test/Dialect/GPU/ops.mlir index 511b018877476..ba7897f4e80cb 100644 --- a/mlir/test/Dialect/GPU/ops.mlir +++ b/mlir/test/Dialect/GPU/ops.mlir @@ -227,7 +227,7 @@ module attributes {gpu.container_module} { gpu.return } - // CHECK-LABEL gpu.func @printf_test + // CHECK-LABEL: gpu.func @printf_test // CHECK: (%[[ARG0:.*]]: i32) // CHECK: gpu.printf "Value: %d" %[[ARG0]] : i32 gpu.func @printf_test(%arg0 : i32) { diff --git a/mlir/test/Dialect/GPU/outlining.mlir b/mlir/test/Dialect/GPU/outlining.mlir index 5e4724c9d309c..47ebe326b5d12 100644 --- a/mlir/test/Dialect/GPU/outlining.mlir +++ b/mlir/test/Dialect/GPU/outlining.mlir @@ -123,7 +123,7 @@ llvm.func @launch_from_llvm_func() { llvm.return } -// CHECK-DL-LABLE: gpu.module @launch_from_llvm_func_kernel attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry>} +// CHECK-DL-LABEL: gpu.module @launch_from_llvm_func_kernel attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry>} // ----- diff --git a/mlir/test/Dialect/LLVMIR/nvvm.mlir b/mlir/test/Dialect/LLVMIR/nvvm.mlir index de2904d15b647..a7bdceba01c1e 100644 --- a/mlir/test/Dialect/LLVMIR/nvvm.mlir +++ b/mlir/test/Dialect/LLVMIR/nvvm.mlir @@ -464,24 +464,24 @@ llvm.func private @mbarrier_test_wait_shared(%barrier: !llvm.ptr<3>, %token : i6 llvm.return } -// CHECK-LABEL : @wgmma_fence_aligned +// CHECK-LABEL: @wgmma_fence_aligned func.func @wgmma_fence_aligned() { - // CHECK : nvvm.wgmma.fence.aligned + // CHECK: nvvm.wgmma.fence.aligned nvvm.wgmma.fence.aligned return } -// CHECK-LABEL : @wgmma_commit_group_sync_aligned +// CHECK-LABEL: @wgmma_commit_group_sync_aligned func.func @wgmma_commit_group_sync_aligned() { - // CHECK : nvvm.wgmma.commit.group.sync.aligned + // CHECK: nvvm.wgmma.commit.group.sync.aligned nvvm.wgmma.commit.group.sync.aligned return } -// CHECK-LABEL : @wgmma_commit_group_sync_aligned +// CHECK-LABEL: @wgmma_wait_group_sync_aligned func.func @wgmma_wait_group_sync_aligned() { - // CHECK : nvvm.wgmma.wait.group.sync.aligned + // CHECK: nvvm.wgmma.wait.group.sync.aligned nvvm.wgmma.wait.group.sync.aligned 0 return } @@ -495,7 +495,7 @@ gpu.module @module_1 [#nvvm.target, #nvvm.target, #nvvm.target] { } -// CHECK-LABEL : nvvm.grid_constant +// CHECK-LABEL: nvvm.grid_constant llvm.func @kernel_func(%arg0: !llvm.ptr {llvm.byval = i32, nvvm.grid_constant}) attributes {nvvm.kernel} { llvm.return } diff --git a/mlir/test/Dialect/Linalg/data-layout-propagation.mlir b/mlir/test/Dialect/Linalg/data-layout-propagation.mlir index bee08503298fd..9140904620acd 100644 --- a/mlir/test/Dialect/Linalg/data-layout-propagation.mlir +++ b/mlir/test/Dialect/Linalg/data-layout-propagation.mlir @@ -795,7 +795,7 @@ func.func @reduction_pack_transpose_inner_dims(%arg0: tensor<128x256x32xi32>, // CHECK-SAME: %[[ARG1:[a-zA-Z0-9]+]] // CHECK: %[[ARG1_EMPTY:.+]] = tensor.empty() : tensor<4x16x16x32xi32> // CHECK: %[[PACK_ARG1:.+]] = tensor.pack %[[ARG1]] -// CHECK-SME: inner_dims_pos = [1, 0] inner_tiles = [16, 32] +// CHECK-SAME: inner_dims_pos = [1, 0] inner_tiles = [16, 32] // CHECK-SAME: into %[[ARG1_EMPTY]] // CHECK: %[[ARG0_EMPTY:.+]] = tensor.empty() : tensor<4x16x32x16x32xi32> // CHECK: %[[PACK_ARG0:.+]] = tensor.pack %[[ARG0]] diff --git a/mlir/test/Dialect/Math/expand-math.mlir b/mlir/test/Dialect/Math/expand-math.mlir index 016a7bbdeb569..c10a78ca4ae4c 100644 --- a/mlir/test/Dialect/Math/expand-math.mlir +++ b/mlir/test/Dialect/Math/expand-math.mlir @@ -221,7 +221,7 @@ func.func @roundf_func(%a: f32) -> f32 { // CHECK-LABEL: func @powf_func // CHECK-SAME: ([[ARG0:%.+]]: f64, [[ARG1:%.+]]: f64) func.func @powf_func(%a: f64, %b: f64) ->f64 { - // CHECK-DAG = [[CST0:%.+]] = arith.constant 0.000000e+00 + // CHECK-DAG: [[CST0:%.+]] = arith.constant 0.000000e+00 // CHECK-DAG: [[TWO:%.+]] = arith.constant 2.000000e+00 // CHECK-DAG: [[NEGONE:%.+]] = arith.constant -1.000000e+00 // CHECK-DAG: [[SQR:%.+]] = arith.mulf [[ARG0]], [[ARG0]] diff --git a/mlir/test/Dialect/SCF/transform-ops.mlir b/mlir/test/Dialect/SCF/transform-ops.mlir index f4b0db7fb1f92..a4daa86583c3d 100644 --- a/mlir/test/Dialect/SCF/transform-ops.mlir +++ b/mlir/test/Dialect/SCF/transform-ops.mlir @@ -6,11 +6,11 @@ // CHECK: scf.for // CHECK: arith.addi // -// CHECK: func @foo[[SUFFIX:.+]](%{{.+}}, %{{.+}}, %{{.+}}) +// CHECK: func @foo[[$SUFFIX:.+]](%{{.+}}, %{{.+}}, %{{.+}}) // CHECK: scf.for // CHECK: arith.addi // -// CHECK-LABEL @loop_outline_op +// CHECK-LABEL: @loop_outline_op func.func @loop_outline_op(%arg0: index, %arg1: index, %arg2: index) { // CHECK: scf.for // CHECK-NOT: scf.for @@ -23,7 +23,7 @@ func.func @loop_outline_op(%arg0: index, %arg1: index, %arg2: index) { } // CHECK: scf.execute_region // CHECK-NOT: scf.for - // CHECK: func.call @foo[[SUFFIX]] + // CHECK: func.call @foo[[$SUFFIX]] scf.for %j = %arg0 to %arg1 step %arg2 { arith.addi %j, %j : index } diff --git a/mlir/test/Dialect/SPIRV/IR/logical-ops.mlir b/mlir/test/Dialect/SPIRV/IR/logical-ops.mlir index 7dc0bd99f54b3..5c24f0e6a7d33 100644 --- a/mlir/test/Dialect/SPIRV/IR/logical-ops.mlir +++ b/mlir/test/Dialect/SPIRV/IR/logical-ops.mlir @@ -180,7 +180,7 @@ func.func @logicalUnary(%arg0 : i32) func.func @select_op_bool(%arg0: i1) -> () { %0 = spirv.Constant true %1 = spirv.Constant false - // CHECK : spirv.Select {{%.*}}, {{%.*}}, {{%.*}} : i1, i1 + // CHECK: spirv.Select {{%.*}}, {{%.*}}, {{%.*}} : i1, i1 %2 = spirv.Select %arg0, %0, %1 : i1, i1 return } @@ -188,7 +188,7 @@ func.func @select_op_bool(%arg0: i1) -> () { func.func @select_op_int(%arg0: i1) -> () { %0 = spirv.Constant 2 : i32 %1 = spirv.Constant 3 : i32 - // CHECK : spirv.Select {{%.*}}, {{%.*}}, {{%.*}} : i1, i32 + // CHECK: spirv.Select {{%.*}}, {{%.*}}, {{%.*}} : i1, i32 %2 = spirv.Select %arg0, %0, %1 : i1, i32 return } @@ -196,7 +196,7 @@ func.func @select_op_int(%arg0: i1) -> () { func.func @select_op_float(%arg0: i1) -> () { %0 = spirv.Constant 2.0 : f32 %1 = spirv.Constant 3.0 : f32 - // CHECK : spirv.Select {{%.*}}, {{%.*}}, {{%.*}} : i1, f32 + // CHECK: spirv.Select {{%.*}}, {{%.*}}, {{%.*}} : i1, f32 %2 = spirv.Select %arg0, %0, %1 : i1, f32 return } @@ -204,7 +204,7 @@ func.func @select_op_float(%arg0: i1) -> () { func.func @select_op_ptr(%arg0: i1) -> () { %0 = spirv.Variable : !spirv.ptr %1 = spirv.Variable : !spirv.ptr - // CHECK : spirv.Select {{%.*}}, {{%.*}}, {{%.*}} : i1, !spirv.ptr + // CHECK: spirv.Select {{%.*}}, {{%.*}}, {{%.*}} : i1, !spirv.ptr %2 = spirv.Select %arg0, %0, %1 : i1, !spirv.ptr return } @@ -212,7 +212,7 @@ func.func @select_op_ptr(%arg0: i1) -> () { func.func @select_op_vec(%arg0: i1) -> () { %0 = spirv.Constant dense<[2.0, 3.0, 4.0]> : vector<3xf32> %1 = spirv.Constant dense<[5.0, 6.0, 7.0]> : vector<3xf32> - // CHECK : spirv.Select {{%.*}}, {{%.*}}, {{%.*}} : i1, vector<3xf32> + // CHECK: spirv.Select {{%.*}}, {{%.*}}, {{%.*}} : i1, vector<3xf32> %2 = spirv.Select %arg0, %0, %1 : i1, vector<3xf32> return } @@ -220,7 +220,7 @@ func.func @select_op_vec(%arg0: i1) -> () { func.func @select_op_vec_condn_vec(%arg0: vector<3xi1>) -> () { %0 = spirv.Constant dense<[2.0, 3.0, 4.0]> : vector<3xf32> %1 = spirv.Constant dense<[5.0, 6.0, 7.0]> : vector<3xf32> - // CHECK : spirv.Select {{%.*}}, {{%.*}}, {{%.*}} : vector<3xi1>, vector<3xf32> + // CHECK: spirv.Select {{%.*}}, {{%.*}}, {{%.*}} : vector<3xi1>, vector<3xf32> %2 = spirv.Select %arg0, %0, %1 : vector<3xi1>, vector<3xf32> return } diff --git a/mlir/test/Dialect/SPIRV/IR/structure-ops.mlir b/mlir/test/Dialect/SPIRV/IR/structure-ops.mlir index db0f52dcc40ed..1eed5892a0857 100644 --- a/mlir/test/Dialect/SPIRV/IR/structure-ops.mlir +++ b/mlir/test/Dialect/SPIRV/IR/structure-ops.mlir @@ -330,7 +330,7 @@ spirv.module Logical GLSL450 { // TODO: Fix test case after initialization with normal constant is addressed // spirv.module Logical GLSL450 { // %0 = spirv.Constant 4.0 : f32 -// // CHECK1: spirv.Variable init(%0) : !spirv.ptr +// COM: CHECK: spirv.Variable init(%0) : !spirv.ptr // spirv.GlobalVariable @var1 init(%0) : !spirv.ptr // } @@ -372,7 +372,7 @@ spirv.module Logical GLSL450 { // TODO: Fix test case after initialization with constant is addressed // spirv.module Logical GLSL450 { // %0 = spirv.Constant 4.0 : f32 -// // CHECK1: spirv.GlobalVariable @var1 initializer(%0) {binding = 5 : i32} : !spirv.ptr +// COM: CHECK: spirv.GlobalVariable @var1 initializer(%0) {binding = 5 : i32} : !spirv.ptr // spirv.GlobalVariable @var1 initializer(%0) {binding = 5 : i32} : !spirv.ptr // } diff --git a/mlir/test/Dialect/Tensor/fold-into-pack-and-unpack.mlir b/mlir/test/Dialect/Tensor/fold-into-pack-and-unpack.mlir index 9f486f9146ad8..9a3143f5e550e 100644 --- a/mlir/test/Dialect/Tensor/fold-into-pack-and-unpack.mlir +++ b/mlir/test/Dialect/Tensor/fold-into-pack-and-unpack.mlir @@ -544,7 +544,7 @@ func.func @linalg_transpose_tensor_unpack_fold(%arg0: tensor<1x1x4x16xi32>) -> t // CHECK-SAME: outer_dims_perm = [1, 0] // CHECK-SAME: inner_dims_pos = [1, 0] // CHECK-SAME: inner_tiles = [4, 16] -// CHEKC-SAME: into %[[OUT]] : tensor<1x1x4x16xi32> -> tensor<16x4xi32> +// CHECK-SAME: into %[[OUT]] : tensor<1x1x4x16xi32> -> tensor<16x4xi32> // CHECK: return %[[UNPACK]] : tensor<16x4xi32> // CHECK: } diff --git a/mlir/test/IR/parser.mlir b/mlir/test/IR/parser.mlir index 020942e7f4c11..bcc146ea0101b 100644 --- a/mlir/test/IR/parser.mlir +++ b/mlir/test/IR/parser.mlir @@ -597,7 +597,7 @@ func.func @funcattrwithblock() -> () return } -// CHECK-label func @funcsimplemap +// CHECK-LABEL: func @funcsimplemap #map_simple0 = affine_map<()[] -> (10)> #map_simple1 = affine_map<()[s0] -> (s0)> #map_non_simple0 = affine_map<(d0)[] -> (d0)> diff --git a/mlir/test/Target/LLVMIR/Import/global-variables.ll b/mlir/test/Target/LLVMIR/Import/global-variables.ll index 9d9734045988a..902f77bd7e6cb 100644 --- a/mlir/test/Target/LLVMIR/Import/global-variables.ll +++ b/mlir/test/Target/LLVMIR/Import/global-variables.ll @@ -36,7 +36,7 @@ ; CHECK-DAG: %[[ADDR:[0-9]+]] = llvm.mlir.addressof @global_int : !llvm.ptr ; CHECK-DAG: %[[IDX:[0-9]+]] = llvm.mlir.constant(2 : i32) : i32 ; CHECK-DAG: %[[GEP:[0-9]+]] = llvm.getelementptr %[[ADDR]][%[[IDX]]] : (!llvm.ptr, i32) -> !llvm.ptr -; CHECK-DAG llvm.return %[[GEP]] : !llvm.ptr +; CHECK-DAG: llvm.return %[[GEP]] : !llvm.ptr @global_gep_const_expr = internal constant ptr getelementptr (i32, ptr @global_int, i32 2) ; // ----- diff --git a/mlir/test/Target/LLVMIR/Import/metadata-loop.ll b/mlir/test/Target/LLVMIR/Import/metadata-loop.ll index 3516101a2367d..20431a7412bd1 100644 --- a/mlir/test/Target/LLVMIR/Import/metadata-loop.ll +++ b/mlir/test/Target/LLVMIR/Import/metadata-loop.ll @@ -324,7 +324,7 @@ end: ; // ----- ; Verify the unused access group is not imported. -; CHECK-COUNT1: #llvm.access_group +; CHECK-COUNT-1: #llvm.access_group ; CHECK-LABEL: @unused_parallel_access define void @unused_parallel_access(ptr %arg) { diff --git a/mlir/test/Target/LLVMIR/llvmir-debug.mlir b/mlir/test/Target/LLVMIR/llvmir-debug.mlir index 1cb94bca169db..2792f13e4ef8f 100644 --- a/mlir/test/Target/LLVMIR/llvmir-debug.mlir +++ b/mlir/test/Target/LLVMIR/llvmir-debug.mlir @@ -234,7 +234,7 @@ llvm.func @func_with_inlined_dbg_value(%arg0: i32) -> (i32) { // CHECK-DAG: ![[LEXICAL_BLOCK_FILE:.*]] = distinct !DILexicalBlockFile(scope: ![[INNER_FUNC]], file: ![[FILE]], discriminator: 0) // CHECK-DAG: ![[VAR_LOC0]] = !DILocalVariable(name: "a", scope: ![[OUTER_FUNC]], file: ![[FILE]] // CHECK-DAG: ![[VAR_LOC1]] = !DILocalVariable(name: "b", scope: ![[LEXICAL_BLOCK_FILE]], file: ![[FILE]] -// CHECK-DAG ![[LABEL]] = !DILabel(scope: ![[LEXICAL_BLOCK_FILE]], name: "label", file: ![[FILE]], line: 42) +// CHECK-DAG: ![[LABEL]] = !DILabel(scope: ![[LEXICAL_BLOCK_FILE]], name: "label", file: ![[FILE]], line: 42) // ----- diff --git a/mlir/test/Target/LLVMIR/omptarget-array-sectioning-host.mlir b/mlir/test/Target/LLVMIR/omptarget-array-sectioning-host.mlir index 08ccbf04014a9..0016a1f05a2b1 100644 --- a/mlir/test/Target/LLVMIR/omptarget-array-sectioning-host.mlir +++ b/mlir/test/Target/LLVMIR/omptarget-array-sectioning-host.mlir @@ -42,7 +42,7 @@ module attributes {omp.is_target_device = false} { // CHECK: @.offload_sizes = private unnamed_addr constant [2 x i64] [i64 36, i64 108] // CHECK: @.offload_maptypes = private unnamed_addr constant [2 x i64] [i64 35, i64 35] -// CHECKL: @.offload_mapnames = private constant [2 x ptr] [ptr @0, ptr @1] +// CHECK: @.offload_mapnames = private constant [2 x ptr] [ptr @0, ptr @1] // CHECK: define void @_3d_target_array_section() diff --git a/mlir/test/python/dialects/transform_structured_ext.py b/mlir/test/python/dialects/transform_structured_ext.py index 935534edba7a6..f97017b7a2c75 100644 --- a/mlir/test/python/dialects/transform_structured_ext.py +++ b/mlir/test/python/dialects/transform_structured_ext.py @@ -443,7 +443,7 @@ def testTileExplicitLoopTypeAll(target): structured.TileUsingForOp(types, target, sizes=[2, 3, 4]) # CHECK-LABEL: TEST: testTileExplicitLoopTypeAll # CHECK: = transform.structured.tile - # CHECK-SAME : (!transform.any_op) -> (!transform.any_op, !transform.op<"scf.for">, + # CHECK-SAME: (!transform.any_op) -> (!transform.any_op, !transform.op<"scf.for">, # CHECK-SAME: !transform.op<"scf.parallel">, !transform.op<"scf.forall">