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EarlGrey

Supported version

Earlgrey 1.0.0

Supported devices

Near feature-complete devices

  • AES
  • Alert controller
    • ping mechanism is not supported
  • AON Timer
  • CSRNG
  • EDN
  • Flash controller
    • largely functional but without ECCs/ICVs, scrambling functionality & alerts
    • no modelling of erase suspend or RMA entry
    • lc_ctrl NVM debug signal not implemented, escalation partially implemented
  • HMAC
  • IBEX CPU
  • Key manager
    • Almost feature complete
    • Missing entropy reseeding, and support for KMAC masking (when available)
  • OTBN
  • OTP controller
    • read and write features are supported,
    • Present scrambling is supported with digest checks,
    • ECC (detection and correction) is supported
  • ROM controller
  • SPI data flash (from QEMU upstream w/ fixes)
  • SPI Host controller
    • HW bus config is ignored (SPI mode, speed, ...)
  • SPI Device
  • Timer
  • UART
    • missing RX timeout, TX break not supported
    • bitrate is not paced vs. selected baurate

Partially implemented devices

Devices in this group implement subset(s) of the real HW.

  • Clock Manager
    • Runtime-configurable device, through properties
    • Manage clock dividers, groups, hints, software configurable clocks
    • Propagate clock signals from source (AST, ...) to devices
    • Hint management and measurement are not implemented
  • Entropy Src
    • test/health features are not supported
  • I2C controller
    • Supports only one target mode address - ADDRESS1 and MASK1 are not implemented
    • Timing features are not implemented
    • Loopback mode is not implemented
  • Ibex wrapper
    • random source (connected to CSR), FPGA version, virtual remapper, fetch enable can be controlled from Power Manager
  • KMAC
    • Masking is not supported
  • Lifecycle controller
    • LC controller can be accessed through JTAG using a DM-TL bridge
  • ROM controller
  • SRAM controller
    • Initialization and scrambling from OTP key supported
    • Wait for init completion (bus stall) emulated
  • USB Device

Sparsely implemented devices

In this group, device CSRs are supported (w/ partial or full access control & masking) but only some features are implemented.

  • Analog Sensor Top
    • noise source only (from host source)
    • configurable clock sources
  • GPIO
    • Connections with pinmux not implemented (need to be ported from Darjeeling version)
  • Power Manager
    • Fast FSM is partially supported, Slow FSM is bypassed
    • Interactions with other devices (such as the Reset Manager) are limited
  • Reset Manager
    • HW and SW reset requests are supported

Dummy devices

Devices in this group are mostly implemented with a RAM backend or real CSRs but do not implement any useful feature (only allow guest test code to execute as expected). Some just use generic UNIMP devices to define a memory region.

  • Pattern Generator
  • Pinmux
  • PWM
  • Sensor Control
  • System Reset Controller

Running the virtual machine

See OpenTitan machine documentation for options.

Arbitrary application

qemu-system-riscv32 -M ot-earlgrey,no_epmp_cfg=true -display none -serial mon:stdio \
  -readconfig docs/config/opentitan/earlgrey.cfg \
  -global ot-ibex_wrapper.lc-ignore=on  -kernel hello.elf

Boot sequence ROM, ROM_EXT, BLO

qemu-system-riscv32 -M ot-earlgrey -display none -serial mon:stdio \
  -readconfig docs/config/opentitan/earlgrey.cfg \
  -object ot-rom_img,id=rom,file=rom_with_fake_keys_fpga_cw310.elf \
  -drive if=pflash,file=otp-rma.raw,format=raw \
  -drive if=mtd,bus=2,file=flash.raw,format=raw

where otp-rma.raw contains the RMA OTP image and flash.raw contains the signed binary file of the ROM_EXT and the BL0. See otptool.py and flashgen.py tools to generate the .raw image files.

Buses

EarlGrey emulation supports the following buses:

Type Num Usage
mtd 0 SPI host 0, SPI device
mtd 1 SPI host 1
mtd 2 Embedded Flash
pflash 0 OTP

Tools

See tools.md

Useful debugging options

See debug option for details.