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24 | 24 | |---|---|---|---|---|---|---|---|---| |
25 | 25 | | NVIDIA CUDA | `FLAGOS_ACCELERATOR=cuda` (default) | CUDA boxing over an external `libtorch_cuda.so` | Stable | Experimental (inductor GPU device registered; no CI test step) | Beta (FlagCX + NCCL fallback, DDP live-verified) | Stable (CUPTI parity) | Beta (Python + C++ dispatch paths) | Stable | |
26 | 26 | | MetaX | `FLAGOS_ACCELERATOR=metax` | CUDA boxing via `cu-bridge` against the vendor libtorch | Stable (FP16/BF16 autocast and GradScaler measured in boxing mode) | Experimental (vendor Triton and FlagTree MetaX measured on C550; vendor Triton CI-covered) | Experimental (NCCL-shaped `mccl` fallback; not CI-covered) | Experimental (MCPTI parity measured on C550; not CI-covered) | Experimental (Python dispatch; not CI-tested on MetaX) | Stable | |
27 | | -| Ascend | `FLAGOS_ACCELERATOR=ascend` | Native ACLNN operator backend, FlagGems via FlagTree (Triton 3.5) | Stable (CI-covered ops, RNG suite) | Experimental (inductor measured on 910 against triton-ascend 3.2.0 only; **not** revalidated on FlagTree, three toolchain workarounds, serial compile, no CI step) | Experimental (HCCL fallback; architectural routing only, no collective-level CI) | Beta (MSPTI kernel/runtime/flow/memcpy events CI-covered by the shared contract; device-time linkage misattributes to the following allocation op, #425; parity suite excluded from CI) | Beta (Python dispatch; FlagGems-first conf, float64 and bool `neg` routes fall back to ACLNN) | Beta | |
| 27 | +| Ascend | `FLAGOS_ACCELERATOR=ascend` | Native ACLNN operator backend, FlagGems via FlagTree (Triton 3.5) | Stable (CI-covered ops, RNG suite) | Experimental (inductor measured on 910 against triton-ascend 3.2.0 only; **not** revalidated on FlagTree, three toolchain workarounds, serial compile, no CI step) | Experimental (HCCL fallback; architectural routing only, no collective-level CI) | Beta (MSPTI kernel/runtime/flow/memcpy events plus device-time linkage, all CI-covered by the shared contract; parity suite excluded from CI) | Beta (Python dispatch; FlagGems-first conf, float64 and bool `neg` routes fall back to ACLNN) | Beta | |
28 | 28 | | PPU | `FLAGOS_ACCELERATOR=ppu` | Same CUDA-boxing path as NVIDIA CUDA, against the PPU's CUDA-13-compatible SDK, bundling its own libtorch | Experimental (FP16/BF16 autocast and GradScaler measured on PPU hardware, not in CI) | Not validated | Experimental (NCCL fallback via vendor-adapted `libnccl.so.2`; not CI-covered) | Not validated on this vendor's tracer | Experimental (vendor-index Triton required) | Experimental | |
29 | 29 | | Hygon DCU | `FLAGOS_ACCELERATOR=dcu` | CUDA boxing over the hipified DTK torch build (HIP kernels under the CUDA dispatch key) | Beta (including FP16/BF16 autocast and GradScaler) | Experimental (FlagTree HCU validated on `gfx936`; not in CI) | Experimental (RCCL via DTK; all_reduce/DDP measured on 2 cards, not in CI) | Beta (parity suite runs in CI) | Beta (Python dispatch only) | Beta | |
30 | 30 | | Enflame GCU | `FLAGOS_ACCELERATOR=gcu` | Native `libtopsaten.so` operator backend, with CPU fallback for unrouted/int64/float64 ops | Beta (operator, RNG, factory, and AMP suites CI-guarded on S60) | Not validated | Not validated | Runtime only (TOPSPTI collects activities; no device events on a CPU-only Kineto build) | Experimental (Python dispatch, requires vendor Triton) | Beta | |
@@ -107,13 +107,17 @@ still out of scope — `test_profiler_parity.py` is a diff against a torch-cuda |
107 | 107 | only the CUDA-boxing platforms can run one — and remains excluded from CI (same file, lines |
108 | 108 | 112-117). The shared profiler *contract* does run, and the device side of it is live: MSPTI |
109 | 109 | emits named kernel, runtime/API, flow, and (under the process-start preload above) memcpy |
110 | | -activity, and the step was measured on 910 at `10 passed, 1 skipped, 1 xfailed`. The skip is |
| 110 | +activity, and the step was measured on 910 at `11 passed, 1 skipped`. The skip is |
111 | 111 | `gpu_memset`, a correct-by-design consequence of routing `torch.zeros()` through |
112 | 112 | `aclnnInplaceZero` rather than the allocator (see |
113 | | -[`docs/architecture/profiler.md`](../architecture/profiler.md)). The xfail is device-time |
114 | | -linkage: Ascend attributes each device event to the CPU op that follows its launch, so the |
115 | | -launching operator reads zero self device time while the allocation op that follows absorbs |
116 | | -it (issue #425). Distributed support recommends the FlagCX path (see |
| 113 | +[`docs/architecture/profiler.md`](../architecture/profiler.md)). The device-time |
| 114 | +linkage case is one of the eleven that assert: MSPTI used to stamp every launch with |
| 115 | +the id of the CPU op that started after it, which turned out to be this repository's |
| 116 | +defect rather than the vendor's — `popCorrelation` passed a null out-parameter, which |
| 117 | +CANN rejects without unwinding, so the external-correlation stack grew for the life of |
| 118 | +the process (issue #425). With the pop fixed, the launching |
| 119 | +operator owns its device events and the case asserts on this platform. Distributed support |
| 120 | +recommends the FlagCX path (see |
117 | 121 | [`docs/architecture/distributed-flagcx.md`](../architecture/distributed-flagcx.md), lines |
118 | 122 | 204-208); the native HCCL fallback and the `flagos→npu` zero-copy view are architectural |
119 | 123 | routing, not on-hardware-verified collectives (same file, lines 67-75). |
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